1 files changed, 69 insertions, 21 deletions
diff --git a/plugins/arm/v7/opdefs/mul_A88114.d b/plugins/arm/v7/opdefs/mul_A88114.d
index fa250b7..25e6736 100644
--- a/plugins/arm/v7/opdefs/mul_A88114.d
+++ b/plugins/arm/v7/opdefs/mul_A88114.d
@@ -2,7 +2,7 @@
 /* Chrysalide - Outil d'analyse de fichiers binaires
  * ##FILE## - traduction d'instructions ARMv7
  *
- * Copyright (C) 2015 Cyrille Bagard
+ * Copyright (C) 2017 Cyrille Bagard
  *
  *  This file is part of Chrysalide.
  *
@@ -23,19 +23,29 @@
 
 @title MUL
 
-@desc Multiply multiplies two register values. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values. Optionally, it can update the condition flags based on the result. In the Thumb instruction set, this option is limited to only a few forms of the instruction. Use of this option adversely affects performance on many processor implementations.
+@id 113
+
+@desc {
+
+	Multiply multiplies two register values. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values. Optionally, it can update the condition flags based on the result. In the Thumb instruction set, this option is limited to only a few forms of the instruction. Use of this option adversely affects performance on many processor implementations.
+
+}
 
 @encoding (t1) {
 
 	@half 0 1 0 0 0 0 1 1 0 1 Rn(3) Rdm(3)
 
-	@syntax "muls" <reg_DM_1> <reg_N> <reg_DM_2>
+	@syntax {
 
-	@conv {
+		@conv {
 
-		reg_N = Register(Rn)
-		reg_DM_1 = Register(Rdm)
-		reg_DM_2 = Register(Rdm)
+			reg_D = Register(Rdm)
+			reg_N = Register(Rn)
+			reg_M = Register(Rdm)
+
+		}
+
+		@asm mul reg_D reg_N ?reg_M
 
 	}
 
@@ -45,13 +55,17 @@
 
 	@word 1 1 1 1 1 0 1 1 0 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4)
 
-	@syntax <reg_D> <reg_N> <reg_M>
+	@syntax {
+
+		@conv {
 
-	@conv {
+			reg_D = Register(Rd)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
 
-		reg_D = Register(Rd)
-		reg_N = Register(Rn)
-		reg_M = Register(Rm)
+		}
+
+		@asm mul reg_D reg_N ?reg_M
 
 	}
 
@@ -61,21 +75,55 @@
 
 	@word cond(4) 0 0 0 0 0 0 0 S(1) Rd(4) 0 0 0 0 Rm(4) 1 0 0 1 Rn(4)
 
-	@syntax <reg_D> <reg_N> <reg_M>
+	@syntax {
+
+		@assert {
+
+			S == 0
+
+		}
+
+		@conv {
+
+			reg_D = Register(Rd)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
 
-	@conv {
+		}
 
-		reg_D = Register(Rd)
-		reg_N = Register(Rn)
-		reg_M = Register(Rm)
-		setflags = (S == '1')
+		@asm mul reg_D reg_N ?reg_M
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
 
 	}
 
-	@rules {
+	@syntax {
+
+		@assert {
+
+			S == 1
+
+		}
+
+		@conv {
+
+			reg_D = Register(Rd)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
+
+		}
+
+		@asm muls reg_D reg_N ?reg_M
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
 
-		if (setflags); chk_call ExtendKeyword("s")
-		chk_call StoreCondition(cond)
+		}
 
 	}