diff options
Diffstat (limited to 'plugins/arm/v7/opdefs/orn_A88121.d')
| -rw-r--r-- | plugins/arm/v7/opdefs/orn_A88121.d | 52 |
1 files changed, 41 insertions, 11 deletions
diff --git a/plugins/arm/v7/opdefs/orn_A88121.d b/plugins/arm/v7/opdefs/orn_A88121.d index f1523ec..5b32f94 100644 --- a/plugins/arm/v7/opdefs/orn_A88121.d +++ b/plugins/arm/v7/opdefs/orn_A88121.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,27 +23,57 @@ @title ORN (register) -@desc Bitwise OR NOT (register) performs a bitwise (inclusive) OR of a register value and the complement of an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 120 + +@desc { + + Bitwise OR NOT (register) performs a bitwise (inclusive) OR of a register value and the complement of an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (T1) { @word 1 1 1 0 1 0 1 0 0 1 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) + } + + @asm orn ?reg_D reg_N reg_M ?shift } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } - if (setflags); chk_call ExtendKeyword("s") + @asm orns ?reg_D reg_N reg_M ?shift } |