1 files changed, 82 insertions, 19 deletions
diff --git a/plugins/arm/v7/opdefs/orr_A88122.d b/plugins/arm/v7/opdefs/orr_A88122.d
index 766b5ee..8b159ad 100644
--- a/plugins/arm/v7/opdefs/orr_A88122.d
+++ b/plugins/arm/v7/opdefs/orr_A88122.d
@@ -2,7 +2,7 @@
 /* Chrysalide - Outil d'analyse de fichiers binaires
  * ##FILE## - traduction d'instructions ARMv7
  *
- * Copyright (C) 2015 Cyrille Bagard
+ * Copyright (C) 2017 Cyrille Bagard
  *
  *  This file is part of Chrysalide.
  *
@@ -23,26 +23,55 @@
 
 @title ORR (immediate)
 
-@desc Bitwise OR (immediate) performs a bitwise (inclusive) OR of a register value and an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result.
+@id 121
+
+@desc {
+
+	Bitwise OR (immediate) performs a bitwise (inclusive) OR of a register value and an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result.
+
+}
 
 @encoding (T1) {
 
 	@word 1 1 1 1 0 i(1) 0 0 0 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8)
 
-	@syntax <reg_D> <reg_N> <imm32>
+	@syntax {
+
+		@assert {
+
+			S == 0
+
+		}
+
+		@conv {
 
-	@conv {
+			reg_D = Register(Rd)
+			reg_N = Register(Rn)
+			const = ThumbExpandImm_C(i:imm3:imm8, APSR_C)
 
-		reg_D = Register(Rd)
-		reg_N = Register(Rn)
-		setflags = (S == '1')
-		imm32 = ThumbExpandImm_C(i:imm3:imm8, 0)
+		}
+
+		@asm orr ?reg_D reg_N const
 
 	}
 
-	@rules {
+	@syntax {
+
+		@assert {
+
+			S == 1
+
+		}
 
-		if (setflags); chk_call ExtendKeyword("s")
+		@conv {
+
+			reg_D = Register(Rd)
+			reg_N = Register(Rn)
+			const = ThumbExpandImm_C(i:imm3:imm8, APSR_C)
+
+		}
+
+		@asm orrs ?reg_D reg_N const
 
 	}
 
@@ -52,21 +81,55 @@
 
 	@word cond(4) 0 0 1 1 1 0 0 S(1) Rn(4) Rd(4) imm12(12)
 
-	@syntax <reg_D> <reg_N> <imm32>
+	@syntax {
+
+		@assert {
 
-	@conv {
+			S == 0
 
-		reg_D = Register(Rd)
-		reg_N = Register(Rn)
-		setflags = (S == '1')
-		imm32 = ARMExpandImm_C(imm12, 0)
+		}
+
+		@conv {
+
+			reg_D = Register(Rd)
+			reg_N = Register(Rn)
+			const = ARMExpandImm_C(imm12, APSR_C)
+
+		}
+
+		@asm orr ?reg_D reg_N const
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
 
 	}
 
-	@rules {
+	@syntax {
+
+		@assert {
+
+			S == 1
+
+		}
+
+		@conv {
+
+			reg_D = Register(Rd)
+			reg_N = Register(Rn)
+			const = ARMExpandImm_C(imm12, APSR_C)
+
+		}
+
+		@asm orrs ?reg_D reg_N const
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
 
-		if (setflags); chk_call ExtendKeyword("s")
-		chk_call StoreCondition(cond)
+		}
 
 	}