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-rw-r--r--plugins/arm/v7/opdefs/push_A88133.d72
1 files changed, 49 insertions, 23 deletions
diff --git a/plugins/arm/v7/opdefs/push_A88133.d b/plugins/arm/v7/opdefs/push_A88133.d
index 14fc3e9..aa7fe56 100644
--- a/plugins/arm/v7/opdefs/push_A88133.d
+++ b/plugins/arm/v7/opdefs/push_A88133.d
@@ -2,7 +2,7 @@
/* Chrysalide - Outil d'analyse de fichiers binaires
* ##FILE## - traduction d'instructions ARMv7
*
- * Copyright (C) 2015 Cyrille Bagard
+ * Copyright (C) 2017 Cyrille Bagard
*
* This file is part of Chrysalide.
*
@@ -23,17 +23,27 @@
@title PUSH
-@desc Push Multiple Registers stores multiple registers to the stack, storing to consecutive memory locations ending just below the address in SP, and updates SP to point to the start of the stored data.
+@id 132
+
+@desc {
+
+ Push Multiple Registers stores multiple registers to the stack, storing to consecutive memory locations ending just below the address in SP, and updates SP to point to the start of the stored data.
+
+}
@encoding (t1) {
@half 1 0 1 1 0 1 0 M(1) register_list(8)
- @syntax <registers>
+ @syntax {
- @conv {
+ @conv {
- registers = RegistersList('0':M:'000000':register_list)
+ registers = RegList('0':M:'000000':register_list)
+
+ }
+
+ @asm push registers
}
@@ -43,11 +53,15 @@
@word 1 1 1 0 1 0 0 1 0 0 1 0 1 1 0 1 0 M(1) 0 register_list(13)
- @syntax ".W" <registers>
+ @syntax {
+
+ @conv {
+
+ registers = RegList('0':M:'0':register_list)
- @conv {
+ }
- registers = RegistersList('0':M:'0':register_list)
+ @asm push.w registers
}
@@ -57,11 +71,15 @@
@word 1 1 1 1 1 0 0 0 0 1 0 0 1 1 0 1 Rt(4) 1 1 0 1 0 0 0 0 0 1 0 0
- @syntax ".W" <registers>
+ @syntax {
- @conv {
+ @conv {
- registers = Zeros(16)
+ registers = SingleRegList(Rt)
+
+ }
+
+ @asm push.w registers
}
@@ -71,17 +89,21 @@
@word cond(4) 1 0 0 1 0 0 1 0 1 1 0 1 register_list(16)
- @syntax <registers>
+ @syntax {
- @conv {
+ @conv {
- registers = RegistersList(register_list)
+ registers = RegList(register_list)
- }
+ }
+
+ @asm push registers
- @rules {
+ @rules {
- chk_call StoreCondition(cond)
+ check g_arm_instruction_set_cond(cond)
+
+ }
}
@@ -91,17 +113,21 @@
@word cond(4) 0 1 0 1 0 0 1 0 1 1 0 1 Rt(4) 0 0 0 0 0 0 0 0 0 1 0 0
- @syntax <registers>
+ @syntax {
- @conv {
+ @conv {
- registers = Zeros(16)
+ registers = SingleRegList(Rt)
- }
+ }
+
+ @asm push registers
+
+ @rules {
- @rules {
+ check g_arm_instruction_set_cond(cond)
- chk_call StoreCondition(cond)
+ }
}