1 files changed, 78 insertions, 17 deletions
diff --git a/plugins/arm/v7/opdefs/rrx_A88151.d b/plugins/arm/v7/opdefs/rrx_A88151.d
index 4debd42..d73570b 100644
--- a/plugins/arm/v7/opdefs/rrx_A88151.d
+++ b/plugins/arm/v7/opdefs/rrx_A88151.d
@@ -2,7 +2,7 @@
 /* Chrysalide - Outil d'analyse de fichiers binaires
  * ##FILE## - traduction d'instructions ARMv7
  *
- * Copyright (C) 2015 Cyrille Bagard
+ * Copyright (C) 2017 Cyrille Bagard
  *
  *  This file is part of Chrysalide.
  *
@@ -23,25 +23,53 @@
 
 @title RRX
 
-@desc Rotate Right with Extend provides the value of the contents of a register shifted right by one place, with the Carry flag shifted into bit[31]. RRX can optionally update the condition flags based on the result. In that case, bit[0] is shifted into the Carry flag.
+@id 150
+
+@desc {
+
+	Rotate Right with Extend provides the value of the contents of a register shifted right by one place, with the Carry flag shifted into bit[31]. RRX can optionally update the condition flags based on the result. In that case, bit[0] is shifted into the Carry flag.
+
+}
 
 @encoding (T1) {
 
 	@word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 0 0 0 Rd(4) 0 0 1 1 Rm(4)
 
-	@syntax <reg_D> <reg_M>
+	@syntax {
+
+		@assert {
+
+			S == 0
+
+		}
+
+		@conv {
 
-	@conv {
+			reg_D = Register(Rd)
+			reg_M = Register(Rm)
 
-		reg_D = Register(Rd)
-		reg_M = Register(Rm)
-		setflags = (S == '1')
+		}
+
+		@asm rrx ?reg_D reg_M
 
 	}
 
-	@rules {
+	@syntax {
+
+		@assert {
+
+			S == 1
+
+		}
 
-		if (setflags); chk_call ExtendKeyword("s")
+		@conv {
+
+			reg_D = Register(Rd)
+			reg_M = Register(Rm)
+
+		}
+
+		@asm rrxs ?reg_D reg_M
 
 	}
 
@@ -51,20 +79,53 @@
 
 	@word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) 0 0 0 0 0 1 1 0 Rm(4)
 
-	@syntax <reg_D> <reg_M>
+	@syntax {
+
+		@assert {
 
-	@conv {
+			S == 0
 
-		reg_D = Register(Rd)
-		reg_M = Register(Rm)
-		setflags = (S == '1')
+		}
+
+		@conv {
+
+			reg_D = Register(Rd)
+			reg_M = Register(Rm)
+
+		}
+
+		@asm rrx ?reg_D reg_M
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
 
 	}
 
-	@rules {
+	@syntax {
+
+		@assert {
+
+			S == 1
+
+		}
+
+		@conv {
+
+			reg_D = Register(Rd)
+			reg_M = Register(Rm)
+
+		}
+
+		@asm rrxs ?reg_D reg_M
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
 
-		if (setflags); chk_call ExtendKeyword("s")
-		chk_call StoreCondition(cond)
+		}
 
 	}