diff options
Diffstat (limited to 'plugins/arm/v7/opdefs/rsb_A88152.d')
| -rw-r--r-- | plugins/arm/v7/opdefs/rsb_A88152.d | 116 |
1 files changed, 91 insertions, 25 deletions
diff --git a/plugins/arm/v7/opdefs/rsb_A88152.d b/plugins/arm/v7/opdefs/rsb_A88152.d index ea53373..0bf4eee 100644 --- a/plugins/arm/v7/opdefs/rsb_A88152.d +++ b/plugins/arm/v7/opdefs/rsb_A88152.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title RSB (immediate) -@desc Reverse Subtract (immediate) subtracts a register value from an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 151 + +@desc { + + Reverse Subtract (immediate) subtracts a register value from an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 1 0 0 1 Rn(3) Rd(3) - @syntax "rsbs" <reg_D> <reg_N> <imm32> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = Zeros(32) - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = Zeros(32) + } + + @asm rsb ?reg_D reg_N imm32 } @@ -45,21 +55,43 @@ @word 1 1 1 1 0 i(1) 0 1 1 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ThumbExpandImm(i:imm3:imm8) + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm rsb.w ?reg_D reg_N imm32 } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm rsbs.w ?reg_D reg_N imm32 } @@ -69,21 +101,55 @@ @word cond(4) 0 0 1 0 0 1 1 S(1) Rn(4) Rd(4) imm12(12) - @syntax <reg_D> <reg_N> <imm32> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ARMExpandImm(imm12) + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm rsb ?reg_D reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm rsbs ?reg_D reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } |