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Diffstat (limited to 'plugins/arm/v7/opdefs/sdiv_A88165.d')
-rw-r--r--plugins/arm/v7/opdefs/sdiv_A88165.d44
1 files changed, 29 insertions, 15 deletions
diff --git a/plugins/arm/v7/opdefs/sdiv_A88165.d b/plugins/arm/v7/opdefs/sdiv_A88165.d
index 19ebfa9..762b49a 100644
--- a/plugins/arm/v7/opdefs/sdiv_A88165.d
+++ b/plugins/arm/v7/opdefs/sdiv_A88165.d
@@ -2,7 +2,7 @@
/* Chrysalide - Outil d'analyse de fichiers binaires
* ##FILE## - traduction d'instructions ARMv7
*
- * Copyright (C) 2015 Cyrille Bagard
+ * Copyright (C) 2017 Cyrille Bagard
*
* This file is part of Chrysalide.
*
@@ -23,19 +23,29 @@
@title SDIV
-@desc Signed Divide divides a 32-bit signed integer register value by a 32-bit signed integer register value, and writes the result to the destination register. The condition flags are not affected. See ARMv7 implementation requirements and options for the divide instructions on page A4-172 for more information about this instruction.
+@id 164
+
+@desc {
+
+ Signed Divide divides a 32-bit signed integer register value by a 32-bit signed integer register value, and writes the result to the destination register. The condition flags are not affected. See ARMv7 implementation requirements and options for the divide instructions on page A4-172 for more information about this instruction.
+
+}
@encoding (T1) {
@word 1 1 1 1 1 0 1 1 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 1 1 1 1 Rm(4)
- @syntax <reg_D> <reg_N> <reg_M>
+ @syntax {
+
+ @conv {
- @conv {
+ reg_D = Register(Rd)
+ reg_N = Register(Rn)
+ reg_M = Register(Rm)
- reg_D = Register(Rd)
- reg_N = Register(Rn)
- reg_M = Register(Rm)
+ }
+
+ @asm sdiv ?reg_D reg_N reg_M
}
@@ -45,19 +55,23 @@
@word cond(4) 0 1 1 1 0 0 0 1 Rd(4) 1 1 1 1 Rm(4) 0 0 0 1 Rn(4)
- @syntax <reg_D> <reg_N> <reg_M>
+ @syntax {
- @conv {
+ @conv {
- reg_D = Register(Rd)
- reg_N = Register(Rn)
- reg_M = Register(Rm)
+ reg_D = Register(Rd)
+ reg_N = Register(Rn)
+ reg_M = Register(Rm)
- }
+ }
+
+ @asm sdiv ?reg_D reg_N reg_M
+
+ @rules {
- @rules {
+ check g_arm_instruction_set_cond(cond)
- chk_call StoreCondition(cond)
+ }
}