1 files changed, 63 insertions, 18 deletions
diff --git a/plugins/arm/v7/opdefs/smlal_A88178.d b/plugins/arm/v7/opdefs/smlal_A88178.d
index 03da53c..0b79de9 100644
--- a/plugins/arm/v7/opdefs/smlal_A88178.d
+++ b/plugins/arm/v7/opdefs/smlal_A88178.d
@@ -2,7 +2,7 @@
 /* Chrysalide - Outil d'analyse de fichiers binaires
  * ##FILE## - traduction d'instructions ARMv7
  *
- * Copyright (C) 2015 Cyrille Bagard
+ * Copyright (C) 2017 Cyrille Bagard
  *
  *  This file is part of Chrysalide.
  *
@@ -23,20 +23,30 @@
 
 @title SMLAL
 
-@desc Signed Multiply Accumulate Long multiplies two signed 32-bit values to produce a 64-bit value, and accumulates this with a 64-bit value. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations.
+@id 177
+
+@desc {
+
+	Signed Multiply Accumulate Long multiplies two signed 32-bit values to produce a 64-bit value, and accumulates this with a 64-bit value. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations.
+
+}
 
 @encoding (T1) {
 
 	@word 1 1 1 1 1 0 1 1 1 1 0 0 Rn(4) RdLo(4) RdHi(4) 0 0 0 0 Rm(4)
 
-	@syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M>
+	@syntax {
+
+		@conv {
+
+			reg_DLO = Register(RdLo)
+			reg_DHI = Register(RdHi)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
 
-	@conv {
+		}
 
-		reg_DLO = Register(RdLo)
-		reg_DHI = Register(RdHi)
-		reg_N = Register(Rn)
-		reg_M = Register(Rm)
+		@asm smlal reg_DLO reg_DHI reg_N reg_M
 
 	}
 
@@ -46,22 +56,57 @@
 
 	@word cond(4) 0 0 0 0 1 1 1 S(1) RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4)
 
-	@syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M>
+	@syntax {
+
+		@assert {
+
+			S == 0
+
+		}
+
+		@conv {
+
+			reg_DLO = Register(RdLo)
+			reg_DHI = Register(RdHi)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
+
+		}
 
-	@conv {
+		@asm smlal reg_DLO reg_DHI reg_N reg_M
 
-		reg_DLO = Register(RdLo)
-		reg_DHI = Register(RdHi)
-		reg_N = Register(Rn)
-		reg_M = Register(Rm)
-		setflags = (S == '1')
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
 
 	}
 
-	@rules {
+	@syntax {
+
+		@assert {
+
+			S == 1
+
+		}
+
+		@conv {
+
+			reg_DLO = Register(RdLo)
+			reg_DHI = Register(RdHi)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
+
+		}
+
+		@asm smlals reg_DLO reg_DHI reg_N reg_M
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
 
-		if (setflags); chk_call ExtendKeyword("s")
-		chk_call StoreCondition(cond)
+		}
 
 	}