1 files changed, 86 insertions, 21 deletions
diff --git a/plugins/arm/v7/opdefs/smlald_A88180.d b/plugins/arm/v7/opdefs/smlald_A88180.d
index fa6a473..16353d2 100644
--- a/plugins/arm/v7/opdefs/smlald_A88180.d
+++ b/plugins/arm/v7/opdefs/smlald_A88180.d
@@ -2,7 +2,7 @@
 /* Chrysalide - Outil d'analyse de fichiers binaires
  * ##FILE## - traduction d'instructions ARMv7
  *
- * Copyright (C) 2015 Cyrille Bagard
+ * Copyright (C) 2017 Cyrille Bagard
  *
  *  This file is part of Chrysalide.
  *
@@ -23,27 +23,57 @@
 
 @title SMLALD
 
-@desc Signed Multiply Accumulate Long Dual performs two signed 16 × 16-bit multiplications. It adds the products to a 64-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. Overflow is possible during this instruction, but only as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo 264.
+@id 179
+
+@desc {
+
+	Signed Multiply Accumulate Long Dual performs two signed 16 × 16-bit multiplications. It adds the products to a 64-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. Overflow is possible during this instruction, but only as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo 264.
+
+}
 
 @encoding (T1) {
 
 	@word 1 1 1 1 1 0 1 1 1 1 0 0 Rn(4) RdLo(4) RdHi(4) 1 1 0 M(1) Rm(4)
 
-	@syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M>
+	@syntax {
+
+		@assert {
+
+			M == 0
+
+		}
+
+		@conv {
 
-	@conv {
+			reg_DLO = Register(RdLo)
+			reg_DHI = Register(RdHi)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
 
-		reg_DLO = Register(RdLo)
-		reg_DHI = Register(RdHi)
-		reg_N = Register(Rn)
-		reg_M = Register(Rm)
-		m_swap = (M == '1')
+		}
+
+		@asm smlald reg_DLO reg_DHI reg_N reg_M
 
 	}
 
-	@rules {
+	@syntax {
+
+		@assert {
+
+			M == 1
+
+		}
 
-		if (m_swap); chk_call ExtendKeyword("x")
+		@conv {
+
+			reg_DLO = Register(RdLo)
+			reg_DHI = Register(RdHi)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
+
+		}
+
+		@asm smlaldx reg_DLO reg_DHI reg_N reg_M
 
 	}
 
@@ -53,22 +83,57 @@
 
 	@word cond(4) 0 1 1 1 0 1 0 0 RdHi(4) RdLo(4) Rm(4) 0 0 M(1) 1 Rn(4)
 
-	@syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M>
+	@syntax {
+
+		@assert {
 
-	@conv {
+			M == 0
 
-		reg_DLO = Register(RdLo)
-		reg_DHI = Register(RdHi)
-		reg_N = Register(Rn)
-		reg_M = Register(Rm)
-		m_swap = (M == '1')
+		}
+
+		@conv {
+
+			reg_DLO = Register(RdLo)
+			reg_DHI = Register(RdHi)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
+
+		}
+
+		@asm smlald reg_DLO reg_DHI reg_N reg_M
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
 
 	}
 
-	@rules {
+	@syntax {
+
+		@assert {
+
+			M == 1
+
+		}
+
+		@conv {
+
+			reg_DLO = Register(RdLo)
+			reg_DHI = Register(RdHi)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
+
+		}
+
+		@asm smlaldx reg_DLO reg_DHI reg_N reg_M
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
 
-		if (m_swap); chk_call ExtendKeyword("x")
-		chk_call StoreCondition(cond)
+		}
 
 	}