1 files changed, 86 insertions, 21 deletions
diff --git a/plugins/arm/v7/opdefs/smlsd_A88182.d b/plugins/arm/v7/opdefs/smlsd_A88182.d
index d458fa8..5808518 100644
--- a/plugins/arm/v7/opdefs/smlsd_A88182.d
+++ b/plugins/arm/v7/opdefs/smlsd_A88182.d
@@ -2,7 +2,7 @@
 /* Chrysalide - Outil d'analyse de fichiers binaires
  * ##FILE## - traduction d'instructions ARMv7
  *
- * Copyright (C) 2015 Cyrille Bagard
+ * Copyright (C) 2017 Cyrille Bagard
  *
  *  This file is part of Chrysalide.
  *
@@ -23,27 +23,57 @@
 
 @title SMLSD
 
-@desc Signed Multiply Subtract Dual performs two signed 16 × 16-bit multiplications. It adds the difference of the products to a 32-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. This instruction sets the Q flag if the accumulate operation overflows. Overflow cannot occur during the multiplications or subtraction.
+@id 181
+
+@desc {
+
+	Signed Multiply Subtract Dual performs two signed 16 × 16-bit multiplications. It adds the difference of the products to a 32-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. This instruction sets the Q flag if the accumulate operation overflows. Overflow cannot occur during the multiplications or subtraction.
+
+}
 
 @encoding (T1) {
 
 	@word 1 1 1 1 1 0 1 1 0 1 0 0 Rn(4) Ra(4) Rd(4) 0 0 0 M(1) Rm(4)
 
-	@syntax <reg_D> <reg_N> <reg_M> <reg_A>
+	@syntax {
+
+		@assert {
+
+			M == 0
+
+		}
+
+		@conv {
 
-	@conv {
+			reg_D = Register(Rd)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
+			reg_A = Register(Ra)
 
-		reg_D = Register(Rd)
-		reg_N = Register(Rn)
-		reg_M = Register(Rm)
-		reg_A = Register(Ra)
-		m_swap = (M == '1')
+		}
+
+		@asm smlsd reg_D reg_N reg_M reg_A
 
 	}
 
-	@rules {
+	@syntax {
+
+		@assert {
+
+			M == 1
+
+		}
 
-		if (m_swap); chk_call ExtendKeyword("x")
+		@conv {
+
+			reg_D = Register(Rd)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
+			reg_A = Register(Ra)
+
+		}
+
+		@asm smlsdx reg_D reg_N reg_M reg_A
 
 	}
 
@@ -53,22 +83,57 @@
 
 	@word cond(4) 0 1 1 1 0 0 0 0 Rd(4) Ra(4) Rm(4) 0 1 M(1) 1 Rn(4)
 
-	@syntax <reg_D> <reg_N> <reg_M> <reg_A>
+	@syntax {
+
+		@assert {
 
-	@conv {
+			M == 0
 
-		reg_D = Register(Rd)
-		reg_N = Register(Rn)
-		reg_M = Register(Rm)
-		reg_A = Register(Ra)
-		m_swap = (M == '1')
+		}
+
+		@conv {
+
+			reg_D = Register(Rd)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
+			reg_A = Register(Ra)
+
+		}
+
+		@asm smlsd reg_D reg_N reg_M reg_A
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
 
 	}
 
-	@rules {
+	@syntax {
+
+		@assert {
+
+			M == 1
+
+		}
+
+		@conv {
+
+			reg_D = Register(Rd)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
+			reg_A = Register(Ra)
+
+		}
+
+		@asm smlsdx reg_D reg_N reg_M reg_A
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
 
-		if (m_swap); chk_call ExtendKeyword("x")
-		chk_call StoreCondition(cond)
+		}
 
 	}