1 files changed, 86 insertions, 21 deletions
diff --git a/plugins/arm/v7/opdefs/smmla_A88184.d b/plugins/arm/v7/opdefs/smmla_A88184.d
index a4d29b8..40bd005 100644
--- a/plugins/arm/v7/opdefs/smmla_A88184.d
+++ b/plugins/arm/v7/opdefs/smmla_A88184.d
@@ -2,7 +2,7 @@
 /* Chrysalide - Outil d'analyse de fichiers binaires
  * ##FILE## - traduction d'instructions ARMv7
  *
- * Copyright (C) 2015 Cyrille Bagard
+ * Copyright (C) 2017 Cyrille Bagard
  *
  *  This file is part of Chrysalide.
  *
@@ -23,27 +23,57 @@
 
 @title SMMLA
 
-@desc Signed Most Significant Word Multiply Accumulate multiplies two signed 32-bit values, extracts the most significant 32 bits of the result, and adds an accumulate value. Optionally, the instruction can specify that the result is rounded instead of being truncated. In this case, the constant 0x80000000 is added to the product before the high word is extracted.
+@id 183
+
+@desc {
+
+	Signed Most Significant Word Multiply Accumulate multiplies two signed 32-bit values, extracts the most significant 32 bits of the result, and adds an accumulate value. Optionally, the instruction can specify that the result is rounded instead of being truncated. In this case, the constant 0x80000000 is added to the product before the high word is extracted.
+
+}
 
 @encoding (T1) {
 
 	@word 1 1 1 1 1 0 1 1 0 1 0 1 Rn(4) Ra(4) Rd(4) 0 0 0 R(1) Rm(4)
 
-	@syntax <reg_D> <reg_N> <reg_M> <reg_A>
+	@syntax {
+
+		@assert {
+
+			R == 0
+
+		}
+
+		@conv {
 
-	@conv {
+			reg_D = Register(Rd)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
+			reg_A = Register(Ra)
 
-		reg_D = Register(Rd)
-		reg_N = Register(Rn)
-		reg_M = Register(Rm)
-		reg_A = Register(Ra)
-		round = (R == '1')
+		}
+
+		@asm smmla reg_D reg_N reg_M reg_A
 
 	}
 
-	@rules {
+	@syntax {
+
+		@assert {
+
+			R == 1
+
+		}
 
-		if (round); chk_call ExtendKeyword("r")
+		@conv {
+
+			reg_D = Register(Rd)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
+			reg_A = Register(Ra)
+
+		}
+
+		@asm smmlar reg_D reg_N reg_M reg_A
 
 	}
 
@@ -53,22 +83,57 @@
 
 	@word cond(4) 0 1 1 1 0 1 0 1 Rd(4) Ra(4) Rm(4) 0 0 R(1) 1 Rn(4)
 
-	@syntax <reg_D> <reg_N> <reg_M> <reg_A>
+	@syntax {
+
+		@assert {
 
-	@conv {
+			R == 0
 
-		reg_D = Register(Rd)
-		reg_N = Register(Rn)
-		reg_M = Register(Rm)
-		reg_A = Register(Ra)
-		round = (R == '1')
+		}
+
+		@conv {
+
+			reg_D = Register(Rd)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
+			reg_A = Register(Ra)
+
+		}
+
+		@asm smmla reg_D reg_N reg_M reg_A
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
 
 	}
 
-	@rules {
+	@syntax {
+
+		@assert {
+
+			R == 1
+
+		}
+
+		@conv {
+
+			reg_D = Register(Rd)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
+			reg_A = Register(Ra)
+
+		}
+
+		@asm smmlar reg_D reg_N reg_M reg_A
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
 
-		if (round); chk_call ExtendKeyword("r")
-		chk_call StoreCondition(cond)
+		}
 
 	}