1 files changed, 82 insertions, 19 deletions
diff --git a/plugins/arm/v7/opdefs/smmul_A88186.d b/plugins/arm/v7/opdefs/smmul_A88186.d
index e02ca52..44a8b9b 100644
--- a/plugins/arm/v7/opdefs/smmul_A88186.d
+++ b/plugins/arm/v7/opdefs/smmul_A88186.d
@@ -2,7 +2,7 @@
 /* Chrysalide - Outil d'analyse de fichiers binaires
  * ##FILE## - traduction d'instructions ARMv7
  *
- * Copyright (C) 2015 Cyrille Bagard
+ * Copyright (C) 2017 Cyrille Bagard
  *
  *  This file is part of Chrysalide.
  *
@@ -23,26 +23,55 @@
 
 @title SMMUL
 
-@desc Signed Most Significant Word Multiply multiplies two signed 32-bit values, extracts the most significant 32 bits of the result, and writes those bits to the destination register. Optionally, the instruction can specify that the result is rounded instead of being truncated. In this case, the constant 0x80000000 is added to the product before the high word is extracted.
+@id 185
+
+@desc {
+
+	Signed Most Significant Word Multiply multiplies two signed 32-bit values, extracts the most significant 32 bits of the result, and writes those bits to the destination register. Optionally, the instruction can specify that the result is rounded instead of being truncated. In this case, the constant 0x80000000 is added to the product before the high word is extracted.
+
+}
 
 @encoding (T1) {
 
 	@word 1 1 1 1 1 0 1 1 0 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 R(1) Rm(4)
 
-	@syntax <reg_D> <reg_N> <reg_M>
+	@syntax {
+
+		@assert {
+
+			R == 0
+
+		}
+
+		@conv {
 
-	@conv {
+			reg_D = Register(Rd)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
 
-		reg_D = Register(Rd)
-		reg_N = Register(Rn)
-		reg_M = Register(Rm)
-		round = (R == '1')
+		}
+
+		@asm smmul ?reg_D reg_N reg_M
 
 	}
 
-	@rules {
+	@syntax {
+
+		@assert {
+
+			R == 1
+
+		}
 
-		if (round); chk_call ExtendKeyword("r")
+		@conv {
+
+			reg_D = Register(Rd)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
+
+		}
+
+		@asm smmulr ?reg_D reg_N reg_M
 
 	}
 
@@ -52,21 +81,55 @@
 
 	@word cond(4) 0 1 1 1 0 1 0 1 Rd(4) 1 1 1 1 Rm(4) 0 0 R(1) 1 Rn(4)
 
-	@syntax <reg_D> <reg_N> <reg_M>
+	@syntax {
+
+		@assert {
 
-	@conv {
+			R == 0
 
-		reg_D = Register(Rd)
-		reg_N = Register(Rn)
-		reg_M = Register(Rm)
-		round = (R == '1')
+		}
+
+		@conv {
+
+			reg_D = Register(Rd)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
+
+		}
+
+		@asm smmul ?reg_D reg_N reg_M
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
 
 	}
 
-	@rules {
+	@syntax {
+
+		@assert {
+
+			R == 1
+
+		}
+
+		@conv {
+
+			reg_D = Register(Rd)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
+
+		}
+
+		@asm smmulr ?reg_D reg_N reg_M
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
 
-		if (round); chk_call ExtendKeyword("r")
-		chk_call StoreCondition(cond)
+		}
 
 	}