1 files changed, 82 insertions, 19 deletions
diff --git a/plugins/arm/v7/opdefs/smuad_A88187.d b/plugins/arm/v7/opdefs/smuad_A88187.d
index 324e257..a10c279 100644
--- a/plugins/arm/v7/opdefs/smuad_A88187.d
+++ b/plugins/arm/v7/opdefs/smuad_A88187.d
@@ -2,7 +2,7 @@
 /* Chrysalide - Outil d'analyse de fichiers binaires
  * ##FILE## - traduction d'instructions ARMv7
  *
- * Copyright (C) 2015 Cyrille Bagard
+ * Copyright (C) 2017 Cyrille Bagard
  *
  *  This file is part of Chrysalide.
  *
@@ -23,26 +23,55 @@
 
 @title SMUAD
 
-@desc Signed Dual Multiply Add performs two signed 16 × 16-bit multiplications. It adds the products together, and writes the result to the destination register. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. This instruction sets the Q flag if the addition overflows. The multiplications cannot overflow.
+@id 186
+
+@desc {
+
+	Signed Dual Multiply Add performs two signed 16 × 16-bit multiplications. It adds the products together, and writes the result to the destination register. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. This instruction sets the Q flag if the addition overflows. The multiplications cannot overflow.
+
+}
 
 @encoding (T1) {
 
 	@word 1 1 1 1 1 0 1 1 0 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 M(1) Rm(4)
 
-	@syntax <reg_D> <reg_N> <reg_M>
+	@syntax {
+
+		@assert {
+
+			M == 0
+
+		}
+
+		@conv {
 
-	@conv {
+			reg_D = Register(Rd)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
 
-		reg_D = Register(Rd)
-		reg_N = Register(Rn)
-		reg_M = Register(Rm)
-		m_swap = (M == '1')
+		}
+
+		@asm smuad ?reg_D reg_N reg_M
 
 	}
 
-	@rules {
+	@syntax {
+
+		@assert {
+
+			M == 1
+
+		}
 
-		if (m_swap); chk_call ExtendKeyword("x")
+		@conv {
+
+			reg_D = Register(Rd)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
+
+		}
+
+		@asm smuadx ?reg_D reg_N reg_M
 
 	}
 
@@ -52,21 +81,55 @@
 
 	@word cond(4) 0 1 1 1 0 0 0 0 Rd(4) 1 1 1 1 Rm(4) 0 0 M(1) 1 Rn(4)
 
-	@syntax <reg_D> <reg_N> <reg_M>
+	@syntax {
+
+		@assert {
 
-	@conv {
+			M == 0
 
-		reg_D = Register(Rd)
-		reg_N = Register(Rn)
-		reg_M = Register(Rm)
-		m_swap = (M == '1')
+		}
+
+		@conv {
+
+			reg_D = Register(Rd)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
+
+		}
+
+		@asm smuad ?reg_D reg_N reg_M
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
 
 	}
 
-	@rules {
+	@syntax {
+
+		@assert {
+
+			M == 1
+
+		}
+
+		@conv {
+
+			reg_D = Register(Rd)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
+
+		}
+
+		@asm smuadx ?reg_D reg_N reg_M
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
 
-		if (m_swap); chk_call ExtendKeyword("x")
-		chk_call StoreCondition(cond)
+		}
 
 	}