diff options
Diffstat (limited to 'plugins/arm/v7/opdefs/str_A88203.d')
| -rw-r--r-- | plugins/arm/v7/opdefs/str_A88203.d | 128 |
1 files changed, 99 insertions, 29 deletions
diff --git a/plugins/arm/v7/opdefs/str_A88203.d b/plugins/arm/v7/opdefs/str_A88203.d index e3feaf7..f8b4958 100644 --- a/plugins/arm/v7/opdefs/str_A88203.d +++ b/plugins/arm/v7/opdefs/str_A88203.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title STR (immediate, Thumb) -@desc Store Register (immediate) calculates an address from a base register value and an immediate offset, and stores a word from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 202 + +@desc { + + Store Register (immediate) calculates an address from a base register value and an immediate offset, and stores a word from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (t1) { @half 0 1 1 0 0 imm5(5) Rn(3) Rt(3) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm5:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm5:'00', 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + } + + @asm str reg_T maccess } @@ -46,14 +56,18 @@ @half 1 0 0 1 0 Rt(3) imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(13) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_T = Register(Rt) - imm32 = ZeroExtend(imm8:'00', 32) - SP = Register(13) - mem_access = MakeMemoryAccess(SP, imm32, NULL, true, true, false) + } + + @asm str reg_T maccess } @@ -63,14 +77,18 @@ @word 1 1 1 1 1 0 0 0 1 1 0 0 Rn(4) Rt(4) imm12(12) - @syntax ".W" <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + } + + @asm str.w reg_T maccess } @@ -80,17 +98,69 @@ @word 1 1 1 1 1 0 0 0 0 1 0 0 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm str reg_T maccess + + } + + @syntax { + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm str reg_T maccess + + } + + @syntax { + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - index = (P == '1') - add = (U == '1') - wback = (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + @asm str reg_T maccess } |