diff options
Diffstat (limited to 'plugins/arm/v7/opdefs/str_A88205.d')
| -rw-r--r-- | plugins/arm/v7/opdefs/str_A88205.d | 134 |
1 files changed, 107 insertions, 27 deletions
diff --git a/plugins/arm/v7/opdefs/str_A88205.d b/plugins/arm/v7/opdefs/str_A88205.d index 55f154c..e4eb6fb 100644 --- a/plugins/arm/v7/opdefs/str_A88205.d +++ b/plugins/arm/v7/opdefs/str_A88205.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title STR (register) -@desc Store Register (register) calculates an address from a base register value and an offset register value, stores a word from a register to memory. The offset register value can optionally be shifted. For information about memory accesses see Memory accesses on page A8-294. +@id 204 + +@desc { + + Store Register (register) calculates an address from a base register value and an offset register value, stores a word from a register to memory. The offset register value can optionally be shifted. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (t1) { @half 0 1 0 1 0 0 0 Rm(3) Rn(3) Rt(3) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, true, false) + } + + @asm str reg_T maccess } @@ -46,15 +56,19 @@ @word 1 1 1 1 1 0 0 0 0 1 0 0 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - @syntax ".W" <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = FixedShift(SRType_LSL, imm2) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(0, imm2) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, true, false) + @asm str.w reg_T maccess } @@ -64,24 +78,90 @@ @word cond(4) 0 1 1 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm str reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPreIndexedExtended(reg_N, reg_M, shift) + + } + + @asm str reg_T maccess + + @rules { - @conv { + check g_arm_instruction_set_cond(cond) - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - shift = DecodeImmShift(type, imm5) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, index, add, wback) + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) + + } + + @asm str reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } |