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diff --git a/plugins/arm/v7/opdefs/strh_A88218.d b/plugins/arm/v7/opdefs/strh_A88218.d
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+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2015 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Foobar.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title STRH (register)
+
+@desc Store Register Halfword (register) calculates an address from a base register value and an offset register value, and stores a halfword from a register to memory. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294.
+
+@encoding (t1) {
+
+	@half 0 1 0 1 0 0 1 Rm(3) Rn(3) Rt(3)
+
+	@syntax <reg_T> <mem_access>
+
+	@conv {
+
+		reg_T = Register(Rt)
+		reg_N = Register(Rn)
+		reg_M = Register(Rm)
+		mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, true, false)
+
+	}
+
+}
+
+@encoding (T2) {
+
+	@word 1 1 1 1 1 0 0 0 0 0 1 0 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4)
+
+	@syntax ".W" <reg_T> <mem_access>
+
+	@conv {
+
+		reg_T = Register(Rt)
+		reg_N = Register(Rn)
+		reg_M = Register(Rm)
+		shift = DecodeImmShift(0, imm2)
+		mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, true, false)
+
+	}
+
+}
+
+@encoding (A1) {
+
+	@word cond(4) 0 0 0 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) 0 0 0 0 1 0 1 1 Rm(4)
+
+	@syntax <reg_T> <mem_access>
+
+	@conv {
+
+		reg_T = Register(Rt)
+		reg_N = Register(Rn)
+		reg_M = Register(Rm)
+		index = (P == '1')
+		add = (U == '1')
+		wback = (P == '0') || (W == '1')
+		mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, index, add, wback)
+
+	}
+
+	@rules {
+
+		chk_call StoreCondition(cond)
+
+	}
+
+}
+