diff options
Diffstat (limited to 'plugins/arm/v7/opdefs')
222 files changed, 16256 insertions, 0 deletions
diff --git a/plugins/arm/v7/opdefs/Makefile.am b/plugins/arm/v7/opdefs/Makefile.am new file mode 100644 index 0000000..3f69a3f --- /dev/null +++ b/plugins/arm/v7/opdefs/Makefile.am @@ -0,0 +1,302 @@ + +include ../../../../tools/d2c/d2c.mk + + +D2C_BIN = ../../../../tools/d2c/d2c +GEN_BIN = ../../../../tools/d2c/d2c_genmakefile.sh + +D2C_TYPE = raw + +D2C_OUTDIR = $(PWD)/.. + +D2C_ARCH = armv7 +D2C_HEADER = _ARCH_ARM_V7 + +D2C_ENCODINGS = \ + -e A=arm_ \ + -e t=thumb_16_ \ + -e T=thumb_32_ + +D2C_MACROS = \ + -M SetFlags=g_armv7_instruction_define_setflags \ + -M Condition=g_arm_instruction_set_cond \ + -M "ExpandImmC32=g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, " \ + -M SignExtend=sign_extend_armv7_imm \ + -M SetInsFlag=g_arch_instruction_set_flag \ + -M StoreCondition=g_arm_instruction_set_cond \ + -M ExtendKeyword=g_arm_instruction_extend_keyword + +D2C_OPERANDS = \ + -n BarrierLimitation \ + -n BitDiff \ + -n IncWidth \ + -n DecodeImmShift \ + -n MakeMemoryAccess \ + -n Register \ + -n RegisterShift \ + -n UInt \ + -n ZeroExtend + +FIXED_C_INCLUDES = \ + \n\#include <arch/link.h> \ + \n\#include <common/bconst.h> \ + \n \ + \n\#include \"../helpers.h\" \ + \n\#include \"../instruction.h\" \ + \n\#include \"../fetch.h\" \ + \n\#include \"../link.h\" \ + \n\#include \"../post.h\" \ + \n\#include \"../../instruction.h\" \ + \n\#include \"../../link.h\" \ + \n\n + +FIXED_H_INCLUDES = \ + \n\#include <stdint.h> \ + \n \ + \n\#include <arch/instruction.h> \ + \n\n + + +# for i in $(seq 1 426); do test -f *A88$i.d && (ls *A88$i.d | sed 's/^/\t/' | sed 's/$/\t\t\t\t\t\t\\/') ; done +ARMV7_DEFS = \ + adc_A881.d \ + adc_A882.d \ + adc_A883.d \ + add_A884.d \ + add_A885.d \ + add_A886.d \ + add_A887.d \ + add_A888.d \ + add_A889.d \ + add_A8810.d \ + add_A8811.d \ + adr_A8812.d \ + and_A8813.d \ + and_A8814.d \ + and_A8815.d \ + asr_A8816.d \ + asr_A8817.d \ + b_A8818.d \ + bfc_A8819.d \ + bfi_A8820.d \ + bic_A8821.d \ + bic_A8822.d \ + bic_A8823.d \ + bkpt_A8824.d \ + bl_A8825.d \ + blx_A8826.d \ + bx_A8827.d \ + bxj_A8828.d \ + cb_A8829.d \ + cdp_A8830.d \ + clrex_A8832.d \ + clz_A8833.d \ + cmn_A8834.d \ + cmn_A8835.d \ + cmn_A8836.d \ + cmp_A8837.d \ + cmp_A8838.d \ + cmp_A8839.d \ + dbg_A8842.d \ + dmb_A8843.d \ + dsb_A8844.d \ + eor_A8846.d \ + eor_A8847.d \ + eor_A8848.d \ + ldr_A8862.d \ + ldr_A8863.d \ + ldr_A8864.d \ + ldr_A8865.d \ + ldr_A8866.d \ + ldrb_A8867.d \ + ldrb_A8868.d \ + ldrb_A8869.d \ + ldrb_A8870.d \ + ldrbt_A8871.d \ + ldrd_A8872.d \ + ldrd_A8873.d \ + ldrd_A8874.d \ + ldrex_A8875.d \ + ldrexb_A8876.d \ + ldrexd_A8877.d \ + ldrexh_A8878.d \ + ldrh_A8879.d \ + ldrh_A8880.d \ + ldrh_A8881.d \ + ldrh_A8882.d \ + ldrht_A8883.d \ + ldrsb_A8884.d \ + ldrsb_A8885.d \ + ldrsb_A8886.d \ + ldrsbt_A8887.d \ + ldrsh_A8888.d \ + ldrsh_A8889.d \ + ldrsh_A8890.d \ + ldrsht_A8891.d \ + ldrt_A8892.d \ + lsl_A8894.d \ + lsl_A8895.d \ + lsr_A8896.d \ + lsr_A8897.d \ + mcr_A8898.d \ + mcrr_A8899.d \ + mla_A88100.d \ + mls_A88101.d \ + mov_A88102.d \ + mov_A88103.d \ + mov_A88104.d \ + movt_A88106.d \ + mrc_A88107.d \ + mrrc_A88108.d \ + mul_A88114.d \ + mvn_A88115.d \ + mvn_A88116.d \ + mvn_A88117.d \ + nop_A88119.d \ + orn_A88120.d \ + orn_A88121.d \ + orr_A88122.d \ + orr_A88123.d \ + orr_A88124.d \ + pop_A88131.d \ + pop_A88132.d \ + push_A88133.d \ + qadd_A88134.d \ + qadd16_A88135.d \ + qadd8_A88136.d \ + qasx_A88137.d \ + qdadd_A88138.d \ + qdsub_A88139.d \ + qsax_A88140.d \ + qsub_A88141.d \ + qsub16_A88142.d \ + qsub8_A88143.d \ + rbit_A88144.d \ + rev_A88145.d \ + rev16_A88146.d \ + revsh_A88147.d \ + ror_A88149.d \ + ror_A88150.d \ + rrx_A88151.d \ + rsb_A88152.d \ + rsb_A88153.d \ + rsb_A88154.d \ + rsc_A88155.d \ + rsc_A88156.d \ + rsc_A88157.d \ + sadd16_A88158.d \ + sadd8_A88159.d \ + sasx_A88160.d \ + sbc_A88161.d \ + sbc_A88162.d \ + sbc_A88163.d \ + sbfx_A88164.d \ + sdiv_A88165.d \ + sel_A88166.d \ + setend_A88167.d \ + sev_A88168.d \ + shadd16_A88169.d \ + shadd8_A88170.d \ + shasx_A88171.d \ + shsax_A88172.d \ + shsub16_A88173.d \ + shsub8_A88174.d \ + smlad_A88177.d \ + smlal_A88178.d \ + smlald_A88180.d \ + smlsd_A88182.d \ + smlsld_A88183.d \ + smmla_A88184.d \ + smmls_A88185.d \ + smmul_A88186.d \ + smuad_A88187.d \ + smull_A88189.d \ + str_A88203.d \ + str_A88204.d \ + str_A88205.d \ + strb_A88206.d \ + strb_A88207.d \ + strb_A88208.d \ + strbt_A88209.d \ + strd_A88210.d \ + strd_A88211.d \ + strex_A88212.d \ + strexb_A88213.d \ + strexd_A88214.d \ + strexh_A88215.d \ + strh_A88216.d \ + strh_A88217.d \ + strh_A88218.d \ + strht_A88219.d \ + strt_A88220.d \ + sub_A88221.d \ + sub_A88222.d \ + sub_A88223.d \ + sub_A88225.d \ + svc_A88228.d \ + swp_A88229.d \ + teq_A88237.d \ + teq_A88238.d \ + teq_A88239.d \ + tst_A88240.d \ + tst_A88241.d \ + tst_A88242.d \ + uadd16_A88243.d \ + uadd8_A88244.d \ + uasx_A88245.d \ + ubfx_A88246.d \ + udf_A88247.d \ + udiv_A88248.d \ + uhadd16_A88249.d \ + uhadd8_A88250.d \ + uhasx_A88251.d \ + uhsax_A88252.d \ + uhsub16_A88253.d \ + uhsub8_A88254.d \ + umaal_A88255.d \ + umlal_A88256.d \ + umull_A88257.d \ + uqadd16_A88258.d \ + uqadd8_A88259.d \ + uqasx_A88260.d \ + uqsax_A88261.d \ + uqsub16_A88262.d \ + uqsub8_A88263.d \ + usad8_A88264.d \ + usada8_A88265.d \ + usat_A88266.d \ + usat16_A88267.d \ + usax_A88268.d \ + usub16_A88269.d \ + usub8_A88270.d \ + uxtab_A88271.d \ + uxtab16_A88272.d \ + uxtah_A88273.d \ + uxtb_A88274.d \ + uxtb16_A88275.d \ + uxth_A88276.d \ + wfi_A88425.d \ + yield_A88426.d + +# subs_B9320.d + +# make dist procède répertoire par répertoire. Or le répertoire opcodes utilise +# le contenu du répertoire opdefs. Il faut donc générer les fichiers nécessaires +# au répertoire opcodes. Et comme on ne peut pas compléter la règle dist, on +# ajoute à la distribution les cibles marquant la génération. (1/2) + +EXTRA_DIST = $(ARMV7_DEFS) $(ARMV7_DEFS:.d=.g) + +# Après coup, on supprime les fichiers inutiles de la distribution/ (2/2) + +dist-hook: + cd $(distdir) && rm $(ARMV7_DEFS:.d=.g) + +all: $(ARMV7_DEFS:.d=.g) fmk.done d2c_final_rules + +fmk.done: $(ARMV7_DEFS) + $(GEN_BIN) ../opcodes/ ../opdefs/.gen ../../../../tools/d2c/globalgen.mk arm thumb_32 thumb_16 + touch $@ + +clean: + rm -rf $(ARMV7_DEFS:.d=.g) .gen fmk.done diff --git a/plugins/arm/v7/opdefs/adc_A881.d b/plugins/arm/v7/opdefs/adc_A881.d new file mode 100644 index 0000000..6bc66e2 --- /dev/null +++ b/plugins/arm/v7/opdefs/adc_A881.d @@ -0,0 +1,74 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title ADC (immediate) + +@desc Add with Carry (immediate) adds an immediate value and the Carry flag value to a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +@encoding (T1) { + + @word 1 1 1 1 0 i(1) 0 1 0 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) + + @syntax <reg_D> <reg_N> <imm32> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + setflags = (S == '1') + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 0 1 0 1 S(1) Rn(4) Rd(4) imm12(12) + + @syntax <reg_D> <reg_N> <imm32> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + setflags = (S == '1') + imm32 = ARMExpandImm(imm12) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/adc_A882.d b/plugins/arm/v7/opdefs/adc_A882.d new file mode 100644 index 0000000..27ce6ad --- /dev/null +++ b/plugins/arm/v7/opdefs/adc_A882.d @@ -0,0 +1,92 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title ADC (register) + +@desc Add with Carry (register) adds a register value, the Carry flag value, and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +@encoding (t1) { + + @half 0 1 0 0 0 0 0 1 0 1 Rm(3) Rdn(3) + + @syntax "adcs" <reg_DN> <reg_M> + + @conv { + + reg_DN = Register(Rdn) + reg_M = Register(Rm) + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 1 1 0 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <?shift> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm3:imm2) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 1 0 1 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <?shift> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm5) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/adc_A883.d b/plugins/arm/v7/opdefs/adc_A883.d new file mode 100644 index 0000000..a9c56d8 --- /dev/null +++ b/plugins/arm/v7/opdefs/adc_A883.d @@ -0,0 +1,52 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title ADC (register-shifted register) + +@desc Add with Carry (register-shifted register) adds a register value, the Carry flag value, and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. + +@encoding (A1) { + + @word cond(4) 0 0 0 0 1 0 1 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <reg_shift> + + @conv { + + reg_shift = RegisterShift(type, Rs) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/add_A8810.d b/plugins/arm/v7/opdefs/add_A8810.d new file mode 100644 index 0000000..2047276 --- /dev/null +++ b/plugins/arm/v7/opdefs/add_A8810.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title ADD (SP plus register, Thumb) + +@desc This instruction adds an optionally-shifted register value to the SP value, and writes the result to the destination register. + +@encoding (t1) { + + @half 0 1 0 0 0 1 0 0 DM(1) 1 1 0 1 Rdm(3) + + @syntax <reg_DM_1> <SP> <reg_DM_2> + + @conv { + + reg_DM_1 = Register(DM:Rdm) + reg_DM_2 = Register(DM:Rdm) + SP = Register(13) + + } + +} + +@encoding (t2) { + + @half 0 1 0 0 0 1 0 0 1 Rm(4) 1 0 1 + + @syntax <SP> <reg_M> + + @conv { + + reg_M = Register(Rm) + SP = Register(13) + + } + +} + +@encoding (T3) { + + @word 1 1 1 0 1 0 1 1 0 0 0 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) + + @syntax <reg_D> <SP> <reg_M> <?shift> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm3:imm2) + SP = Register(13) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") + + } + +} + diff --git a/plugins/arm/v7/opdefs/add_A8811.d b/plugins/arm/v7/opdefs/add_A8811.d new file mode 100644 index 0000000..5b6c0d1 --- /dev/null +++ b/plugins/arm/v7/opdefs/add_A8811.d @@ -0,0 +1,52 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title ADD (SP plus register, ARM) + +@desc This instruction adds an optionally-shifted register value to the SP value, and writes the result to the destination register. + +@encoding (A1) { + + @word cond(4) 0 0 0 0 1 0 0 S(1) 1 1 0 1 Rd(4) imm5(5) type(2) 0 Rm(4) + + @syntax <reg_D> <SP> <reg_M> <?shift> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm5) + SP = Register(13) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/add_A884.d b/plugins/arm/v7/opdefs/add_A884.d new file mode 100644 index 0000000..8b624a7 --- /dev/null +++ b/plugins/arm/v7/opdefs/add_A884.d @@ -0,0 +1,98 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title ADD (immediate, Thumb) + +@desc This instruction adds an immediate value to a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +@encoding (t1) { + + @half 0 0 0 1 1 1 0 imm3(3) Rn(3) Rd(3) + + @syntax "adds" <reg_D> <reg_N> <imm32> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm3, 32) + + } + +} + +@encoding (t2) { + + @half 0 0 1 1 0 Rdn(3) imm8(8) + + @syntax "adds" <reg_DN> <imm32> + + @conv { + + reg_DN = Register(Rdn) + imm32 = ZeroExtend(imm8, 32) + + } + +} + +@encoding (T3) { + + @word 1 1 1 1 0 i(1) 0 1 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) + + @syntax <reg_D> <reg_N> <imm32> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + setflags = (S == '1') + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") + + } + +} + +@encoding (T4) { + + @word 1 1 1 1 0 i(1) 1 0 0 0 0 0 Rn(4) 0 imm3(3) Rd(4) imm8(8) + + @syntax "addw" <reg_D> <reg_N> <imm32> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ZeroExtend(i:imm3:imm8, 32) + + } + +} + diff --git a/plugins/arm/v7/opdefs/add_A885.d b/plugins/arm/v7/opdefs/add_A885.d new file mode 100644 index 0000000..0f4a919 --- /dev/null +++ b/plugins/arm/v7/opdefs/add_A885.d @@ -0,0 +1,51 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title ADD (immediate, ARM) + +@desc This instruction adds an immediate value to a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +@encoding (A1) { + + @word cond(4) 0 0 1 0 1 0 0 S(1) Rn(4) Rd(4) imm12(12) + + @syntax <reg_D> <reg_N> <imm32> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + setflags = (S == '1') + imm32 = ARMExpandImm(imm12) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/add_A886.d b/plugins/arm/v7/opdefs/add_A886.d new file mode 100644 index 0000000..e4f9e00 --- /dev/null +++ b/plugins/arm/v7/opdefs/add_A886.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title ADD (register, Thumb) + +@desc This instruction adds a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +@encoding (t1) { + + @half 0 0 0 1 1 0 0 Rm(3) Rn(3) Rd(3) + + @syntax "adds" <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (t2) { + + @half 0 1 0 0 0 1 0 0 DN(1) Rm(4) Rdn(3) + + @syntax <reg_DN> <reg_M> + + @conv { + + reg_DN = Register(DN:Rdn) + reg_M = Register(Rm) + + } + +} + +@encoding (T3) { + + @word 1 1 1 0 1 0 1 1 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <?shift> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm3:imm2) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") + + } + +} + diff --git a/plugins/arm/v7/opdefs/add_A887.d b/plugins/arm/v7/opdefs/add_A887.d new file mode 100644 index 0000000..18400a6 --- /dev/null +++ b/plugins/arm/v7/opdefs/add_A887.d @@ -0,0 +1,52 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title ADD (register, ARM) + +@desc This instruction adds a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +@encoding (A1) { + + @word cond(4) 0 0 0 0 1 0 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <?shift> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm5) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/add_A888.d b/plugins/arm/v7/opdefs/add_A888.d new file mode 100644 index 0000000..5549145 --- /dev/null +++ b/plugins/arm/v7/opdefs/add_A888.d @@ -0,0 +1,52 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title ADD (register-shifted register) + +@desc Add (register-shifted register) adds a register value and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. + +@encoding (A1) { + + @word cond(4) 0 0 0 0 1 0 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <reg_shift> + + @conv { + + reg_shift = RegisterShift(type, Rs) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/add_A889.d b/plugins/arm/v7/opdefs/add_A889.d new file mode 100644 index 0000000..5fab17c --- /dev/null +++ b/plugins/arm/v7/opdefs/add_A889.d @@ -0,0 +1,123 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title ADD (SP plus immediate) + +@desc This instruction adds an immediate value to the SP value, and writes the result to the destination register. + +@encoding (t1) { + + @half 1 0 1 0 1 Rd(3) imm8(8) + + @syntax <reg_D> <SP> <imm32> + + @conv { + + reg_D = Register(Rd) + imm32 = ZeroExtend(imm8:'00', 32) + SP = Register(13) + + } + +} + +@encoding (t2) { + + @half 1 0 1 1 0 0 0 0 0 imm7(7) + + @syntax <SP_0> <SP_1> <imm32> + + @conv { + + imm32 = ZeroExtend(imm7:'00', 32) + SP_0 = Register(13) + SP_1 = Register(13) + + } + +} + +@encoding (T3) { + + @word 1 1 1 1 0 i(1) 0 1 0 0 0 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm8(8) + + @syntax <reg_D> <SP> <imm32> + + @conv { + + reg_D = Register(Rd) + setflags = (S == '1') + imm32 = ThumbExpandImm(i:imm3:imm8) + SP = Register(13) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") + + } + +} + +@encoding (T4) { + + @word 1 1 1 1 0 i(1) 1 0 0 0 0 0 1 1 0 1 0 imm3(3) Rd(4) imm8(8) + + @syntax "addw" <reg_D> <SP> <imm32> + + @conv { + + reg_D = Register(Rd) + imm32 = ZeroExtend(i:imm3:imm8, 32) + SP = Register(13) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 0 1 0 0 S(1) 1 1 0 1 Rd(4) imm12(12) + + @syntax <reg_D> <SP> <imm32> + + @conv { + + reg_D = Register(Rd) + setflags = (S == '1') + imm32 = ARMExpandImm(imm12) + SP = Register(13) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/adr_A8812.d b/plugins/arm/v7/opdefs/adr_A8812.d new file mode 100644 index 0000000..16615cb --- /dev/null +++ b/plugins/arm/v7/opdefs/adr_A8812.d @@ -0,0 +1,114 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title ADR + +@desc This instruction adds an immediate value to the PC value to form a PC-relative address, and writes the result to the destination register. + +@encoding (t1) { + + @half 1 0 1 0 0 Rd(3) imm8(8) + + @syntax <reg_D> <imm32> + + @conv { + + reg_D = Register(Rd) + imm32 = ZeroExtend(imm8:'00', 32) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 0 i(1) 1 0 1 0 1 0 1 1 1 1 0 imm3(3) Rd(4) imm8(8) + + @syntax ".W" <reg_D> <imm32> + + @conv { + + reg_D = Register(Rd) + imm32 = ZeroExtend(i:imm3:imm8, 32) + + } + +} + +@encoding (T3) { + + @word 1 1 1 1 0 i(1) 1 0 0 0 0 0 1 1 1 1 0 imm3(3) Rd(4) imm8(8) + + @syntax ".W" <reg_D> <imm32> + + @conv { + + reg_D = Register(Rd) + imm32 = ZeroExtend(i:imm3:imm8, 32) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 0 1 0 0 0 1 1 1 1 Rd(4) imm12(12) + + @syntax <reg_D> <imm32> + + @conv { + + reg_D = Register(Rd) + imm32 = ARMExpandImm(imm12) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + +@encoding (A2) { + + @word cond(4) 0 0 1 0 0 1 0 0 1 1 1 1 Rd(4) imm12(12) + + @syntax <reg_D> <imm32> + + @conv { + + reg_D = Register(Rd) + imm32 = ARMExpandImm(imm12) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/and_A8813.d b/plugins/arm/v7/opdefs/and_A8813.d new file mode 100644 index 0000000..3e1d0ed --- /dev/null +++ b/plugins/arm/v7/opdefs/and_A8813.d @@ -0,0 +1,74 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title AND (immediate) + +@desc This instruction performs a bitwise AND of a register value and an immediate value, and writes the result to the destination register. + +@encoding (T1) { + + @word 1 1 1 1 0 i(1) 0 0 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) + + @syntax <reg_D> <reg_N> <imm32> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + setflags = (S == '1') + imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 0 0 0 0 S(1) Rn(4) Rd(4) imm12(12) + + @syntax <reg_D> <reg_N> <imm32> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + setflags = (S == '1') + imm32 = ARMExpandImm_C(imm12, 0) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/and_A8814.d b/plugins/arm/v7/opdefs/and_A8814.d new file mode 100644 index 0000000..77f7e55 --- /dev/null +++ b/plugins/arm/v7/opdefs/and_A8814.d @@ -0,0 +1,92 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title AND (register) + +@desc This instruction performs a bitwise AND of a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +@encoding (t1) { + + @half 0 1 0 0 0 0 0 0 0 0 Rm(3) Rdn(3) + + @syntax "ands" <reg_DN> <reg_M> + + @conv { + + reg_DN = Register(Rdn) + reg_M = Register(Rm) + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 1 0 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <?shift> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm3:imm2) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 0 0 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <?shift> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm5) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/and_A8815.d b/plugins/arm/v7/opdefs/and_A8815.d new file mode 100644 index 0000000..5ace3fa --- /dev/null +++ b/plugins/arm/v7/opdefs/and_A8815.d @@ -0,0 +1,52 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title AND (register-shifted register) + +@desc This instruction performs a bitwise AND of a register value and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. + +@encoding (A1) { + + @word cond(4) 0 0 0 0 0 0 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <reg_shift> + + @conv { + + reg_shift = RegisterShift(type, Rs) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/asr_A8816.d b/plugins/arm/v7/opdefs/asr_A8816.d new file mode 100644 index 0000000..006a26c --- /dev/null +++ b/plugins/arm/v7/opdefs/asr_A8816.d @@ -0,0 +1,91 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title ASR (immediate) + +@desc Arithmetic Shift Right (immediate) shifts a register value right by an immediate number of bits, shifting in copies of its sign bit, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +@encoding (t1) { + + @half 0 0 0 1 0 imm5(5) Rm(3) Rd(3) + + @syntax "asrs" <reg_D> <reg_M> <shift_imm> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_imm = DecodeImmShift('10', imm5) + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 1 0 Rm(4) + + @syntax <reg_D> <reg_M> <shift_imm> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + setflags = (S == '1') + shift_imm = DecodeImmShift('10', imm3:imm2) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 1 0 0 Rm(4) + + @syntax <reg_D> <reg_M> <shift_imm> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + setflags = (S == '1') + shift_imm = DecodeImmShift('10', imm5) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/asr_A8817.d b/plugins/arm/v7/opdefs/asr_A8817.d new file mode 100644 index 0000000..1e1e9c1 --- /dev/null +++ b/plugins/arm/v7/opdefs/asr_A8817.d @@ -0,0 +1,90 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title ASR (register) + +@desc Arithmetic Shift Right (register) shifts a register value right by a variable number of bits, shifting in copies of its sign bit, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. + +@encoding (t1) { + + @half 0 1 0 0 0 0 0 1 0 0 Rm(3) Rdn(3) + + @syntax "asrs" <reg_DN> <reg_M> + + @conv { + + reg_DN = Register(Rdn) + reg_M = Register(Rm) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 1 0 0 1 0 S(1) Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) Rm(4) 0 1 0 1 Rn(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/b_A8818.d b/plugins/arm/v7/opdefs/b_A8818.d new file mode 100644 index 0000000..9e27753 --- /dev/null +++ b/plugins/arm/v7/opdefs/b_A8818.d @@ -0,0 +1,157 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title B + +@desc Branch causes a branch to a target address. + +@encoding (t1) { + + @half 1 1 0 1 cond(4) imm8(8) + + @syntax <imm32> + + @conv { + + imm32 = SignExtend(imm8:'0', imm8 & 0x80, 32) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + + @hooks { + + fetch = help_fetching_with_instruction_b_from_thumb + link = handle_arm_conditional_branch_as_link + post = post_process_branch_instructions + + } + +} + +@encoding (t2) { + + @half 1 1 1 0 0 imm11(11) + + @syntax <imm32> + + @conv { + + imm32 = SignExtend(imm11:'0', imm11 & 0x400, 32) + + } + + @hooks { + + fetch = help_fetching_with_instruction_b_from_thumb + link = handle_arm_conditional_branch_as_link + post = post_process_branch_instructions + + } + +} + +@encoding (T3) { + + @word 1 1 1 1 0 S(1) cond(4) imm6(6) 1 0 J1(1) 0 J2(1) imm11(11) + + @syntax ".W" <imm32> + + @conv { + + imm32 = SignExtend(S:J2:J1:imm6:imm11:'0', S & 0x1, 32) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + + @hooks { + + fetch = help_fetching_with_instruction_b_from_thumb + link = handle_arm_conditional_branch_as_link + post = post_process_branch_instructions + + } + +} + +@encoding (T4) { + + @word 1 1 1 1 0 S(1) imm10(10) 1 0 J1(1) 1 J2(1) imm11(11) + + @syntax ".W" <imm32> + + @conv { + + I1 = NOT(J1 EOR S) + I2 = NOT(J2 EOR S) + imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', S & 0x1, 32) + + } + + @hooks { + + fetch = help_fetching_with_instruction_b_from_thumb + link = handle_arm_conditional_branch_as_link + post = post_process_branch_instructions + + } + +} + +@encoding (A1) { + + @word cond(4) 1 0 1 0 imm24(24) + + @syntax <imm32> + + @conv { + + imm32 = SignExtend(imm24:'00', imm24 & 0x800000, 32) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + + @hooks { + + fetch = help_fetching_with_instruction_b_from_arm + link = handle_arm_conditional_branch_as_link + post = post_process_branch_instructions + + } + +} + diff --git a/plugins/arm/v7/opdefs/bfc_A8819.d b/plugins/arm/v7/opdefs/bfc_A8819.d new file mode 100644 index 0000000..0ee99c8 --- /dev/null +++ b/plugins/arm/v7/opdefs/bfc_A8819.d @@ -0,0 +1,67 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title BFC + +@desc Bit Field Clear clears any number of adjacent bits at any position in a register, without affecting the other bits in the register. + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 0 1 1 0 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 0 msb(5) + + @syntax <reg_D> <lsbit> <width> + + @conv { + + reg_D = Register(Rd) + msbit = UInt(msb) + lsbit = UInt(imm3:imm2) + width = BitDiff(msbit, lsbit) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 1 1 0 msb(5) Rd(4) lsb(5) 0 0 1 1 1 1 1 + + @syntax <reg_D> <lsbit> <width> + + @conv { + + reg_D = Register(Rd) + msbit = UInt(msb) + lsbit = UInt(lsb) + width = BitDiff(msbit, lsbit) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/bfi_A8820.d b/plugins/arm/v7/opdefs/bfi_A8820.d new file mode 100644 index 0000000..1d2bb2f --- /dev/null +++ b/plugins/arm/v7/opdefs/bfi_A8820.d @@ -0,0 +1,69 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title BFI + +@desc Bit Field Insert copies any number of low order bits from a register into the same number of adjacent bits at any position in the destination register. + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 0 1 1 0 Rn(4) 0 imm3(3) Rd(4) imm2(2) 0 msb(5) + + @syntax <reg_D> <reg_N> <lsbit> <width> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + msbit = UInt(msb) + lsbit = UInt(imm3:imm2) + width = BitDiff(msbit, lsbit) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 1 1 0 msb(5) Rd(4) lsb(5) 0 0 1 Rn(4) + + @syntax <reg_D> <reg_N> <lsbit> <width> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + msbit = UInt(msb) + lsbit = UInt(lsb) + width = BitDiff(msbit, lsbit) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/bic_A8821.d b/plugins/arm/v7/opdefs/bic_A8821.d new file mode 100644 index 0000000..9171b69 --- /dev/null +++ b/plugins/arm/v7/opdefs/bic_A8821.d @@ -0,0 +1,74 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title BIC (immediate) + +@desc Bitwise Bit Clear (immediate) performs a bitwise AND of a register value and the complement of an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +@encoding (T1) { + + @word 1 1 1 1 0 i(1) 0 0 0 0 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) + + @syntax <reg_D> <reg_N> <imm32> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + setflags = (S == '1') + imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 1 1 0 S(1) Rn(4) Rd(4) imm12(12) + + @syntax <reg_D> <reg_N> <imm32> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + setflags = (S == '1') + imm32 = ARMExpandImm_C(imm12, 0) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/bic_A8822.d b/plugins/arm/v7/opdefs/bic_A8822.d new file mode 100644 index 0000000..8503460 --- /dev/null +++ b/plugins/arm/v7/opdefs/bic_A8822.d @@ -0,0 +1,92 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title BIC (register) + +@desc Bitwise Bit Clear (register) performs a bitwise AND of a register value and the complement of an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +@encoding (t1) { + + @half 0 1 0 0 0 0 1 1 1 0 Rm(3) Rdn(3) + + @syntax "bics" <reg_DN> <reg_M> + + @conv { + + reg_DN = Register(Rdn) + reg_M = Register(Rm) + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 1 0 0 0 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <?shift> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm3:imm2) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 1 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <?shift> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm5) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/bic_A8823.d b/plugins/arm/v7/opdefs/bic_A8823.d new file mode 100644 index 0000000..e6903db --- /dev/null +++ b/plugins/arm/v7/opdefs/bic_A8823.d @@ -0,0 +1,52 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title BIC (register-shifted register) + +@desc Bitwise Bit Clear (register-shifted register) performs a bitwise AND of a register value and the complement of a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 1 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <reg_shift> + + @conv { + + reg_shift = RegisterShift(type, Rs) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/bkpt_A8824.d b/plugins/arm/v7/opdefs/bkpt_A8824.d new file mode 100644 index 0000000..f0aa13a --- /dev/null +++ b/plugins/arm/v7/opdefs/bkpt_A8824.d @@ -0,0 +1,55 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title BKPT + +@desc Breakpoint causes a software breakpoint to occur. Breakpoint is always unconditional, even when inside an IT block. + +@encoding (t1) { + + @half 1 0 1 1 1 1 1 0 imm8(8) + + @syntax <imm32> + + @conv { + + imm32 = ZeroExtend(imm8, 32) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 0 1 0 imm12(12) 0 1 1 1 imm4(4) + + @syntax <imm32> + + @conv { + + imm32 = ZeroExtend(imm12:imm4, 32) + + } + +} + diff --git a/plugins/arm/v7/opdefs/bl_A8825.d b/plugins/arm/v7/opdefs/bl_A8825.d new file mode 100644 index 0000000..da0def4 --- /dev/null +++ b/plugins/arm/v7/opdefs/bl_A8825.d @@ -0,0 +1,125 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title BL, BLX (immediate) + +@desc Branch with Link calls a subroutine at a PC-relative address. Branch with Link and Exchange Instruction Sets (immediate) calls a subroutine at a PC-relative address, and changes instruction set from ARM to Thumb, or from Thumb to ARM. + +@encoding (T1) { + + @word 1 1 1 1 0 S(1) imm10(10) 1 1 J1(1) 1 J2(1) imm11(11) + + @syntax <imm32> + + @conv { + + I1 = NOT(J1 EOR S) + I2 = NOT(J2 EOR S) + imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', S & 0x1, 32) + + } + + @hooks { + + fetch = help_fetching_with_instruction_bl_from_thumb + link = handle_call_as_link + post = post_process_branch_and_link_instructions + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 0 S(1) imm10H(10) 1 1 J1(1) 0 J2(1) imm10L(10) H(1) + + @syntax "blx" <imm32> + + @conv { + + I1 = NOT(J1 EOR S) + I2 = NOT(J2 EOR S) + imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', S & 0x1, 32) + + } + + @hooks { + + fetch = help_fetching_with_instruction_blx_from_thumb + link = handle_call_as_link + post = post_process_branch_and_link_instructions + + } + +} + +@encoding (A1) { + + @word cond(4) 1 0 1 1 imm24(24) + + @syntax <imm32> + + @conv { + + imm32 = SignExtend(imm24:'00', imm24 & 0x800000, 32) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + + @hooks { + + fetch = help_fetching_with_instruction_bl_from_arm + link = handle_call_as_link + post = post_process_branch_and_link_instructions + + } + +} + +@encoding (A2) { + + @word 1 1 1 1 1 0 1 H(1) imm24(24) + + @syntax "blx" <imm32> + + @conv { + + imm32 = SignExtend(imm24:H:'0', imm24 & 0x800000, 32) + + } + + @hooks { + + fetch = help_fetching_with_instruction_blx_from_arm + link = handle_call_as_link + post = post_process_branch_and_link_instructions + + } + +} + diff --git a/plugins/arm/v7/opdefs/blx_A8826.d b/plugins/arm/v7/opdefs/blx_A8826.d new file mode 100644 index 0000000..29719fa --- /dev/null +++ b/plugins/arm/v7/opdefs/blx_A8826.d @@ -0,0 +1,61 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title BLX (register) + +@desc Branch with Link and Exchange (register) calls a subroutine at an address and instruction set specified by a register. + +@encoding (t1) { + + @half 0 1 0 0 0 1 1 1 1 Rm(4) 0 0 0 + + @syntax <reg_M> + + @conv { + + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 Rm(4) + + @syntax <reg_M> + + @conv { + + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/bx_A8827.d b/plugins/arm/v7/opdefs/bx_A8827.d new file mode 100644 index 0000000..f3681e7 --- /dev/null +++ b/plugins/arm/v7/opdefs/bx_A8827.d @@ -0,0 +1,75 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title BX + +@desc Branch and Exchange causes a branch to an address and instruction set specified by a register. + +@encoding (t1) { + + @half 0 1 0 0 0 1 1 1 0 Rm(4) 0 0 0 + + @syntax <reg_M> + + @conv { + + reg_M = Register(Rm) + + } + + @hooks { + + fetch = help_fetching_with_instruction_bx_from_thumb + link = handle_armv7_conditional_branch_from_register + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 Rm(4) + + @syntax <reg_M> + + @conv { + + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + + @hooks { + + fetch = help_fetching_with_instruction_bx_from_arm + link = handle_armv7_conditional_branch_from_register + + } + +} + diff --git a/plugins/arm/v7/opdefs/bxj_A8828.d b/plugins/arm/v7/opdefs/bxj_A8828.d new file mode 100644 index 0000000..efa2de2 --- /dev/null +++ b/plugins/arm/v7/opdefs/bxj_A8828.d @@ -0,0 +1,61 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title BXJ + +@desc Branch and Exchange Jazelle attempts to change to Jazelle state. If the attempt fails, it branches to an address and instruction set specified by a register as though it were a BX instruction. In an implementation that includes the Virtualization Extensions, if HSTR.TJDBX is set to 1, execution of a BXJ instruction in a Non-secure mode other than Hyp mode generates a Hyp Trap exception. For more information see Trapping accesses to Jazelle functionality on page B1-1255. + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 1 1 0 0 Rm(4) 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 + + @syntax <reg_M> + + @conv { + + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 Rm(4) + + @syntax <reg_M> + + @conv { + + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/cb_A8829.d b/plugins/arm/v7/opdefs/cb_A8829.d new file mode 100644 index 0000000..134e0f4 --- /dev/null +++ b/plugins/arm/v7/opdefs/cb_A8829.d @@ -0,0 +1,58 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title CBNZ, CBZ + +@desc Compare and Branch on Nonzero and Compare and Branch on Zero compare the value in a register with zero, and conditionally branch forward a constant value. They do not affect the condition flags. + +@encoding (t1) { + + @half 1 0 1 1 op(1) 0 i(1) 1 imm5(5) Rn(3) + + @syntax <reg_N> <imm32> + + @conv { + + reg_N = Register(Rn) + imm32 = ZeroExtend(i:imm5:'0', 32) + nonzero = (op == '1') + + } + + @rules { + + if (nonzero); chk_call ExtendKeyword("n") + chk_call ExtendKeyword("z") + + } + + @hooks { + + fetch = help_fetching_with_instruction_cb_n_z + link = handle_comp_and_branch_if_true_as_link + post = post_process_comp_and_branch_instructions + + } + +} + diff --git a/plugins/arm/v7/opdefs/cdp_A8830.d b/plugins/arm/v7/opdefs/cdp_A8830.d new file mode 100644 index 0000000..109b89b --- /dev/null +++ b/plugins/arm/v7/opdefs/cdp_A8830.d @@ -0,0 +1,109 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title CDP, CDP2 + +@desc Coprocessor Data Processing tells a coprocessor to perform an operation that is independent of ARM core registers and memory. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1, opc2, CRd, CRn, and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid CDP and CDP2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. + +@encoding (T1) { + + @word 1 1 1 0 1 1 1 0 opc1(4) CRn(4) CRd(4) coproc(4) opc2(3) 0 CRm(4) + + @syntax <cp> <undef_opc1> <creg_D> <creg_N> <creg_M> <undef_opc2> + + @conv { + + cp = CoProcessor(coproc) + undef_opc1 = RawValue(opc1) + creg_D = CRegister(CRd) + creg_N = CRegister(CRn) + creg_M = CRegister(CRm) + undef_opc2 = RawValue(opc2) + + } + +} + +@encoding (A1) { + + @word cond(4) 1 1 1 0 opc1(4) CRn(4) CRd(4) coproc(4) opc2(3) 0 CRm(4) + + @syntax <cp> <undef_opc1> <creg_D> <creg_N> <creg_M> <undef_opc2> + + @conv { + + cp = CoProcessor(coproc) + undef_opc1 = RawValue(opc1) + creg_D = CRegister(CRd) + creg_N = CRegister(CRn) + creg_M = CRegister(CRm) + undef_opc2 = RawValue(opc2) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 1 1 0 opc1(4) CRn(4) CRd(4) coproc(4) opc2(3) 0 CRm(4) + + @syntax "cdp2" <cp> <undef_opc1> <creg_D> <creg_N> <creg_M> <undef_opc2> + + @conv { + + cp = CoProcessor(coproc) + undef_opc1 = RawValue(opc1) + creg_D = CRegister(CRd) + creg_N = CRegister(CRn) + creg_M = CRegister(CRm) + undef_opc2 = RawValue(opc2) + + } + +} + +@encoding (A2) { + + @word 1 1 1 1 1 1 1 0 opc1(4) CRn(4) CRd(4) coproc(4) opc2(3) 0 CRm(4) + + @syntax "cdp2" <cp> <undef_opc1> <creg_D> <creg_N> <creg_M> <undef_opc2> + + @conv { + + cp = CoProcessor(coproc) + undef_opc1 = RawValue(opc1) + creg_D = CRegister(CRd) + creg_N = CRegister(CRn) + creg_M = CRegister(CRm) + undef_opc2 = RawValue(opc2) + + } + +} + diff --git a/plugins/arm/v7/opdefs/clrex_A8832.d b/plugins/arm/v7/opdefs/clrex_A8832.d new file mode 100644 index 0000000..4f313f2 --- /dev/null +++ b/plugins/arm/v7/opdefs/clrex_A8832.d @@ -0,0 +1,39 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title CLREX + +@desc Clear-Exclusive clears the local record of the executing processor that an address has had a request for an exclusive access. + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 1 0 1 1 1 1 + +} + +@encoding (A1) { + + @word 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 + +} + diff --git a/plugins/arm/v7/opdefs/clz_A8833.d b/plugins/arm/v7/opdefs/clz_A8833.d new file mode 100644 index 0000000..d4fdac6 --- /dev/null +++ b/plugins/arm/v7/opdefs/clz_A8833.d @@ -0,0 +1,63 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title CLZ + +@desc Count Leading Zeros returns the number of binary zero bits before the first binary one bit in a value. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 1 1 Rm(4) 1 1 1 1 Rd(4) 1 0 0 0 Rm(4) + + @syntax <reg_D> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 1 1 0 1 1 1 1 Rd(4) 1 1 1 1 0 0 0 1 Rm(4) + + @syntax <reg_D> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/cmn_A8834.d b/plugins/arm/v7/opdefs/cmn_A8834.d new file mode 100644 index 0000000..fc0b19f --- /dev/null +++ b/plugins/arm/v7/opdefs/cmn_A8834.d @@ -0,0 +1,63 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title CMN (immediate) + +@desc Compare Negative (immediate) adds a register value and an immediate value. It updates the condition flags based on the result, and discards the result. + +@encoding (T1) { + + @word 1 1 1 1 0 i(1) 0 1 0 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm8(8) + + @syntax <reg_N> <imm32> + + @conv { + + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 0 1 1 1 Rn(4) 0 0 0 0 imm12(12) + + @syntax <reg_N> <imm32> + + @conv { + + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/cmn_A8835.d b/plugins/arm/v7/opdefs/cmn_A8835.d new file mode 100644 index 0000000..cd228de --- /dev/null +++ b/plugins/arm/v7/opdefs/cmn_A8835.d @@ -0,0 +1,80 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title CMN (register) + +@desc Compare Negative (register) adds a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result. + +@encoding (t1) { + + @half 0 1 0 0 0 0 1 0 1 1 Rm(3) Rn(3) + + @syntax <reg_N> <reg_M> + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 1 1 0 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm2(2) type(2) Rm(4) + + @syntax ".W" <reg_N> <reg_M> <?shift> + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 1 1 1 Rn(4) 0 0 0 0 imm5(5) type(2) 0 Rm(4) + + @syntax <reg_N> <reg_M> <?shift> + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/cmn_A8836.d b/plugins/arm/v7/opdefs/cmn_A8836.d new file mode 100644 index 0000000..ad58482 --- /dev/null +++ b/plugins/arm/v7/opdefs/cmn_A8836.d @@ -0,0 +1,49 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title CMN (register-shifted register) + +@desc Compare Negative (register-shifted register) adds a register value and a register-shifted register value. It updates the condition flags based on the result, and discards the result. + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 1 1 1 Rn(4) 0 0 0 0 Rs(4) 0 type(2) 1 Rm(4) + + @syntax <reg_N> <reg_M> <reg_shift> + + @conv { + + reg_shift = RegisterShift(type, Rs) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/cmp_A8837.d b/plugins/arm/v7/opdefs/cmp_A8837.d new file mode 100644 index 0000000..76b7a76 --- /dev/null +++ b/plugins/arm/v7/opdefs/cmp_A8837.d @@ -0,0 +1,78 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title CMP (immediate) + +@desc Compare (immediate) subtracts an immediate value from a register value. It updates the condition flags based on the result, and discards the result. + +@encoding (t1) { + + @half 0 0 1 0 1 Rn(3) imm8(8) + + @syntax <reg_N> <imm32> + + @conv { + + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 0 i(1) 0 1 1 0 1 1 Rn(4) 0 imm3(3) 1 1 1 1 imm8(8) + + @syntax ".W" <reg_N> <imm32> + + @conv { + + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 0 1 0 1 Rn(4) 0 0 0 0 imm12(12) + + @syntax <reg_N> <imm32> + + @conv { + + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/cmp_A8838.d b/plugins/arm/v7/opdefs/cmp_A8838.d new file mode 100644 index 0000000..cd02543 --- /dev/null +++ b/plugins/arm/v7/opdefs/cmp_A8838.d @@ -0,0 +1,95 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title CMP (register) + +@desc Compare (register) subtracts an optionally-shifted register value from a register value. It updates the condition flags based on the result, and discards the result. + +@encoding (t1) { + + @half 0 1 0 0 0 0 1 0 1 0 Rm(3) Rn(3) + + @syntax <reg_N> <reg_M> + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (t2) { + + @half 0 1 0 0 0 1 0 1 N(1) Rm(4) Rn(3) + + @syntax <reg_N> <reg_M> + + @conv { + + reg_N = Register(N:Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (T3) { + + @word 1 1 1 0 1 0 1 1 1 0 1 1 Rn(4) 0 imm3(3) 1 1 1 1 imm2(2) type(2) Rm(4) + + @syntax ".W" <reg_N> <reg_M> <?shift> + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 1 0 1 Rn(4) 0 0 0 0 imm5(5) type(2) 0 Rm(4) + + @syntax <reg_N> <reg_M> <?shift> + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/cmp_A8839.d b/plugins/arm/v7/opdefs/cmp_A8839.d new file mode 100644 index 0000000..45ed0f9 --- /dev/null +++ b/plugins/arm/v7/opdefs/cmp_A8839.d @@ -0,0 +1,49 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title CMP (register-shifted register) + +@desc Compare (register-shifted register) subtracts a register-shifted register value from a register value. It updates the condition flags based on the result, and discards the result. + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 1 0 1 Rn(4) 0 0 0 0 Rs(4) 0 type(2) 1 Rm(4) + + @syntax <reg_N> <reg_M> <reg_shift> + + @conv { + + reg_shift = RegisterShift(type, Rs) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/dbg_A8842.d b/plugins/arm/v7/opdefs/dbg_A8842.d new file mode 100644 index 0000000..62142f5 --- /dev/null +++ b/plugins/arm/v7/opdefs/dbg_A8842.d @@ -0,0 +1,61 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title DBG + +@desc Debug Hint provides a hint to debug and related systems. See their documentation for what use (if any) they make of this instruction. + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 option(4) + + @syntax <undef_option> + + @conv { + + undef_option = RawValue(option) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 option(4) + + @syntax <undef_option> + + @conv { + + undef_option = RawValue(option) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/dmb_A8843.d b/plugins/arm/v7/opdefs/dmb_A8843.d new file mode 100644 index 0000000..34f053a --- /dev/null +++ b/plugins/arm/v7/opdefs/dmb_A8843.d @@ -0,0 +1,55 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title DMB + +@desc Data Memory Barrier is a memory barrier that ensures the ordering of observations of memory accesses, see Data Memory Barrier (DMB) on page A3-151. + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 0 1 option(4) + + @syntax <limitation> + + @conv { + + limitation = BarrierLimitation(option) + + } + +} + +@encoding (A1) { + + @word 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 1 option(4) + + @syntax <limitation> + + @conv { + + limitation = BarrierLimitation(option) + + } + +} + diff --git a/plugins/arm/v7/opdefs/dsb_A8844.d b/plugins/arm/v7/opdefs/dsb_A8844.d new file mode 100644 index 0000000..512220c --- /dev/null +++ b/plugins/arm/v7/opdefs/dsb_A8844.d @@ -0,0 +1,55 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title DSB + +@desc Data Synchronization Barrier is a memory barrier that ensures the completion of memory accesses, see Data Synchronization Barrier (DSB) on page A3-152. + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 0 0 option(4) + + @syntax <limitation> + + @conv { + + limitation = BarrierLimitation(option) + + } + +} + +@encoding (A1) { + + @word 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 option(4) + + @syntax <limitation> + + @conv { + + limitation = BarrierLimitation(option) + + } + +} + diff --git a/plugins/arm/v7/opdefs/eor_A8846.d b/plugins/arm/v7/opdefs/eor_A8846.d new file mode 100644 index 0000000..38dc858 --- /dev/null +++ b/plugins/arm/v7/opdefs/eor_A8846.d @@ -0,0 +1,74 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title EOR (immediate) + +@desc Bitwise Exclusive OR (immediate) performs a bitwise Exclusive OR of a register value and an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +@encoding (T1) { + + @word 1 1 1 1 0 i(1) 0 0 1 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) + + @syntax <reg_D> <reg_N> <imm32> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + setflags = (S == '1') + imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 0 0 0 1 S(1) Rn(4) Rd(4) imm12(12) + + @syntax <reg_D> <reg_N> <imm32> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + setflags = (S == '1') + imm32 = ARMExpandImm_C(imm12, 0) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/eor_A8847.d b/plugins/arm/v7/opdefs/eor_A8847.d new file mode 100644 index 0000000..66643a1 --- /dev/null +++ b/plugins/arm/v7/opdefs/eor_A8847.d @@ -0,0 +1,92 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title EOR (register) + +@desc Bitwise Exclusive OR (register) performs a bitwise Exclusive OR of a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +@encoding (t1) { + + @half 0 1 0 0 0 0 0 0 0 1 Rm(3) Rdn(3) + + @syntax "eors" <reg_DN> <reg_M> + + @conv { + + reg_DN = Register(Rdn) + reg_M = Register(Rm) + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 1 0 1 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <?shift> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm3:imm2) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 0 0 1 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <?shift> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm5) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/eor_A8848.d b/plugins/arm/v7/opdefs/eor_A8848.d new file mode 100644 index 0000000..f38fa74 --- /dev/null +++ b/plugins/arm/v7/opdefs/eor_A8848.d @@ -0,0 +1,52 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title EOR (register-shifted register) + +@desc Bitwise Exclusive OR (register-shifted register) performs a bitwise Exclusive OR of a register value and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. + +@encoding (A1) { + + @word cond(4) 0 0 0 0 0 0 1 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <reg_shift> + + @conv { + + reg_shift = RegisterShift(type, Rs) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldr_A8862.d b/plugins/arm/v7/opdefs/ldr_A8862.d new file mode 100644 index 0000000..03df506 --- /dev/null +++ b/plugins/arm/v7/opdefs/ldr_A8862.d @@ -0,0 +1,98 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDR (immediate, Thumb) + +@desc Load Register (immediate) calculates an address from a base register value and an immediate offset, loads a word from memory, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (t1) { + + @half 0 1 1 0 1 imm5(5) Rn(3) Rt(3) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm5:'00', 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + + } + +} + +@encoding (t2) { + + @half 1 0 0 1 1 Rt(3) imm8(8) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + imm32 = ZeroExtend(imm8:'00', 32) + SP = Register(13) + mem_access = MakeMemoryAccess(SP, imm32, NULL, true, true, false) + + } + +} + +@encoding (T3) { + + @word 1 1 1 1 1 0 0 0 1 1 0 1 Rn(4) Rt(4) imm12(12) + + @syntax ".W" <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + + } + +} + +@encoding (T4) { + + @word 1 1 1 1 1 0 0 0 0 1 0 1 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + index = (P == '1') + add = (U == '1') + wback = (W == '1') + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldr_A8863.d b/plugins/arm/v7/opdefs/ldr_A8863.d new file mode 100644 index 0000000..0d0ce1f --- /dev/null +++ b/plugins/arm/v7/opdefs/ldr_A8863.d @@ -0,0 +1,53 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDR (immediate, ARM) + +@desc Load Register (immediate) calculates an address from a base register value and an immediate offset, loads a word from memory, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (A1) { + + @word cond(4) 0 1 0 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) imm12(12) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + index = (P == '1') + add = (U == '1') + wback = (P == '0') || (W == '1') + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldr_A8864.d b/plugins/arm/v7/opdefs/ldr_A8864.d new file mode 100644 index 0000000..74afa2d --- /dev/null +++ b/plugins/arm/v7/opdefs/ldr_A8864.d @@ -0,0 +1,99 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDR (literal) + +@desc Load Register (literal) calculates an address from the PC value and an immediate offset, loads a word from memory, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (t1) { + + @half 0 1 0 0 1 Rt(3) imm8(8) + + @syntax <reg_T> <imm32> + + @conv { + + reg_T = Register(Rt) + imm32 = ZeroExtend(imm8:'00', 32) + + } + + @hooks { + + fetch = help_fetching_with_instruction_ldr_literal_from_thumb + post = post_process_ldr_instructions + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 0 U(1) 1 0 1 1 1 1 1 Rt(4) imm12(12) + + @syntax ".W" <reg_T> <imm32> + + @conv { + + reg_T = Register(Rt) + imm32 = ZeroExtend(imm12, 32) + + } + + @hooks { + + fetch = help_fetching_with_instruction_ldr_literal_from_thumb + post = post_process_ldr_instructions + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 0 1 U(1) 0 0 1 1 1 1 1 Rt(4) imm12(12) + + @syntax <reg_T> <imm32> + + @conv { + + reg_T = Register(Rt) + imm32 = ZeroExtend(imm12, 32) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + + @hooks { + + fetch = help_fetching_with_instruction_ldr_literal_from_arm + post = post_process_ldr_instructions + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldr_A8865.d b/plugins/arm/v7/opdefs/ldr_A8865.d new file mode 100644 index 0000000..ebb4e09 --- /dev/null +++ b/plugins/arm/v7/opdefs/ldr_A8865.d @@ -0,0 +1,62 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDR (register, Thumb) + +@desc Load Register (register) calculates an address from a base register value and an offset register value, loads a word from memory, and writes it to a register. The offset register value can optionally be shifted. For information about memory accesses, see Memory accesses on page A8-294. The Thumb form of LDR (register) does not support register writeback. + +@encoding (t1) { + + @half 0 1 0 1 1 0 0 Rm(3) Rn(3) Rt(3) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, false, false) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 0 0 1 0 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) + + @syntax ".W" <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(0, imm2) + mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, false, false) + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldr_A8866.d b/plugins/arm/v7/opdefs/ldr_A8866.d new file mode 100644 index 0000000..b161043 --- /dev/null +++ b/plugins/arm/v7/opdefs/ldr_A8866.d @@ -0,0 +1,54 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDR (register, ARM) + +@desc Load Register (register) calculates an address from a base register value and an offset register value, loads a word from memory, and writes it to a register. The offset register value can optionally be shifted. For information about memory accesses, see Memory accesses on page A8-294. + +@encoding (A1) { + + @word cond(4) 0 1 1 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + index = (P == '1') + add = (U == '1') + wback = (P == '0') || (W == '1') + shift = DecodeImmShift(type, imm5) + mem_access = MakeMemoryAccess(reg_N, reg_M, shift, index, add, wback) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldrb_A8867.d b/plugins/arm/v7/opdefs/ldrb_A8867.d new file mode 100644 index 0000000..2dea64e --- /dev/null +++ b/plugins/arm/v7/opdefs/ldrb_A8867.d @@ -0,0 +1,81 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDRB (immediate, Thumb) + +@desc Load Register Byte (immediate) calculates an address from a base register value and an immediate offset, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (t1) { + + @half 0 1 1 1 1 imm5(5) Rn(3) Rt(3) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm5, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 0 1 0 0 1 Rn(4) Rt(4) imm12(12) + + @syntax ".W" <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + + } + +} + +@encoding (T3) { + + @word 1 1 1 1 1 0 0 0 0 0 0 1 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + index = (P == '1') + add = (U == '1') + wback = (W == '1') + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldrb_A8868.d b/plugins/arm/v7/opdefs/ldrb_A8868.d new file mode 100644 index 0000000..519c309 --- /dev/null +++ b/plugins/arm/v7/opdefs/ldrb_A8868.d @@ -0,0 +1,53 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDRB (immediate, ARM) + +@desc Load Register Byte (immediate) calculates an address from a base register value and an immediate offset, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (A1) { + + @word cond(4) 0 1 0 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) imm12(12) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + index = (P == '1') + add = (U == '1') + wback = (P == '0') || (W == '1') + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldrb_A8869.d b/plugins/arm/v7/opdefs/ldrb_A8869.d new file mode 100644 index 0000000..fb80049 --- /dev/null +++ b/plugins/arm/v7/opdefs/ldrb_A8869.d @@ -0,0 +1,63 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDRB (literal) + +@desc Load Register Byte (literal) calculates an address from the PC value and an immediate offset, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 0 U(1) 0 0 1 1 1 1 1 Rt(4) imm12(12) + + @syntax <reg_T> <imm32> + + @conv { + + reg_T = Register(Rt) + imm32 = ZeroExtend(imm12, 32) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 0 1 U(1) 1 0 1 1 1 1 1 Rt(4) imm12(12) + + @syntax <reg_T> <imm32> + + @conv { + + reg_T = Register(Rt) + imm32 = ZeroExtend(imm12, 32) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldrb_A8870.d b/plugins/arm/v7/opdefs/ldrb_A8870.d new file mode 100644 index 0000000..35f95ab --- /dev/null +++ b/plugins/arm/v7/opdefs/ldrb_A8870.d @@ -0,0 +1,89 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDRB (register) + +@desc Load Register Byte (register) calculates an address from a base register value and an offset register value, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. The offset register value can optionally be shifted. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (t1) { + + @half 0 1 0 1 1 1 0 Rm(3) Rn(3) Rt(3) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, true, false) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 0 0 0 0 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) + + @syntax ".W" <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(0, imm2) + mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, true, false) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + index = (P == '1') + add = (U == '1') + wback = (P == '0') || (W == '1') + shift = DecodeImmShift(type, imm5) + mem_access = MakeMemoryAccess(reg_N, reg_M, shift, index, add, wback) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldrbt_A8871.d b/plugins/arm/v7/opdefs/ldrbt_A8871.d new file mode 100644 index 0000000..0bf9c3c --- /dev/null +++ b/plugins/arm/v7/opdefs/ldrbt_A8871.d @@ -0,0 +1,93 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDRBT + +@desc Load Register Byte Unprivileged loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRBT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 0 0 0 0 1 Rn(4) Rt(4) 1 1 1 0 imm8(8) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 0 0 U(1) 1 1 1 Rn(4) Rt(4) imm12(12) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + add = (U == '1') + imm32 = ZeroExtend(imm12, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + +@encoding (A2) { + + @word cond(4) 0 1 1 0 U(1) 1 1 1 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + add = (U == '1') + shift = DecodeImmShift(type, imm5) + mem_access = MakeMemoryAccess(reg_N, reg_M, shift, false, add, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldrd_A8872.d b/plugins/arm/v7/opdefs/ldrd_A8872.d new file mode 100644 index 0000000..c73fdca --- /dev/null +++ b/plugins/arm/v7/opdefs/ldrd_A8872.d @@ -0,0 +1,75 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDRD (immediate) + +@desc Load Register Dual (immediate) calculates an address from a base register value and an immediate offset, loads two words from memory, and writes them to two registers. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) Rt2(4) imm8(8) + + @syntax <reg_T> <reg_T2> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + index = (P == '1') + add = (U == '1') + wback = (W == '1') + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) imm4H(4) 1 1 0 1 imm4L(4) + + @syntax <reg_T> <reg_T2> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(reg_T) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + index = (P == '1') + add = (U == '1') + wback = (P == '0') || (W == '1') + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldrd_A8873.d b/plugins/arm/v7/opdefs/ldrd_A8873.d new file mode 100644 index 0000000..828e4a3 --- /dev/null +++ b/plugins/arm/v7/opdefs/ldrd_A8873.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDRD (literal) + +@desc Load Register Dual (literal) calculates an address from the PC value and an immediate offset, loads two words from memory, and writes them to two registers. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 P(1) U(1) 1 W(1) 1 1 1 1 1 Rt(4) Rt2(4) imm8(8) + + @syntax <reg_T> <reg_T2> <imm32> + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + imm32 = ZeroExtend(imm8:'00', 32) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 U(1) 1 0 0 1 1 1 1 Rt(4) imm4H(4) 1 1 0 1 imm4L(4) + + @syntax <reg_T> <reg_T2> <imm32> + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(reg_T) + imm32 = ZeroExtend(imm4H:imm4L, 32) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldrd_A8874.d b/plugins/arm/v7/opdefs/ldrd_A8874.d new file mode 100644 index 0000000..ed055a6 --- /dev/null +++ b/plugins/arm/v7/opdefs/ldrd_A8874.d @@ -0,0 +1,54 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDRD (register) + +@desc Load Register Dual (register) calculates an address from a base register value and a register offset, loads two words from memory, and writes them to two registers. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (A1) { + + @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) 0 0 0 0 1 1 0 1 Rm(4) + + @syntax <reg_T> <reg_T2> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(reg_T) + reg_N = Register(Rn) + reg_M = Register(Rm) + index = (P == '1') + add = (U == '1') + wback = (P == '0') || (W == '1') + mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, index, add, wback) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldrex_A8875.d b/plugins/arm/v7/opdefs/ldrex_A8875.d new file mode 100644 index 0000000..b915061 --- /dev/null +++ b/plugins/arm/v7/opdefs/ldrex_A8875.d @@ -0,0 +1,66 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDREX + +@desc Load Register Exclusive calculates an address from a base register value and an immediate offset, loads a word from memory, writes it to a register and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 0 0 1 0 1 Rn(4) Rt(4) 1 1 1 1 imm8(8) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, false, false) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 0 1 Rn(4) Rt(4) 1 1 1 1 1 0 0 1 1 1 1 1 + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldrexb_A8876.d b/plugins/arm/v7/opdefs/ldrexb_A8876.d new file mode 100644 index 0000000..e398ef2 --- /dev/null +++ b/plugins/arm/v7/opdefs/ldrexb_A8876.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDREXB + +@desc Load Register Exclusive Byte derives an address from a base register value, loads a byte from memory, zero-extends it to form a 32-bit word, writes it to a register and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 0 1 1 0 1 Rn(4) Rt(4) 1 1 1 1 0 1 0 0 1 1 1 1 + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 1 0 1 Rn(4) Rt(4) 1 1 1 1 1 0 0 1 1 1 1 1 + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldrexd_A8877.d b/plugins/arm/v7/opdefs/ldrexd_A8877.d new file mode 100644 index 0000000..0188cb7 --- /dev/null +++ b/plugins/arm/v7/opdefs/ldrexd_A8877.d @@ -0,0 +1,67 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDREXD + +@desc Load Register Exclusive Doubleword derives an address from a base register value, loads a 64-bit doubleword from memory, writes it to two registers and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 0 1 1 0 1 Rn(4) Rt(4) Rt2(4) 0 1 1 1 1 1 1 1 + + @syntax <reg_T> <reg_T2> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 1 1 Rn(4) Rt(4) 1 1 1 1 1 0 0 1 1 1 1 1 + + @syntax <reg_T> <reg_T2> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(reg_T) + reg_N = Register(Rn) + mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldrexh_A8878.d b/plugins/arm/v7/opdefs/ldrexh_A8878.d new file mode 100644 index 0000000..8e9366f --- /dev/null +++ b/plugins/arm/v7/opdefs/ldrexh_A8878.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDREXH + +@desc Load Register Exclusive Halfword derives an address from a base register value, loads a halfword from memory, zero-extends it to form a 32-bit word, writes it to a register and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 0 1 1 0 1 Rn(4) Rt(4) 1 1 1 1 0 1 0 1 1 1 1 1 + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 1 1 1 Rn(4) Rt(4) 1 1 1 1 1 0 0 1 1 1 1 1 + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldrh_A8879.d b/plugins/arm/v7/opdefs/ldrh_A8879.d new file mode 100644 index 0000000..3b57bf8 --- /dev/null +++ b/plugins/arm/v7/opdefs/ldrh_A8879.d @@ -0,0 +1,81 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDRH (immediate, Thumb) + +@desc Load Register Halfword (immediate) calculates an address from a base register value and an immediate offset, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (t1) { + + @half 1 0 0 0 1 imm5(5) Rn(3) Rt(3) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm5:'0', 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 0 1 0 1 1 Rn(4) Rt(4) imm12(12) + + @syntax ".W" <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + + } + +} + +@encoding (T3) { + + @word 1 1 1 1 1 0 0 0 0 0 1 1 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + index = (P == '1') + add = (U == '1') + wback = (W == '1') + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldrh_A8880.d b/plugins/arm/v7/opdefs/ldrh_A8880.d new file mode 100644 index 0000000..f5f7ab0 --- /dev/null +++ b/plugins/arm/v7/opdefs/ldrh_A8880.d @@ -0,0 +1,53 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDRH (immediate, ARM) + +@desc Load Register Halfword (immediate) calculates an address from a base register value and an immediate offset, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (A1) { + + @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) imm4H(4) 1 0 1 1 imm4L(4) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + index = (P == '1') + add = (U == '1') + wback = (P == '0') || (W == '1') + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldrh_A8881.d b/plugins/arm/v7/opdefs/ldrh_A8881.d new file mode 100644 index 0000000..59005e4 --- /dev/null +++ b/plugins/arm/v7/opdefs/ldrh_A8881.d @@ -0,0 +1,63 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDRH (literal) + +@desc Load Register Halfword (literal) calculates an address from the PC value and an immediate offset, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 0 U(1) 0 1 1 1 1 1 1 Rt(4) imm12(12) + + @syntax <reg_T> <imm32> + + @conv { + + reg_T = Register(Rt) + imm32 = ZeroExtend(imm12, 32) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 1 1 1 1 1 Rt(4) imm4H(4) 1 0 1 1 imm4L(4) + + @syntax <reg_T> <imm32> + + @conv { + + reg_T = Register(Rt) + imm32 = ZeroExtend(imm4H:imm4L, 32) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldrh_A8882.d b/plugins/arm/v7/opdefs/ldrh_A8882.d new file mode 100644 index 0000000..823bf24 --- /dev/null +++ b/plugins/arm/v7/opdefs/ldrh_A8882.d @@ -0,0 +1,88 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDRH (register) + +@desc Load Register Halfword (register) calculates an address from a base register value and an offset register value, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (t1) { + + @half 0 1 0 1 1 0 1 Rm(3) Rn(3) Rt(3) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, true, false) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 0 0 0 1 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) + + @syntax ".W" <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(0, imm2) + mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, true, false) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) 0 0 0 0 1 0 1 1 Rm(4) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + index = (P == '1') + add = (U == '1') + wback = (P == '0') || (W == '1') + mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, index, add, wback) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldrht_A8883.d b/plugins/arm/v7/opdefs/ldrht_A8883.d new file mode 100644 index 0000000..8f8f015 --- /dev/null +++ b/plugins/arm/v7/opdefs/ldrht_A8883.d @@ -0,0 +1,92 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDRHT + +@desc Load Register Halfword Unprivileged loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRHT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value. + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 0 0 0 1 1 Rn(4) Rt(4) 1 1 1 0 imm8(8) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 U(1) 1 1 1 Rn(4) Rt(4) imm4H(4) 1 0 1 1 imm4L(4) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + add = (U == '1') + imm32 = ZeroExtend(imm4H:imm4L, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + +@encoding (A2) { + + @word cond(4) 0 0 0 0 U(1) 0 1 1 Rn(4) Rt(4) 0 0 0 0 1 0 1 1 Rm(4) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + add = (U == '1') + mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, false, add, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldrsb_A8884.d b/plugins/arm/v7/opdefs/ldrsb_A8884.d new file mode 100644 index 0000000..fc41134 --- /dev/null +++ b/plugins/arm/v7/opdefs/ldrsb_A8884.d @@ -0,0 +1,90 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDRSB (immediate) + +@desc Load Register Signed Byte (immediate) calculates an address from a base register value and an immediate offset, loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 1 1 0 0 1 Rn(4) Rt(4) imm12(12) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 1 0 0 0 1 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + index = (P == '1') + add = (U == '1') + wback = (W == '1') + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) imm4H(4) 1 1 0 1 imm4L(4) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + index = (P == '1') + add = (U == '1') + wback = (P == '0') || (W == '1') + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldrsb_A8885.d b/plugins/arm/v7/opdefs/ldrsb_A8885.d new file mode 100644 index 0000000..6cb1d34 --- /dev/null +++ b/plugins/arm/v7/opdefs/ldrsb_A8885.d @@ -0,0 +1,63 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDRSB (literal) + +@desc Load Register Signed Byte (literal) calculates an address from the PC value and an immediate offset, loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 1 U(1) 0 0 1 1 1 1 1 Rt(4) imm12(12) + + @syntax <reg_T> <imm32> + + @conv { + + reg_T = Register(Rt) + imm32 = ZeroExtend(imm12, 32) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 U(1) 1 0 1 1 1 1 1 Rt(4) imm4H(4) 1 1 0 1 imm4L(4) + + @syntax <reg_T> <imm32> + + @conv { + + reg_T = Register(Rt) + imm32 = ZeroExtend(imm4H:imm4L, 32) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldrsb_A8886.d b/plugins/arm/v7/opdefs/ldrsb_A8886.d new file mode 100644 index 0000000..4a66278 --- /dev/null +++ b/plugins/arm/v7/opdefs/ldrsb_A8886.d @@ -0,0 +1,88 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDRSB (register) + +@desc Load Register Signed Byte (register) calculates an address from a base register value and an offset register value, loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (t1) { + + @half 0 1 0 1 0 1 1 Rm(3) Rn(3) Rt(3) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, true, false) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 1 0 0 0 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) + + @syntax ".W" <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(0, imm2) + mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, true, false) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) 0 0 0 0 1 1 0 1 Rm(4) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + index = (P == '1') + add = (U == '1') + wback = (P == '0') || (W == '1') + mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, index, add, wback) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldrsbt_A8887.d b/plugins/arm/v7/opdefs/ldrsbt_A8887.d new file mode 100644 index 0000000..b545f32 --- /dev/null +++ b/plugins/arm/v7/opdefs/ldrsbt_A8887.d @@ -0,0 +1,92 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDRSBT + +@desc Load Register Signed Byte Unprivileged loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRSBT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value. + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 1 0 0 0 1 Rn(4) Rt(4) 1 1 1 0 imm8(8) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 U(1) 1 1 1 Rn(4) Rt(4) imm4H(4) 1 1 0 1 imm4L(4) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + add = (U == '1') + imm32 = ZeroExtend(imm4H:imm4L, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + +@encoding (A2) { + + @word cond(4) 0 0 0 0 U(1) 0 1 1 Rn(4) Rt(4) 0 0 0 0 1 1 0 1 Rm(4) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + add = (U == '1') + mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, false, add, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldrsh_A8888.d b/plugins/arm/v7/opdefs/ldrsh_A8888.d new file mode 100644 index 0000000..f01024c --- /dev/null +++ b/plugins/arm/v7/opdefs/ldrsh_A8888.d @@ -0,0 +1,90 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDRSH (immediate) + +@desc Load Register Signed Halfword (immediate) calculates an address from a base register value and an immediate offset, loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 1 1 0 1 1 Rn(4) Rt(4) imm12(12) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 1 0 0 1 1 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + index = (P == '1') + add = (U == '1') + wback = (W == '1') + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) imm4H(4) 1 1 1 1 imm4L(4) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + index = (P == '1') + add = (U == '1') + wback = (P == '0') || (W == '1') + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldrsh_A8889.d b/plugins/arm/v7/opdefs/ldrsh_A8889.d new file mode 100644 index 0000000..074cd5c --- /dev/null +++ b/plugins/arm/v7/opdefs/ldrsh_A8889.d @@ -0,0 +1,63 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDRSH (literal) + +@desc Load Register Signed Halfword (literal) calculates an address from the PC value and an immediate offset, loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 1 U(1) 0 1 1 1 1 1 1 Rt(4) imm12(12) + + @syntax <reg_T> <imm32> + + @conv { + + reg_T = Register(Rt) + imm32 = ZeroExtend(imm12, 32) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 U(1) 1 0 1 1 1 1 1 Rt(4) imm4H(4) 1 1 1 1 imm4L(4) + + @syntax <reg_T> <imm32> + + @conv { + + reg_T = Register(Rt) + imm32 = ZeroExtend(imm4H:imm4L, 32) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldrsh_A8890.d b/plugins/arm/v7/opdefs/ldrsh_A8890.d new file mode 100644 index 0000000..eac6c09 --- /dev/null +++ b/plugins/arm/v7/opdefs/ldrsh_A8890.d @@ -0,0 +1,88 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDRSH (register) + +@desc Load Register Signed Halfword (register) calculates an address from a base register value and an offset register value, loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (t1) { + + @half 0 1 0 1 1 1 1 Rm(3) Rn(3) Rt(3) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, true, false) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 1 0 0 1 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) + + @syntax ".W" <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(0, imm2) + mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, true, false) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) 0 0 0 0 1 1 1 1 Rm(4) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + index = (P == '1') + add = (U == '1') + wback = (P == '0') || (W == '1') + mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, index, add, wback) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldrsht_A8891.d b/plugins/arm/v7/opdefs/ldrsht_A8891.d new file mode 100644 index 0000000..355178b --- /dev/null +++ b/plugins/arm/v7/opdefs/ldrsht_A8891.d @@ -0,0 +1,92 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDRSHT + +@desc Load Register Signed Halfword Unprivileged loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRSHT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value. + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 1 0 0 1 1 Rn(4) Rt(4) 1 1 1 0 imm8(8) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 U(1) 1 1 1 Rn(4) Rt(4) imm4H(4) 1 1 1 1 imm4L(4) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + add = (U == '1') + imm32 = ZeroExtend(imm4H:imm4L, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + +@encoding (A2) { + + @word cond(4) 0 0 0 0 U(1) 0 1 1 Rn(4) Rt(4) 0 0 0 0 1 1 1 1 Rm(4) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + add = (U == '1') + mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, false, add, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/ldrt_A8892.d b/plugins/arm/v7/opdefs/ldrt_A8892.d new file mode 100644 index 0000000..e13f0e7 --- /dev/null +++ b/plugins/arm/v7/opdefs/ldrt_A8892.d @@ -0,0 +1,93 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDRT + +@desc Load Register Unprivileged loads a word from memory, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 0 0 1 0 1 Rn(4) Rt(4) 1 1 1 0 imm8(8) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 0 0 U(1) 0 1 1 Rn(4) Rt(4) imm12(12) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + add = (U == '1') + imm32 = ZeroExtend(imm12, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + +@encoding (A2) { + + @word cond(4) 0 1 1 0 U(1) 0 1 1 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + add = (U == '1') + shift = DecodeImmShift(type, imm5) + mem_access = MakeMemoryAccess(reg_N, reg_M, shift, false, add, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/lsl_A8894.d b/plugins/arm/v7/opdefs/lsl_A8894.d new file mode 100644 index 0000000..89924c6 --- /dev/null +++ b/plugins/arm/v7/opdefs/lsl_A8894.d @@ -0,0 +1,91 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LSL (immediate) + +@desc Logical Shift Left (immediate) shifts a register value left by an immediate number of bits, shifting in zeros, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +@encoding (t1) { + + @half 0 0 0 0 0 imm5(5) Rm(3) Rd(3) + + @syntax "lsls" <reg_D> <reg_M> <shift_imm> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_imm = DecodeImmShift('00', imm5) + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 0 0 Rm(4) + + @syntax <reg_D> <reg_M> <shift_imm> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + setflags = (S == '1') + shift_imm = DecodeImmShift('00', imm3:imm2) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 0 0 0 Rm(4) + + @syntax <reg_D> <reg_M> <shift_imm> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + setflags = (S == '1') + shift_imm = DecodeImmShift('00', imm5) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/lsl_A8895.d b/plugins/arm/v7/opdefs/lsl_A8895.d new file mode 100644 index 0000000..4ac5ab6 --- /dev/null +++ b/plugins/arm/v7/opdefs/lsl_A8895.d @@ -0,0 +1,90 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LSL (register) + +@desc Logical Shift Left (register) shifts a register value left by a variable number of bits, shifting in zeros, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. + +@encoding (t1) { + + @half 0 1 0 0 0 0 0 0 1 0 Rm(3) Rdn(3) + + @syntax "lsls" <reg_DN> <reg_M> + + @conv { + + reg_DN = Register(Rdn) + reg_M = Register(Rm) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 1 0 0 0 0 S(1) Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) Rm(4) 0 0 0 1 Rn(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/lsr_A8896.d b/plugins/arm/v7/opdefs/lsr_A8896.d new file mode 100644 index 0000000..acb9e25 --- /dev/null +++ b/plugins/arm/v7/opdefs/lsr_A8896.d @@ -0,0 +1,91 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LSR (immediate) + +@desc Logical Shift Right (immediate) shifts a register value right by an immediate number of bits, shifting in zeros, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +@encoding (t1) { + + @half 0 0 0 0 1 imm5(5) Rm(3) Rd(3) + + @syntax "lsrs" <reg_D> <reg_M> <shift_imm> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_imm = DecodeImmShift('01', imm5) + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 0 1 Rm(4) + + @syntax <reg_D> <reg_M> <shift_imm> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + setflags = (S == '1') + shift_imm = DecodeImmShift('01', imm3:imm2) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 0 1 0 Rm(4) + + @syntax <reg_D> <reg_M> <shift_imm> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + setflags = (S == '1') + shift_imm = DecodeImmShift('01', imm5) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/lsr_A8897.d b/plugins/arm/v7/opdefs/lsr_A8897.d new file mode 100644 index 0000000..070a152 --- /dev/null +++ b/plugins/arm/v7/opdefs/lsr_A8897.d @@ -0,0 +1,90 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LSR (register) + +@desc Logical Shift Right (register) shifts a register value right by a variable number of bits, shifting in zeros, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. + +@encoding (t1) { + + @half 0 1 0 0 0 0 0 0 1 1 Rm(3) Rdn(3) + + @syntax "lsrs" <reg_DN> <reg_M> + + @conv { + + reg_DN = Register(Rdn) + reg_M = Register(Rm) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 1 0 0 0 1 S(1) Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) Rm(4) 0 0 1 1 Rn(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/mcr_A8898.d b/plugins/arm/v7/opdefs/mcr_A8898.d new file mode 100644 index 0000000..f710d5d --- /dev/null +++ b/plugins/arm/v7/opdefs/mcr_A8898.d @@ -0,0 +1,109 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title MCR, MCR2 + +@desc Move to Coprocessor from ARM core register passes the value of an ARM core register to a coprocessor. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1, opc2, CRn, and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid MCR and MCR2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, MCR accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an MCR instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Traps to the hypervisor on page B1-1247. Note Because of the range of possible traps to Hyp mode, the MCR pseudocode does not show these possible traps. + +@encoding (T1) { + + @word 1 1 1 0 1 1 1 0 opc1(3) 0 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) + + @syntax <cp> <undef_opc1> <reg_T> <creg_N> <creg_M> <?undef_opc2> + + @conv { + + reg_T = Register(Rt) + cp = CoProcessor(coproc) + undef_opc1 = RawValue(opc1) + creg_N = CRegister(CRn) + creg_M = CRegister(CRm) + undef_opc2 = RawValue(opc2) + + } + +} + +@encoding (A1) { + + @word cond(4) 1 1 1 0 opc1(3) 0 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) + + @syntax <cp> <undef_opc1> <reg_T> <creg_N> <creg_M> <?undef_opc2> + + @conv { + + reg_T = Register(Rt) + cp = CoProcessor(coproc) + undef_opc1 = RawValue(opc1) + creg_N = CRegister(CRn) + creg_M = CRegister(CRm) + undef_opc2 = RawValue(opc2) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 1 1 0 opc1(3) 0 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) + + @syntax "mcr2" <cp> <undef_opc1> <reg_T> <creg_N> <creg_M> <?undef_opc2> + + @conv { + + reg_T = Register(Rt) + cp = CoProcessor(coproc) + undef_opc1 = RawValue(opc1) + creg_N = CRegister(CRn) + creg_M = CRegister(CRm) + undef_opc2 = RawValue(opc2) + + } + +} + +@encoding (A2) { + + @word 1 1 1 1 1 1 1 0 opc1(3) 0 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) + + @syntax "mcr2" <cp> <undef_opc1> <reg_T> <creg_N> <creg_M> <?undef_opc2> + + @conv { + + reg_T = Register(Rt) + cp = CoProcessor(coproc) + undef_opc1 = RawValue(opc1) + creg_N = CRegister(CRn) + creg_M = CRegister(CRm) + undef_opc2 = RawValue(opc2) + + } + +} + diff --git a/plugins/arm/v7/opdefs/mcrr_A8899.d b/plugins/arm/v7/opdefs/mcrr_A8899.d new file mode 100644 index 0000000..f643826 --- /dev/null +++ b/plugins/arm/v7/opdefs/mcrr_A8899.d @@ -0,0 +1,105 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title MCRR, MCRR2 + +@desc Move to Coprocessor from two ARM core registers passes the values of two ARM core registers to a coprocessor. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1 and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid MCRR and MCRR2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, MCRR accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an MCRR instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Traps to the hypervisor on page B1-1247. Note Because of the range of possible traps to Hyp mode, the MCRR pseudocode does not show these possible traps. + +@encoding (T1) { + + @word 1 1 1 0 1 1 0 0 0 1 0 0 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) + + @syntax <cp> <undef_opc1> <reg_T> <reg_T2> <creg_M> + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + cp = CoProcessor(coproc) + undef_opc1 = RawValue(opc1) + creg_M = CRegister(CRm) + + } + +} + +@encoding (A1) { + + @word cond(4) 1 1 0 0 0 1 0 0 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) + + @syntax <cp> <undef_opc1> <reg_T> <reg_T2> <creg_M> + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + cp = CoProcessor(coproc) + undef_opc1 = RawValue(opc1) + creg_M = CRegister(CRm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 1 0 0 0 1 0 0 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) + + @syntax "mcrr2" <cp> <undef_opc1> <reg_T> <reg_T2> <creg_M> + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + cp = CoProcessor(coproc) + undef_opc1 = RawValue(opc1) + creg_M = CRegister(CRm) + + } + +} + +@encoding (A2) { + + @word 1 1 1 1 1 1 0 0 0 1 0 0 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) + + @syntax "mcrr2" <cp> <undef_opc1> <reg_T> <reg_T2> <creg_M> + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + cp = CoProcessor(coproc) + undef_opc1 = RawValue(opc1) + creg_M = CRegister(CRm) + + } + +} + diff --git a/plugins/arm/v7/opdefs/mla_A88100.d b/plugins/arm/v7/opdefs/mla_A88100.d new file mode 100644 index 0000000..5d4b4e4 --- /dev/null +++ b/plugins/arm/v7/opdefs/mla_A88100.d @@ -0,0 +1,69 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title MLA + +@desc Multiply Accumulate multiplies two register values, and adds a third register value. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values. In an ARM instruction, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 0 0 0 0 Rn(4) Ra(4) Rd(4) 0 0 0 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <reg_A> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 0 0 1 S(1) Rd(4) Ra(4) Rm(4) 1 0 0 1 Rn(4) + + @syntax <reg_D> <reg_N> <reg_M> <reg_A> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/mls_A88101.d b/plugins/arm/v7/opdefs/mls_A88101.d new file mode 100644 index 0000000..4d10be8 --- /dev/null +++ b/plugins/arm/v7/opdefs/mls_A88101.d @@ -0,0 +1,67 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title MLS + +@desc Multiply and Subtract multiplies two register values, and subtracts the product from a third register value. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 0 0 0 0 Rn(4) Ra(4) Rd(4) 0 0 0 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <reg_A> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 0 1 1 0 Rd(4) Ra(4) Rm(4) 1 0 0 1 Rn(4) + + @syntax <reg_D> <reg_N> <reg_M> <reg_A> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/mov_A88102.d b/plugins/arm/v7/opdefs/mov_A88102.d new file mode 100644 index 0000000..d96baab --- /dev/null +++ b/plugins/arm/v7/opdefs/mov_A88102.d @@ -0,0 +1,124 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title MOV (immediate) + +@desc Move (immediate) writes an immediate value to the destination register. It can optionally update the condition flags based on the value. + +@encoding (t1) { + + @half 0 0 1 0 0 Rd(3) imm8(8) + + @syntax "movs" <reg_D> <imm32> + + @conv { + + reg_D = Register(Rd) + imm32 = ZeroExtend(imm8, 32) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 0 i(1) 0 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm8(8) + + @syntax <reg_D> <imm32> + + @conv { + + reg_D = Register(Rd) + setflags = (S == '1') + imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") + + } + +} + +@encoding (T3) { + + @word 1 1 1 1 0 i(1) 1 0 0 1 0 0 imm4(4) 0 imm3(3) Rd(4) imm8(8) + + @syntax "movw" <reg_D> <imm32> + + @conv { + + reg_D = Register(Rd) + imm32 = ZeroExtend(imm4:i:imm3:imm8, 32) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm12(12) + + @syntax <reg_D> <imm32> + + @conv { + + reg_D = Register(Rd) + setflags = (S == '1') + imm32 = ARMExpandImm_C(imm12, 0) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + +@encoding (A2) { + + @word cond(4) 0 0 1 1 0 0 0 0 imm4(4) Rd(4) imm12(12) + + @syntax "movw" <reg_D> <imm32> + + @conv { + + reg_D = Register(Rd) + imm32 = ZeroExtend(imm4:imm12, 32) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/mov_A88103.d b/plugins/arm/v7/opdefs/mov_A88103.d new file mode 100644 index 0000000..cd3d75a --- /dev/null +++ b/plugins/arm/v7/opdefs/mov_A88103.d @@ -0,0 +1,80 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title MOV (register, Thumb) + +@desc Move (register) copies a value from a register to the destination register. It can optionally update the condition flags based on the value. + +@encoding (t1) { + + @half 0 1 0 0 0 1 1 0 D(1) Rm(4) Rd(3) + + @syntax <reg_D> <reg_M> + + @conv { + + reg_D = Register(D:Rd) + reg_M = Register(Rm) + + } + +} + +@encoding (t2) { + + @half 0 0 0 0 0 0 0 0 0 0 Rm(3) Rd(3) + + @syntax "movs" <reg_D> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + +} + +@encoding (T3) { + + @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 0 0 0 Rd(4) 0 0 0 0 Rm(4) + + @syntax <reg_D> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") + + } + +} + diff --git a/plugins/arm/v7/opdefs/mov_A88104.d b/plugins/arm/v7/opdefs/mov_A88104.d new file mode 100644 index 0000000..d164983 --- /dev/null +++ b/plugins/arm/v7/opdefs/mov_A88104.d @@ -0,0 +1,50 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title MOV (register, ARM) + +@desc Move (register) copies a value from a register to the destination register. It can optionally update the condition flags based on the value. + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) 0 0 0 0 0 0 0 0 Rm(4) + + @syntax <reg_D> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/movt_A88106.d b/plugins/arm/v7/opdefs/movt_A88106.d new file mode 100644 index 0000000..265d008 --- /dev/null +++ b/plugins/arm/v7/opdefs/movt_A88106.d @@ -0,0 +1,63 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title MOVT + +@desc Move Top writes an immediate value to the top halfword of the destination register. It does not affect the contents of the bottom halfword. + +@encoding (T1) { + + @word 1 1 1 1 0 i(1) 1 0 1 1 0 0 imm4(4) 0 imm3(3) Rd(4) imm8(8) + + @syntax <reg_D> <imm16> + + @conv { + + reg_D = Register(Rd) + imm16 = BuildImm16(imm4:i:imm3:imm8) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 0 1 0 0 imm4(4) Rd(4) imm12(12) + + @syntax <reg_D> <imm16> + + @conv { + + reg_D = Register(Rd) + imm16 = BuildImm16(imm4:imm12) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/mrc_A88107.d b/plugins/arm/v7/opdefs/mrc_A88107.d new file mode 100644 index 0000000..fb9714c --- /dev/null +++ b/plugins/arm/v7/opdefs/mrc_A88107.d @@ -0,0 +1,109 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title MRC, MRC2 + +@desc Move to ARM core register from Coprocessor causes a coprocessor to transfer a value to an ARM core register or to the condition flags. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1, opc2, CRn, and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid MRC and MRC2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, MRC accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an MRC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Traps to the hypervisor on page B1-1247. Note Because of the range of possible traps to Hyp mode, the MRC pseudocode does not show these possible traps. + +@encoding (T1) { + + @word 1 1 1 0 1 1 1 0 opc1(3) 1 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) + + @syntax <cp> <undef_opc1> <reg_T> <creg_N> <creg_M> <?undef_opc2> + + @conv { + + reg_T = Register(Rt) + cp = CoProcessor(coproc) + undef_opc1 = RawValue(opc1) + creg_N = CRegister(CRn) + creg_M = CRegister(CRm) + undef_opc2 = RawValue(opc2) + + } + +} + +@encoding (A1) { + + @word cond(4) 1 1 1 0 opc1(3) 1 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) + + @syntax <cp> <undef_opc1> <reg_T> <creg_N> <creg_M> <?undef_opc2> + + @conv { + + reg_T = Register(Rt) + cp = CoProcessor(coproc) + undef_opc1 = RawValue(opc1) + creg_N = CRegister(CRn) + creg_M = CRegister(CRm) + undef_opc2 = RawValue(opc2) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 1 1 0 opc1(3) 1 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) + + @syntax "mrc2" <cp> <undef_opc1> <reg_T> <creg_N> <creg_M> <?undef_opc2> + + @conv { + + reg_T = Register(Rt) + cp = CoProcessor(coproc) + undef_opc1 = RawValue(opc1) + creg_N = CRegister(CRn) + creg_M = CRegister(CRm) + undef_opc2 = RawValue(opc2) + + } + +} + +@encoding (A2) { + + @word 1 1 1 1 1 1 1 0 opc1(3) 1 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) + + @syntax "mrc2" <cp> <undef_opc1> <reg_T> <creg_N> <creg_M> <?undef_opc2> + + @conv { + + reg_T = Register(Rt) + cp = CoProcessor(coproc) + undef_opc1 = RawValue(opc1) + creg_N = CRegister(CRn) + creg_M = CRegister(CRm) + undef_opc2 = RawValue(opc2) + + } + +} + diff --git a/plugins/arm/v7/opdefs/mrrc_A88108.d b/plugins/arm/v7/opdefs/mrrc_A88108.d new file mode 100644 index 0000000..026c0ef --- /dev/null +++ b/plugins/arm/v7/opdefs/mrrc_A88108.d @@ -0,0 +1,105 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title MRRC, MRRC2 + +@desc Move to two ARM core registers from Coprocessor causes a coprocessor to transfer values to two ARM core registers. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1 and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid MRRC and MRRC2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, MRRC accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an MRRC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Traps to the hypervisor on page B1-1247. Note Because of the range of possible traps to Hyp mode, the MRRC pseudocode does not show these possible traps. + +@encoding (T1) { + + @word 1 1 1 0 1 1 0 0 0 1 0 1 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) + + @syntax <cp> <opc> <reg_T> <reg_T2> <creg_M> + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + cp = CoProcessor(coproc) + opc = RawValue(opc1) + creg_M = CRegister(CRm) + + } + +} + +@encoding (A1) { + + @word cond(4) 1 1 0 0 0 1 0 1 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) + + @syntax <cp> <opc> <reg_T> <reg_T2> <creg_M> + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + cp = CoProcessor(coproc) + opc = RawValue(opc1) + creg_M = CRegister(CRm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 1 0 0 0 1 0 1 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) + + @syntax "mrrc2" <cp> <opc> <reg_T> <reg_T2> <creg_M> + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + cp = CoProcessor(coproc) + opc = RawValue(opc1) + creg_M = CRegister(CRm) + + } + +} + +@encoding (A2) { + + @word 1 1 1 1 1 1 0 0 0 1 0 1 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) + + @syntax "mrrc2" <cp> <opc> <reg_T> <reg_T2> <creg_M> + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + cp = CoProcessor(coproc) + opc = RawValue(opc1) + creg_M = CRegister(CRm) + + } + +} + diff --git a/plugins/arm/v7/opdefs/mul_A88114.d b/plugins/arm/v7/opdefs/mul_A88114.d new file mode 100644 index 0000000..fa250b7 --- /dev/null +++ b/plugins/arm/v7/opdefs/mul_A88114.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title MUL + +@desc Multiply multiplies two register values. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values. Optionally, it can update the condition flags based on the result. In the Thumb instruction set, this option is limited to only a few forms of the instruction. Use of this option adversely affects performance on many processor implementations. + +@encoding (t1) { + + @half 0 1 0 0 0 0 1 1 0 1 Rn(3) Rdm(3) + + @syntax "muls" <reg_DM_1> <reg_N> <reg_DM_2> + + @conv { + + reg_N = Register(Rn) + reg_DM_1 = Register(Rdm) + reg_DM_2 = Register(Rdm) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 1 1 0 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 0 0 0 S(1) Rd(4) 0 0 0 0 Rm(4) 1 0 0 1 Rn(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/mvn_A88115.d b/plugins/arm/v7/opdefs/mvn_A88115.d new file mode 100644 index 0000000..2955439 --- /dev/null +++ b/plugins/arm/v7/opdefs/mvn_A88115.d @@ -0,0 +1,72 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title MVN (immediate) + +@desc Bitwise NOT (immediate) writes the bitwise inverse of an immediate value to the destination register. It can optionally update the condition flags based on the value. + +@encoding (T1) { + + @word 1 1 1 1 0 i(1) 0 0 0 1 1 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm8(8) + + @syntax <reg_D> <imm32> + + @conv { + + reg_D = Register(Rd) + setflags = (S == '1') + imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 1 1 1 S(1) 0 0 0 0 Rd(4) imm12(12) + + @syntax <reg_D> <imm32> + + @conv { + + reg_D = Register(Rd) + setflags = (S == '1') + imm32 = ARMExpandImm_C(imm12, 0) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/mvn_A88116.d b/plugins/arm/v7/opdefs/mvn_A88116.d new file mode 100644 index 0000000..1f3f390 --- /dev/null +++ b/plugins/arm/v7/opdefs/mvn_A88116.d @@ -0,0 +1,90 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title MVN (register) + +@desc Bitwise NOT (register) writes the bitwise inverse of a register value to the destination register. It can optionally update the condition flags based on the result. + +@encoding (t1) { + + @half 0 1 0 0 0 0 1 1 1 1 Rm(3) Rd(3) + + @syntax "mvns" <reg_D> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 1 0 0 1 1 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) + + @syntax <reg_D> <reg_M> <?shift> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm3:imm2) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 1 1 S(1) 0 0 0 0 Rd(4) imm5(5) type(2) 0 Rm(4) + + @syntax <reg_D> <reg_M> <?shift> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm5) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/mvn_A88117.d b/plugins/arm/v7/opdefs/mvn_A88117.d new file mode 100644 index 0000000..cc6ef16 --- /dev/null +++ b/plugins/arm/v7/opdefs/mvn_A88117.d @@ -0,0 +1,51 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title MVN (register-shifted register) + +@desc Bitwise NOT (register-shifted register) writes the bitwise inverse of a register-shifted register value to the destination register. It can optionally update the condition flags based on the result. + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 1 1 S(1) 0 0 0 0 Rd(4) Rs(4) 0 type(2) 1 Rm(4) + + @syntax <reg_D> <reg_M> <reg_shift> + + @conv { + + reg_shift = RegisterShift(type, Rs) + reg_D = Register(Rd) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/nop_A88119.d b/plugins/arm/v7/opdefs/nop_A88119.d new file mode 100644 index 0000000..84c495a --- /dev/null +++ b/plugins/arm/v7/opdefs/nop_A88119.d @@ -0,0 +1,53 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title NOP + +@desc No Operation does nothing. This instruction can be used for instruction alignment purposes. See Pre-UAL pseudo-instruction NOP on page AppxH-2472 for details of NOP before the introduction of UAL and the ARMv6K and ARMv6T2 architecture variants. Note The timing effects of including a NOP instruction in a program are not guaranteed. It can increase execution time, leave it unchanged, or even reduce it. Therefore, NOP instructions are not suitable for timing loops. + +@encoding (t1) { + + @half 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 + +} + +@encoding (T2) { + + @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + + @syntax ".W" + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/orn_A88120.d b/plugins/arm/v7/opdefs/orn_A88120.d new file mode 100644 index 0000000..b823b6c --- /dev/null +++ b/plugins/arm/v7/opdefs/orn_A88120.d @@ -0,0 +1,50 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title ORN (immediate) + +@desc Bitwise OR NOT (immediate) performs a bitwise (inclusive) OR of a register value and the complement of an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +@encoding (T1) { + + @word 1 1 1 1 0 i(1) 0 0 0 1 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) + + @syntax <reg_D> <reg_N> <imm32> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + setflags = (S == '1') + imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + + } + +} + diff --git a/plugins/arm/v7/opdefs/orn_A88121.d b/plugins/arm/v7/opdefs/orn_A88121.d new file mode 100644 index 0000000..f1523ec --- /dev/null +++ b/plugins/arm/v7/opdefs/orn_A88121.d @@ -0,0 +1,51 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title ORN (register) + +@desc Bitwise OR NOT (register) performs a bitwise (inclusive) OR of a register value and the complement of an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +@encoding (T1) { + + @word 1 1 1 0 1 0 1 0 0 1 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <?shift> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm3:imm2) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + + } + +} + diff --git a/plugins/arm/v7/opdefs/orr_A88122.d b/plugins/arm/v7/opdefs/orr_A88122.d new file mode 100644 index 0000000..766b5ee --- /dev/null +++ b/plugins/arm/v7/opdefs/orr_A88122.d @@ -0,0 +1,74 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title ORR (immediate) + +@desc Bitwise OR (immediate) performs a bitwise (inclusive) OR of a register value and an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +@encoding (T1) { + + @word 1 1 1 1 0 i(1) 0 0 0 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) + + @syntax <reg_D> <reg_N> <imm32> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + setflags = (S == '1') + imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 1 0 0 S(1) Rn(4) Rd(4) imm12(12) + + @syntax <reg_D> <reg_N> <imm32> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + setflags = (S == '1') + imm32 = ARMExpandImm_C(imm12, 0) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/orr_A88123.d b/plugins/arm/v7/opdefs/orr_A88123.d new file mode 100644 index 0000000..2395c89 --- /dev/null +++ b/plugins/arm/v7/opdefs/orr_A88123.d @@ -0,0 +1,92 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title ORR (register) + +@desc Bitwise OR (register) performs a bitwise (inclusive) OR of a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +@encoding (t1) { + + @half 0 1 0 0 0 0 1 1 0 0 Rm(3) Rdn(3) + + @syntax "orrs" <reg_DN> <reg_M> + + @conv { + + reg_DN = Register(Rdn) + reg_M = Register(Rm) + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 1 0 0 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <?shift> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm3:imm2) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <?shift> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm5) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/orr_A88124.d b/plugins/arm/v7/opdefs/orr_A88124.d new file mode 100644 index 0000000..f4d78b9 --- /dev/null +++ b/plugins/arm/v7/opdefs/orr_A88124.d @@ -0,0 +1,52 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title ORR (register-shifted register) + +@desc Bitwise OR (register-shifted register) performs a bitwise (inclusive) OR of a register value and a register-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <reg_shift> + + @conv { + + reg_shift = RegisterShift(type, Rs) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/pop_A88131.d b/plugins/arm/v7/opdefs/pop_A88131.d new file mode 100644 index 0000000..2dee09a --- /dev/null +++ b/plugins/arm/v7/opdefs/pop_A88131.d @@ -0,0 +1,87 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title POP (Thumb) + +@desc Pop Multiple Registers loads multiple registers from the stack, loading from consecutive memory locations starting at the address in SP, and updates SP to point just above the loaded data. + +@encoding (t1) { + + @half 1 0 1 1 1 1 0 P(1) register_list(8) + + @syntax <registers> + + @conv { + + registers = RegistersList(P:'0000000':register_list) + + } + + @hooks { + + link = handle_armv7_return_from_pop + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 0 0 1 0 1 1 1 1 0 1 P(1) M(1) 0 register_list(13) + + @syntax ".W" <registers> + + @conv { + + registers = RegistersList(P:M:'0':register_list) + + } + + @hooks { + + link = handle_armv7_return_from_pop + + } + +} + +@encoding (T3) { + + @word 1 1 1 1 1 0 0 0 0 1 0 1 1 1 0 1 Rt(4) 1 0 1 1 0 0 0 0 0 1 0 0 + + @syntax ".W" <registers> + + @conv { + + registers = RegistersList(1 << Rt) + + } + + @hooks { + + link = handle_armv7_return_from_pop + + } + +} + diff --git a/plugins/arm/v7/opdefs/pop_A88132.d b/plugins/arm/v7/opdefs/pop_A88132.d new file mode 100644 index 0000000..27bbf3b --- /dev/null +++ b/plugins/arm/v7/opdefs/pop_A88132.d @@ -0,0 +1,79 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title POP (ARM) + +@desc Pop Multiple Registers loads multiple registers from the stack, loading from consecutive memory locations starting at the address in SP, and updates SP to point just above the loaded data. + +@encoding (A1) { + + @word cond(4) 1 0 0 0 1 0 1 1 1 1 0 1 register_list(16) + + @syntax <registers> + + @conv { + + registers = RegistersList(register_list) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + + @hooks { + + link = handle_armv7_return_from_pop + + } + +} + +@encoding (A2) { + + @word cond(4) 0 1 0 0 1 0 0 1 1 1 0 1 Rt(4) 0 0 0 0 0 0 0 0 0 1 0 0 + + @syntax <registers> + + @conv { + + registers = RegistersList(1 << Rt) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + + @hooks { + + link = handle_armv7_return_from_pop + + } + +} + diff --git a/plugins/arm/v7/opdefs/push_A88133.d b/plugins/arm/v7/opdefs/push_A88133.d new file mode 100644 index 0000000..14fc3e9 --- /dev/null +++ b/plugins/arm/v7/opdefs/push_A88133.d @@ -0,0 +1,109 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title PUSH + +@desc Push Multiple Registers stores multiple registers to the stack, storing to consecutive memory locations ending just below the address in SP, and updates SP to point to the start of the stored data. + +@encoding (t1) { + + @half 1 0 1 1 0 1 0 M(1) register_list(8) + + @syntax <registers> + + @conv { + + registers = RegistersList('0':M:'000000':register_list) + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 0 1 0 0 1 0 1 1 0 1 0 M(1) 0 register_list(13) + + @syntax ".W" <registers> + + @conv { + + registers = RegistersList('0':M:'0':register_list) + + } + +} + +@encoding (T3) { + + @word 1 1 1 1 1 0 0 0 0 1 0 0 1 1 0 1 Rt(4) 1 1 0 1 0 0 0 0 0 1 0 0 + + @syntax ".W" <registers> + + @conv { + + registers = Zeros(16) + + } + +} + +@encoding (A1) { + + @word cond(4) 1 0 0 1 0 0 1 0 1 1 0 1 register_list(16) + + @syntax <registers> + + @conv { + + registers = RegistersList(register_list) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + +@encoding (A2) { + + @word cond(4) 0 1 0 1 0 0 1 0 1 1 0 1 Rt(4) 0 0 0 0 0 0 0 0 0 1 0 0 + + @syntax <registers> + + @conv { + + registers = Zeros(16) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/qadd16_A88135.d b/plugins/arm/v7/opdefs/qadd16_A88135.d new file mode 100644 index 0000000..15af29d --- /dev/null +++ b/plugins/arm/v7/opdefs/qadd16_A88135.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title QADD16 + +@desc Saturating Add 16 performs two 16-bit integer additions, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/qadd8_A88136.d b/plugins/arm/v7/opdefs/qadd8_A88136.d new file mode 100644 index 0000000..a71b251 --- /dev/null +++ b/plugins/arm/v7/opdefs/qadd8_A88136.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title QADD8 + +@desc Saturating Add 8 performs four 8-bit integer additions, saturates the results to the 8-bit signed integer range –27 ≤ x ≤ 27 – 1, and writes the results to the destination register. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/qadd_A88134.d b/plugins/arm/v7/opdefs/qadd_A88134.d new file mode 100644 index 0000000..f932983 --- /dev/null +++ b/plugins/arm/v7/opdefs/qadd_A88134.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title QADD + +@desc Saturating Add adds two register values, saturates the result to the 32-bit signed integer range –231 to (231 – 1), and writes the result to the destination register. If saturation occurs, it sets the Q flag in the APSR. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 1 0 0 0 Rm(4) + + @syntax <reg_D> <reg_M> <reg_N> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 0 0 0 Rn(4) Rd(4) 0 0 0 0 0 1 0 1 Rm(4) + + @syntax <reg_D> <reg_M> <reg_N> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/qasx_A88137.d b/plugins/arm/v7/opdefs/qasx_A88137.d new file mode 100644 index 0000000..68251ca --- /dev/null +++ b/plugins/arm/v7/opdefs/qasx_A88137.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title QASX + +@desc Saturating Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one 16-bit integer addition and one 16-bit subtraction, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/qdadd_A88138.d b/plugins/arm/v7/opdefs/qdadd_A88138.d new file mode 100644 index 0000000..c40cdcd --- /dev/null +++ b/plugins/arm/v7/opdefs/qdadd_A88138.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title QDADD + +@desc Saturating Double and Add adds a doubled register value to another register value, and writes the result to the destination register. Both the doubling and the addition have their results saturated to the 32-bit signed integer range –231 ≤ x ≤ 231 – 1. If saturation occurs in either operation, it sets the Q flag in the APSR. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 1 0 0 1 Rm(4) + + @syntax <reg_D> <reg_M> <reg_N> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 1 0 0 Rn(4) Rd(4) 0 0 0 0 0 1 0 1 Rm(4) + + @syntax <reg_D> <reg_M> <reg_N> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/qdsub_A88139.d b/plugins/arm/v7/opdefs/qdsub_A88139.d new file mode 100644 index 0000000..87bd083 --- /dev/null +++ b/plugins/arm/v7/opdefs/qdsub_A88139.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title QDSUB + +@desc Saturating Double and Subtract subtracts a doubled register value from another register value, and writes the result to the destination register. Both the doubling and the subtraction have their results saturated to the 32-bit signed integer range –231 ≤ x ≤ 231 – 1. If saturation occurs in either operation, it sets the Q flag in the APSR. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 1 0 1 1 Rm(4) + + @syntax <reg_D> <reg_M> <reg_N> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 1 1 0 Rn(4) Rd(4) 0 0 0 0 0 1 0 1 Rm(4) + + @syntax <reg_D> <reg_M> <reg_N> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/qsax_A88140.d b/plugins/arm/v7/opdefs/qsax_A88140.d new file mode 100644 index 0000000..df24cf8 --- /dev/null +++ b/plugins/arm/v7/opdefs/qsax_A88140.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title QSAX + +@desc Saturating Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one 16-bit integer subtraction and one 16-bit addition, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/qsub16_A88142.d b/plugins/arm/v7/opdefs/qsub16_A88142.d new file mode 100644 index 0000000..5b2c96b --- /dev/null +++ b/plugins/arm/v7/opdefs/qsub16_A88142.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title QSUB16 + +@desc Saturating Subtract 16 performs two 16-bit integer subtractions, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 0 1 1 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/qsub8_A88143.d b/plugins/arm/v7/opdefs/qsub8_A88143.d new file mode 100644 index 0000000..270a99d --- /dev/null +++ b/plugins/arm/v7/opdefs/qsub8_A88143.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title QSUB8 + +@desc Saturating Subtract 8 performs four 8-bit integer subtractions, saturates the results to the 8-bit signed integer range –27 ≤ x ≤ 27 – 1, and writes the results to the destination register. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 1 1 1 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/qsub_A88141.d b/plugins/arm/v7/opdefs/qsub_A88141.d new file mode 100644 index 0000000..c60ec57 --- /dev/null +++ b/plugins/arm/v7/opdefs/qsub_A88141.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title QSUB + +@desc Saturating Subtract subtracts one register value from another register value, saturates the result to the 32-bit signed integer range –231 ≤ x ≤ 231 – 1, and writes the result to the destination register. If saturation occurs, it sets the Q flag in the APSR. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 1 0 1 0 Rm(4) + + @syntax <reg_D> <reg_M> <reg_N> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 0 1 0 Rn(4) Rd(4) 0 0 0 0 0 1 0 1 Rm(4) + + @syntax <reg_D> <reg_M> <reg_N> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/rbit_A88144.d b/plugins/arm/v7/opdefs/rbit_A88144.d new file mode 100644 index 0000000..7f2bdb6 --- /dev/null +++ b/plugins/arm/v7/opdefs/rbit_A88144.d @@ -0,0 +1,63 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title RBIT + +@desc Reverse Bits reverses the bit order in a 32-bit register. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 1 Rm(4) 1 1 1 1 Rd(4) 1 0 1 0 Rm(4) + + @syntax <reg_D> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 1 1 1 1 1 1 1 Rd(4) 1 1 1 1 0 0 1 1 Rm(4) + + @syntax <reg_D> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/rev16_A88146.d b/plugins/arm/v7/opdefs/rev16_A88146.d new file mode 100644 index 0000000..53b9a82 --- /dev/null +++ b/plugins/arm/v7/opdefs/rev16_A88146.d @@ -0,0 +1,78 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title REV16 + +@desc Byte-Reverse Packed Halfword reverses the byte order in each16-bit halfword of a 32-bit register. + +@encoding (t1) { + + @half 1 0 1 1 1 0 1 0 0 1 Rm(3) Rd(3) + + @syntax <reg_D> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 1 0 1 0 0 1 Rm(4) 1 1 1 1 Rd(4) 1 0 0 1 Rm(4) + + @syntax ".W" <reg_D> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 0 1 1 1 1 1 1 Rd(4) 1 1 1 1 1 0 1 1 Rm(4) + + @syntax <reg_D> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/rev_A88145.d b/plugins/arm/v7/opdefs/rev_A88145.d new file mode 100644 index 0000000..2fe305d --- /dev/null +++ b/plugins/arm/v7/opdefs/rev_A88145.d @@ -0,0 +1,78 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title REV + +@desc Byte-Reverse Word reverses the byte order in a 32-bit register. + +@encoding (t1) { + + @half 1 0 1 1 1 0 1 0 0 0 Rm(3) Rd(3) + + @syntax <reg_D> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 1 0 1 0 0 1 Rm(4) 1 1 1 1 Rd(4) 1 0 0 0 Rm(4) + + @syntax ".W" <reg_D> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 0 1 1 1 1 1 1 Rd(4) 1 1 1 1 0 0 1 1 Rm(4) + + @syntax <reg_D> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/revsh_A88147.d b/plugins/arm/v7/opdefs/revsh_A88147.d new file mode 100644 index 0000000..551582c --- /dev/null +++ b/plugins/arm/v7/opdefs/revsh_A88147.d @@ -0,0 +1,78 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title REVSH + +@desc Byte-Reverse Signed Halfword reverses the byte order in the lower 16-bit halfword of a 32-bit register, and sign-extends the result to 32 bits. + +@encoding (t1) { + + @half 1 0 1 1 1 0 1 0 1 1 Rm(3) Rd(3) + + @syntax <reg_D> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 1 0 1 0 0 1 Rm(4) 1 1 1 1 Rd(4) 1 0 1 1 Rm(4) + + @syntax ".W" <reg_D> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 1 1 1 1 1 1 1 Rd(4) 1 1 1 1 1 0 1 1 Rm(4) + + @syntax <reg_D> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/ror_A88149.d b/plugins/arm/v7/opdefs/ror_A88149.d new file mode 100644 index 0000000..7e061c6 --- /dev/null +++ b/plugins/arm/v7/opdefs/ror_A88149.d @@ -0,0 +1,74 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title ROR (immediate) + +@desc Rotate Right (immediate) provides the value of the contents of a register rotated by a constant value. The bits that are rotated off the right end are inserted into the vacated bit positions on the left. It can optionally update the condition flags based on the result. + +@encoding (T1) { + + @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 1 1 Rm(4) + + @syntax <reg_D> <reg_M> <shift_imm> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + setflags = (S == '1') + shift_imm = DecodeImmShift('11', imm3:imm2) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 1 1 0 Rm(4) + + @syntax <reg_D> <reg_M> <shift_imm> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + setflags = (S == '1') + shift_imm = DecodeImmShift('11', imm5) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/ror_A88150.d b/plugins/arm/v7/opdefs/ror_A88150.d new file mode 100644 index 0000000..c046bf7 --- /dev/null +++ b/plugins/arm/v7/opdefs/ror_A88150.d @@ -0,0 +1,90 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title ROR (register) + +@desc Rotate Right (register) provides the value of the contents of a register rotated by a variable number of bits. The bits that are rotated off the right end are inserted into the vacated bit positions on the left. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. + +@encoding (t1) { + + @half 0 1 0 0 0 0 0 1 1 1 Rm(3) Rdn(3) + + @syntax "rors" <reg_DN> <reg_M> + + @conv { + + reg_DN = Register(Rdn) + reg_M = Register(Rm) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 1 0 0 1 1 S(1) Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) Rm(4) 0 1 1 1 Rn(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/rrx_A88151.d b/plugins/arm/v7/opdefs/rrx_A88151.d new file mode 100644 index 0000000..4debd42 --- /dev/null +++ b/plugins/arm/v7/opdefs/rrx_A88151.d @@ -0,0 +1,72 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title RRX + +@desc Rotate Right with Extend provides the value of the contents of a register shifted right by one place, with the Carry flag shifted into bit[31]. RRX can optionally update the condition flags based on the result. In that case, bit[0] is shifted into the Carry flag. + +@encoding (T1) { + + @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 0 0 0 Rd(4) 0 0 1 1 Rm(4) + + @syntax <reg_D> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) 0 0 0 0 0 1 1 0 Rm(4) + + @syntax <reg_D> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/rsb_A88152.d b/plugins/arm/v7/opdefs/rsb_A88152.d new file mode 100644 index 0000000..ea53373 --- /dev/null +++ b/plugins/arm/v7/opdefs/rsb_A88152.d @@ -0,0 +1,91 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title RSB (immediate) + +@desc Reverse Subtract (immediate) subtracts a register value from an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +@encoding (t1) { + + @half 0 1 0 0 0 0 1 0 0 1 Rn(3) Rd(3) + + @syntax "rsbs" <reg_D> <reg_N> <imm32> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = Zeros(32) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 0 i(1) 0 1 1 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) + + @syntax <reg_D> <reg_N> <imm32> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + setflags = (S == '1') + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 0 0 1 1 S(1) Rn(4) Rd(4) imm12(12) + + @syntax <reg_D> <reg_N> <imm32> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + setflags = (S == '1') + imm32 = ARMExpandImm(imm12) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/rsb_A88153.d b/plugins/arm/v7/opdefs/rsb_A88153.d new file mode 100644 index 0000000..f4a6d61 --- /dev/null +++ b/plugins/arm/v7/opdefs/rsb_A88153.d @@ -0,0 +1,76 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title RSB (register) + +@desc Reverse Subtract (register) subtracts a register value from an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +@encoding (T1) { + + @word 1 1 1 0 1 0 1 1 1 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <?shift> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm3:imm2) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 0 1 1 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <?shift> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm5) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/rsb_A88154.d b/plugins/arm/v7/opdefs/rsb_A88154.d new file mode 100644 index 0000000..9ccf559 --- /dev/null +++ b/plugins/arm/v7/opdefs/rsb_A88154.d @@ -0,0 +1,52 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title RSB (register-shifted register) + +@desc Reverse Subtract (register-shifted register) subtracts a register value from a register-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +@encoding (A1) { + + @word cond(4) 0 0 0 0 0 1 1 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <reg_shift> + + @conv { + + reg_shift = RegisterShift(type, Rs) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/rsc_A88155.d b/plugins/arm/v7/opdefs/rsc_A88155.d new file mode 100644 index 0000000..fc5f8b6 --- /dev/null +++ b/plugins/arm/v7/opdefs/rsc_A88155.d @@ -0,0 +1,51 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title RSC (immediate) + +@desc Reverse Subtract with Carry (immediate) subtracts a register value and the value of NOT (Carry flag) from an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +@encoding (A1) { + + @word cond(4) 0 0 1 0 1 1 1 S(1) Rn(4) Rd(4) imm12(12) + + @syntax <reg_D> <reg_N> <imm32> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + setflags = (S == '1') + imm32 = ARMExpandImm(imm12) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/rsc_A88156.d b/plugins/arm/v7/opdefs/rsc_A88156.d new file mode 100644 index 0000000..70829cd --- /dev/null +++ b/plugins/arm/v7/opdefs/rsc_A88156.d @@ -0,0 +1,52 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title RSC (register) + +@desc Reverse Subtract with Carry (register) subtracts a register value and the value of NOT (Carry flag) from an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +@encoding (A1) { + + @word cond(4) 0 0 0 0 1 1 1 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <?shift> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm5) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/rsc_A88157.d b/plugins/arm/v7/opdefs/rsc_A88157.d new file mode 100644 index 0000000..4fa276d --- /dev/null +++ b/plugins/arm/v7/opdefs/rsc_A88157.d @@ -0,0 +1,52 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title RSC (register-shifted register) + +@desc Reverse Subtract (register-shifted register) subtracts a register value and the value of NOT (Carry flag) from a register-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +@encoding (A1) { + + @word cond(4) 0 0 0 0 1 1 1 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <reg_shift> + + @conv { + + reg_shift = RegisterShift(type, Rs) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/sadd16_A88158.d b/plugins/arm/v7/opdefs/sadd16_A88158.d new file mode 100644 index 0000000..51ad948 --- /dev/null +++ b/plugins/arm/v7/opdefs/sadd16_A88158.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SADD16 + +@desc Signed Add 16 performs two 16-bit signed integer additions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the additions. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 0 1 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/sadd8_A88159.d b/plugins/arm/v7/opdefs/sadd8_A88159.d new file mode 100644 index 0000000..463c968 --- /dev/null +++ b/plugins/arm/v7/opdefs/sadd8_A88159.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SADD8 + +@desc Signed Add 8 performs four 8-bit signed integer additions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the additions. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 0 1 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/sasx_A88160.d b/plugins/arm/v7/opdefs/sasx_A88160.d new file mode 100644 index 0000000..a0529cb --- /dev/null +++ b/plugins/arm/v7/opdefs/sasx_A88160.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SASX + +@desc Signed Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one 16-bit integer addition and one 16-bit subtraction, and writes the results to the destination register. It sets the APSR.GE bits according to the results. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 0 1 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/sbc_A88161.d b/plugins/arm/v7/opdefs/sbc_A88161.d new file mode 100644 index 0000000..4ea776a --- /dev/null +++ b/plugins/arm/v7/opdefs/sbc_A88161.d @@ -0,0 +1,74 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SBC (immediate) + +@desc Subtract with Carry (immediate) subtracts an immediate value and the value of NOT (Carry flag) from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +@encoding (T1) { + + @word 1 1 1 1 0 i(1) 0 1 0 1 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) + + @syntax <reg_D> <reg_N> <imm32> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + setflags = (S == '1') + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 0 1 1 0 S(1) Rn(4) Rd(4) imm12(12) + + @syntax <reg_D> <reg_N> <imm32> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + setflags = (S == '1') + imm32 = ARMExpandImm(imm12) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/sbc_A88162.d b/plugins/arm/v7/opdefs/sbc_A88162.d new file mode 100644 index 0000000..b6e660a --- /dev/null +++ b/plugins/arm/v7/opdefs/sbc_A88162.d @@ -0,0 +1,92 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SBC (register) + +@desc Subtract with Carry (register) subtracts an optionally-shifted register value and the value of NOT (Carry flag) from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +@encoding (t1) { + + @half 0 1 0 0 0 0 0 1 1 0 Rm(3) Rdn(3) + + @syntax "sbcs" <reg_DN> <reg_M> + + @conv { + + reg_DN = Register(Rdn) + reg_M = Register(Rm) + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 1 1 0 1 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <?shift> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm3:imm2) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 1 1 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <?shift> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm5) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/sbc_A88163.d b/plugins/arm/v7/opdefs/sbc_A88163.d new file mode 100644 index 0000000..0500edc --- /dev/null +++ b/plugins/arm/v7/opdefs/sbc_A88163.d @@ -0,0 +1,52 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SBC (register-shifted register) + +@desc Subtract with Carry (register-shifted register) subtracts a register-shifted register value and the value of NOT (Carry flag) from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +@encoding (A1) { + + @word cond(4) 0 0 0 0 1 1 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <reg_shift> + + @conv { + + reg_shift = RegisterShift(type, Rs) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/sbfx_A88164.d b/plugins/arm/v7/opdefs/sbfx_A88164.d new file mode 100644 index 0000000..486db3c --- /dev/null +++ b/plugins/arm/v7/opdefs/sbfx_A88164.d @@ -0,0 +1,67 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SBFX + +@desc Signed Bit Field Extract extracts any number of adjacent bits at any position from a register, sign-extends them to 32 bits, and writes the result to the destination register. + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 0 1 0 0 Rn(4) 0 imm3(3) Rd(4) imm2(2) 0 widthm1(5) + + @syntax <reg_D> <reg_N> <lsbit> <width> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + lsbit = UInt(imm3:imm2) + width = IncWidth(widthm1) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 1 0 1 widthm1(5) Rd(4) lsb(5) 1 0 1 Rn(4) + + @syntax <reg_D> <reg_N> <lsbit> <width> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + lsbit = UInt(lsb) + width = IncWidth(widthm1) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/sdiv_A88165.d b/plugins/arm/v7/opdefs/sdiv_A88165.d new file mode 100644 index 0000000..19ebfa9 --- /dev/null +++ b/plugins/arm/v7/opdefs/sdiv_A88165.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SDIV + +@desc Signed Divide divides a 32-bit signed integer register value by a 32-bit signed integer register value, and writes the result to the destination register. The condition flags are not affected. See ARMv7 implementation requirements and options for the divide instructions on page A4-172 for more information about this instruction. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 1 1 1 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 0 0 0 1 Rd(4) 1 1 1 1 Rm(4) 0 0 0 1 Rn(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/sel_A88166.d b/plugins/arm/v7/opdefs/sel_A88166.d new file mode 100644 index 0000000..cb32ed6 --- /dev/null +++ b/plugins/arm/v7/opdefs/sel_A88166.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SEL + +@desc Select Bytes selects each byte of its result from either its first operand or its second operand, according to the values of the GE flags. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 1 0 0 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 0 0 0 Rn(4) Rd(4) 1 1 1 1 1 0 1 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/setend_A88167.d b/plugins/arm/v7/opdefs/setend_A88167.d new file mode 100644 index 0000000..e549c50 --- /dev/null +++ b/plugins/arm/v7/opdefs/setend_A88167.d @@ -0,0 +1,55 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SETEND + +@desc Set Endianness writes a new value to ENDIANSTATE. + +@encoding (t1) { + + @half 1 0 1 1 0 1 1 0 0 1 0 1 E(1) 0 0 0 + + @syntax <set_bigend> + + @conv { + + set_bigend = EndianState(E == '1') + + } + +} + +@encoding (A1) { + + @word 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 E(1) 0 0 0 0 0 0 0 0 0 + + @syntax <set_bigend> + + @conv { + + set_bigend = EndianState(E == '1') + + } + +} + diff --git a/plugins/arm/v7/opdefs/sev_A88168.d b/plugins/arm/v7/opdefs/sev_A88168.d new file mode 100644 index 0000000..2bd9af4 --- /dev/null +++ b/plugins/arm/v7/opdefs/sev_A88168.d @@ -0,0 +1,53 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SEV + +@desc Send Event is a hint instruction. It causes an event to be signaled to all processors in the multiprocessor system. For more information, see Wait For Event and Send Event on page B1-1199. + +@encoding (t1) { + + @half 1 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 + +} + +@encoding (T2) { + + @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 + + @syntax ".W" + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/shadd16_A88169.d b/plugins/arm/v7/opdefs/shadd16_A88169.d new file mode 100644 index 0000000..22baa05 --- /dev/null +++ b/plugins/arm/v7/opdefs/shadd16_A88169.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SHADD16 + +@desc Signed Halving Add 16 performs two signed 16-bit integer additions, halves the results, and writes the results to the destination register. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/shadd8_A88170.d b/plugins/arm/v7/opdefs/shadd8_A88170.d new file mode 100644 index 0000000..bfc3031 --- /dev/null +++ b/plugins/arm/v7/opdefs/shadd8_A88170.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SHADD8 + +@desc Signed Halving Add 8 performs four signed 8-bit integer additions, halves the results, and writes the results to the destination register. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/shasx_A88171.d b/plugins/arm/v7/opdefs/shasx_A88171.d new file mode 100644 index 0000000..71d241b --- /dev/null +++ b/plugins/arm/v7/opdefs/shasx_A88171.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SHASX + +@desc Signed Halving Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one signed 16-bit integer addition and one signed 16-bit subtraction, halves the results, and writes the results to the destination register. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/shsax_A88172.d b/plugins/arm/v7/opdefs/shsax_A88172.d new file mode 100644 index 0000000..8794738 --- /dev/null +++ b/plugins/arm/v7/opdefs/shsax_A88172.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SHSAX + +@desc Signed Halving Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one signed 16-bit integer subtraction and one signed 16-bit addition, halves the results, and writes the results to the destination register. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/shsub16_A88173.d b/plugins/arm/v7/opdefs/shsub16_A88173.d new file mode 100644 index 0000000..f7099f2 --- /dev/null +++ b/plugins/arm/v7/opdefs/shsub16_A88173.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SHSUB16 + +@desc Signed Halving Subtract 16 performs two signed 16-bit integer subtractions, halves the results, and writes the results to the destination register. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 0 1 1 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/shsub8_A88174.d b/plugins/arm/v7/opdefs/shsub8_A88174.d new file mode 100644 index 0000000..99af65d --- /dev/null +++ b/plugins/arm/v7/opdefs/shsub8_A88174.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SHSUB8 + +@desc Signed Halving Subtract 8 performs four signed 8-bit integer subtractions, halves the results, and writes the results to the destination register. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 1 1 1 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/smlad_A88177.d b/plugins/arm/v7/opdefs/smlad_A88177.d new file mode 100644 index 0000000..3eabaa9 --- /dev/null +++ b/plugins/arm/v7/opdefs/smlad_A88177.d @@ -0,0 +1,76 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SMLAD + +@desc Signed Multiply Accumulate Dual performs two signed 16 × 16-bit multiplications. It adds the products to a 32-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. This instruction sets the Q flag if the accumulate operation overflows. Overflow cannot occur during the multiplications. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 0 0 1 0 Rn(4) Ra(4) Rd(4) 0 0 0 M(1) Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <reg_A> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + m_swap = (M == '1') + + } + + @rules { + + if (m_swap); chk_call ExtendKeyword("x") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 0 0 0 0 Rd(4) Ra(4) Rm(4) 0 0 M(1) 1 Rn(4) + + @syntax <reg_D> <reg_N> <reg_M> <reg_A> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + m_swap = (M == '1') + + } + + @rules { + + if (m_swap); chk_call ExtendKeyword("x") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/smlal_A88178.d b/plugins/arm/v7/opdefs/smlal_A88178.d new file mode 100644 index 0000000..03da53c --- /dev/null +++ b/plugins/arm/v7/opdefs/smlal_A88178.d @@ -0,0 +1,69 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SMLAL + +@desc Signed Multiply Accumulate Long multiplies two signed 32-bit values to produce a 64-bit value, and accumulates this with a 64-bit value. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 1 1 0 0 Rn(4) RdLo(4) RdHi(4) 0 0 0 0 Rm(4) + + @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 1 1 1 S(1) RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4) + + @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/smlald_A88180.d b/plugins/arm/v7/opdefs/smlald_A88180.d new file mode 100644 index 0000000..fa6a473 --- /dev/null +++ b/plugins/arm/v7/opdefs/smlald_A88180.d @@ -0,0 +1,76 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SMLALD + +@desc Signed Multiply Accumulate Long Dual performs two signed 16 × 16-bit multiplications. It adds the products to a 64-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. Overflow is possible during this instruction, but only as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo 264. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 1 1 0 0 Rn(4) RdLo(4) RdHi(4) 1 1 0 M(1) Rm(4) + + @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + m_swap = (M == '1') + + } + + @rules { + + if (m_swap); chk_call ExtendKeyword("x") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 0 1 0 0 RdHi(4) RdLo(4) Rm(4) 0 0 M(1) 1 Rn(4) + + @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + m_swap = (M == '1') + + } + + @rules { + + if (m_swap); chk_call ExtendKeyword("x") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/smlsd_A88182.d b/plugins/arm/v7/opdefs/smlsd_A88182.d new file mode 100644 index 0000000..d458fa8 --- /dev/null +++ b/plugins/arm/v7/opdefs/smlsd_A88182.d @@ -0,0 +1,76 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SMLSD + +@desc Signed Multiply Subtract Dual performs two signed 16 × 16-bit multiplications. It adds the difference of the products to a 32-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. This instruction sets the Q flag if the accumulate operation overflows. Overflow cannot occur during the multiplications or subtraction. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 0 1 0 0 Rn(4) Ra(4) Rd(4) 0 0 0 M(1) Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <reg_A> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + m_swap = (M == '1') + + } + + @rules { + + if (m_swap); chk_call ExtendKeyword("x") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 0 0 0 0 Rd(4) Ra(4) Rm(4) 0 1 M(1) 1 Rn(4) + + @syntax <reg_D> <reg_N> <reg_M> <reg_A> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + m_swap = (M == '1') + + } + + @rules { + + if (m_swap); chk_call ExtendKeyword("x") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/smlsld_A88183.d b/plugins/arm/v7/opdefs/smlsld_A88183.d new file mode 100644 index 0000000..9f64eed --- /dev/null +++ b/plugins/arm/v7/opdefs/smlsld_A88183.d @@ -0,0 +1,76 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SMLSLD + +@desc Signed Multiply Subtract Long Dual performs two signed 16 × 16-bit multiplications. It adds the difference of the products to a 64-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. Overflow is possible during this instruction, but only as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo 264. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 1 1 0 1 Rn(4) RdLo(4) RdHi(4) 1 1 0 M(1) Rm(4) + + @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + m_swap = (M == '1') + + } + + @rules { + + if (m_swap); chk_call ExtendKeyword("x") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 0 1 0 0 RdHi(4) RdLo(4) Rm(4) 0 1 M(1) 1 Rn(4) + + @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + m_swap = (M == '1') + + } + + @rules { + + if (m_swap); chk_call ExtendKeyword("x") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/smmla_A88184.d b/plugins/arm/v7/opdefs/smmla_A88184.d new file mode 100644 index 0000000..a4d29b8 --- /dev/null +++ b/plugins/arm/v7/opdefs/smmla_A88184.d @@ -0,0 +1,76 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SMMLA + +@desc Signed Most Significant Word Multiply Accumulate multiplies two signed 32-bit values, extracts the most significant 32 bits of the result, and adds an accumulate value. Optionally, the instruction can specify that the result is rounded instead of being truncated. In this case, the constant 0x80000000 is added to the product before the high word is extracted. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 0 1 0 1 Rn(4) Ra(4) Rd(4) 0 0 0 R(1) Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <reg_A> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + round = (R == '1') + + } + + @rules { + + if (round); chk_call ExtendKeyword("r") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 0 1 0 1 Rd(4) Ra(4) Rm(4) 0 0 R(1) 1 Rn(4) + + @syntax <reg_D> <reg_N> <reg_M> <reg_A> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + round = (R == '1') + + } + + @rules { + + if (round); chk_call ExtendKeyword("r") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/smmls_A88185.d b/plugins/arm/v7/opdefs/smmls_A88185.d new file mode 100644 index 0000000..d59617b --- /dev/null +++ b/plugins/arm/v7/opdefs/smmls_A88185.d @@ -0,0 +1,76 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SMMLS + +@desc Signed Most Significant Word Multiply Subtract multiplies two signed 32-bit values, subtracts the result from a 32-bit accumulate value that is shifted left by 32 bits, and extracts the most significant 32 bits of the result of that subtraction. Optionally, the instruction can specify that the result of the instruction is rounded instead of being truncated. In this case, the constant 0x80000000 is added to the result of the subtraction before the high word is extracted. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 0 1 1 0 Rn(4) Ra(4) Rd(4) 0 0 0 R(1) Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <reg_A> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + round = (R == '1') + + } + + @rules { + + if (round); chk_call ExtendKeyword("r") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 0 1 0 1 Rd(4) Ra(4) Rm(4) 1 1 R(1) 1 Rn(4) + + @syntax <reg_D> <reg_N> <reg_M> <reg_A> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + round = (R == '1') + + } + + @rules { + + if (round); chk_call ExtendKeyword("r") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/smmul_A88186.d b/plugins/arm/v7/opdefs/smmul_A88186.d new file mode 100644 index 0000000..e02ca52 --- /dev/null +++ b/plugins/arm/v7/opdefs/smmul_A88186.d @@ -0,0 +1,74 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SMMUL + +@desc Signed Most Significant Word Multiply multiplies two signed 32-bit values, extracts the most significant 32 bits of the result, and writes those bits to the destination register. Optionally, the instruction can specify that the result is rounded instead of being truncated. In this case, the constant 0x80000000 is added to the product before the high word is extracted. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 0 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 R(1) Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + round = (R == '1') + + } + + @rules { + + if (round); chk_call ExtendKeyword("r") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 0 1 0 1 Rd(4) 1 1 1 1 Rm(4) 0 0 R(1) 1 Rn(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + round = (R == '1') + + } + + @rules { + + if (round); chk_call ExtendKeyword("r") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/smuad_A88187.d b/plugins/arm/v7/opdefs/smuad_A88187.d new file mode 100644 index 0000000..324e257 --- /dev/null +++ b/plugins/arm/v7/opdefs/smuad_A88187.d @@ -0,0 +1,74 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SMUAD + +@desc Signed Dual Multiply Add performs two signed 16 × 16-bit multiplications. It adds the products together, and writes the result to the destination register. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. This instruction sets the Q flag if the addition overflows. The multiplications cannot overflow. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 0 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 M(1) Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + m_swap = (M == '1') + + } + + @rules { + + if (m_swap); chk_call ExtendKeyword("x") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 0 0 0 0 Rd(4) 1 1 1 1 Rm(4) 0 0 M(1) 1 Rn(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + m_swap = (M == '1') + + } + + @rules { + + if (m_swap); chk_call ExtendKeyword("x") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/smull_A88189.d b/plugins/arm/v7/opdefs/smull_A88189.d new file mode 100644 index 0000000..5ab1c54 --- /dev/null +++ b/plugins/arm/v7/opdefs/smull_A88189.d @@ -0,0 +1,69 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SMULL + +@desc Signed Multiply Long multiplies two 32-bit signed values to produce a 64-bit result. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 1 0 0 0 Rn(4) RdLo(4) RdHi(4) 0 0 0 0 Rm(4) + + @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 1 1 0 S(1) RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4) + + @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/str_A88203.d b/plugins/arm/v7/opdefs/str_A88203.d new file mode 100644 index 0000000..e3feaf7 --- /dev/null +++ b/plugins/arm/v7/opdefs/str_A88203.d @@ -0,0 +1,98 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STR (immediate, Thumb) + +@desc Store Register (immediate) calculates an address from a base register value and an immediate offset, and stores a word from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (t1) { + + @half 0 1 1 0 0 imm5(5) Rn(3) Rt(3) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm5:'00', 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + + } + +} + +@encoding (t2) { + + @half 1 0 0 1 0 Rt(3) imm8(8) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + imm32 = ZeroExtend(imm8:'00', 32) + SP = Register(13) + mem_access = MakeMemoryAccess(SP, imm32, NULL, true, true, false) + + } + +} + +@encoding (T3) { + + @word 1 1 1 1 1 0 0 0 1 1 0 0 Rn(4) Rt(4) imm12(12) + + @syntax ".W" <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + + } + +} + +@encoding (T4) { + + @word 1 1 1 1 1 0 0 0 0 1 0 0 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + index = (P == '1') + add = (U == '1') + wback = (W == '1') + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + + } + +} + diff --git a/plugins/arm/v7/opdefs/str_A88204.d b/plugins/arm/v7/opdefs/str_A88204.d new file mode 100644 index 0000000..d780ae3 --- /dev/null +++ b/plugins/arm/v7/opdefs/str_A88204.d @@ -0,0 +1,53 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STR (immediate, ARM) + +@desc Store Register (immediate) calculates an address from a base register value and an immediate offset, and stores a word from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (A1) { + + @word cond(4) 0 1 0 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) imm12(12) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + index = (P == '1') + add = (U == '1') + wback = (P == '0') || (W == '1') + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/str_A88205.d b/plugins/arm/v7/opdefs/str_A88205.d new file mode 100644 index 0000000..55f154c --- /dev/null +++ b/plugins/arm/v7/opdefs/str_A88205.d @@ -0,0 +1,89 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STR (register) + +@desc Store Register (register) calculates an address from a base register value and an offset register value, stores a word from a register to memory. The offset register value can optionally be shifted. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (t1) { + + @half 0 1 0 1 0 0 0 Rm(3) Rn(3) Rt(3) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, true, false) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 0 0 1 0 0 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) + + @syntax ".W" <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(0, imm2) + mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, true, false) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + index = (P == '1') + add = (U == '1') + wback = (P == '0') || (W == '1') + shift = DecodeImmShift(type, imm5) + mem_access = MakeMemoryAccess(reg_N, reg_M, shift, index, add, wback) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/strb_A88206.d b/plugins/arm/v7/opdefs/strb_A88206.d new file mode 100644 index 0000000..2caf94c --- /dev/null +++ b/plugins/arm/v7/opdefs/strb_A88206.d @@ -0,0 +1,81 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STRB (immediate, Thumb) + +@desc Store Register Byte (immediate) calculates an address from a base register value and an immediate offset, and stores a byte from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (t1) { + + @half 0 1 1 1 0 imm5(5) Rn(3) Rt(3) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm5, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 0 1 0 0 0 Rn(4) Rt(4) imm12(12) + + @syntax ".W" <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + + } + +} + +@encoding (T3) { + + @word 1 1 1 1 1 0 0 0 0 0 0 0 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + index = (P == '1') + add = (U == '1') + wback = (W == '1') + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + + } + +} + diff --git a/plugins/arm/v7/opdefs/strb_A88207.d b/plugins/arm/v7/opdefs/strb_A88207.d new file mode 100644 index 0000000..4e893fb --- /dev/null +++ b/plugins/arm/v7/opdefs/strb_A88207.d @@ -0,0 +1,53 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STRB (immediate, ARM) + +@desc Store Register Byte (immediate) calculates an address from a base register value and an immediate offset, and stores a byte from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (A1) { + + @word cond(4) 0 1 0 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) imm12(12) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + index = (P == '1') + add = (U == '1') + wback = (P == '0') || (W == '1') + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/strb_A88208.d b/plugins/arm/v7/opdefs/strb_A88208.d new file mode 100644 index 0000000..36f6134 --- /dev/null +++ b/plugins/arm/v7/opdefs/strb_A88208.d @@ -0,0 +1,89 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STRB (register) + +@desc Store Register Byte (register) calculates an address from a base register value and an offset register value, and stores a byte from a register to memory. The offset register value can optionally be shifted. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (t1) { + + @half 0 1 0 1 0 1 0 Rm(3) Rn(3) Rt(3) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, true, false) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 0 0 0 0 0 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) + + @syntax ".W" <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(0, imm2) + mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, true, false) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + index = (P == '1') + add = (U == '1') + wback = (P == '0') || (W == '1') + shift = DecodeImmShift(type, imm5) + mem_access = MakeMemoryAccess(reg_N, reg_M, shift, index, add, wback) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/strbt_A88209.d b/plugins/arm/v7/opdefs/strbt_A88209.d new file mode 100644 index 0000000..2bcb260 --- /dev/null +++ b/plugins/arm/v7/opdefs/strbt_A88209.d @@ -0,0 +1,93 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STRBT + +@desc Store Register Byte Unprivileged stores a byte from a register to memory. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. STRBT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 0 0 0 0 0 Rn(4) Rt(4) 1 1 1 0 imm8(8) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 0 0 U(1) 1 1 0 Rn(4) Rt(4) imm12(12) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + add = (U == '1') + imm32 = ZeroExtend(imm12, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + +@encoding (A2) { + + @word cond(4) 0 1 1 0 U(1) 1 1 0 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + add = (U == '1') + shift = DecodeImmShift(type, imm5) + mem_access = MakeMemoryAccess(reg_N, reg_M, shift, false, add, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/strd_A88210.d b/plugins/arm/v7/opdefs/strd_A88210.d new file mode 100644 index 0000000..437bcb3 --- /dev/null +++ b/plugins/arm/v7/opdefs/strd_A88210.d @@ -0,0 +1,75 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STRD (immediate) + +@desc Store Register Dual (immediate) calculates an address from a base register value and an immediate offset, and stores two words from two registers to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) Rt2(4) imm8(8) + + @syntax <reg_T> <reg_T2> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + index = (P == '1') + add = (U == '1') + wback = (W == '1') + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) imm4H(4) 1 1 1 1 imm4L(4) + + @syntax <reg_T> <reg_T2> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(reg_T) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + index = (P == '1') + add = (U == '1') + wback = (P == '0') || (W == '1') + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/strd_A88211.d b/plugins/arm/v7/opdefs/strd_A88211.d new file mode 100644 index 0000000..b30d4a5 --- /dev/null +++ b/plugins/arm/v7/opdefs/strd_A88211.d @@ -0,0 +1,54 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STRD (register) + +@desc Store Register Dual (register) calculates an address from a base register value and a register offset, and stores two words from two registers to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (A1) { + + @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) 0 0 0 0 1 1 1 1 Rm(4) + + @syntax <reg_T> <reg_T2> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(reg_T) + reg_N = Register(Rn) + reg_M = Register(Rm) + index = (P == '1') + add = (U == '1') + wback = (P == '0') || (W == '1') + mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, index, add, wback) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/strex_A88212.d b/plugins/arm/v7/opdefs/strex_A88212.d new file mode 100644 index 0000000..65a7dfe --- /dev/null +++ b/plugins/arm/v7/opdefs/strex_A88212.d @@ -0,0 +1,68 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STREX + +@desc Store Register Exclusive calculates an address from a base register value and an immediate offset, and stores a word from a register to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 0 0 1 0 0 Rn(4) Rt(4) Rd(4) imm8(8) + + @syntax <reg_D> <reg_T> <mem_access> + + @conv { + + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, false, false) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 0 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rt(4) + + @syntax <reg_D> <reg_T> <mem_access> + + @conv { + + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_N = Register(Rn) + mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/strexb_A88213.d b/plugins/arm/v7/opdefs/strexb_A88213.d new file mode 100644 index 0000000..0197d6c --- /dev/null +++ b/plugins/arm/v7/opdefs/strexb_A88213.d @@ -0,0 +1,67 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STREXB + +@desc Store Register Exclusive Byte derives an address from a base register value, and stores a byte from a register to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 0 1 1 0 0 Rn(4) Rt(4) 1 1 1 1 0 1 0 0 Rd(4) + + @syntax <reg_D> <reg_T> <mem_access> + + @conv { + + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_N = Register(Rn) + mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 1 0 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rt(4) + + @syntax <reg_D> <reg_T> <mem_access> + + @conv { + + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_N = Register(Rn) + mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/strexd_A88214.d b/plugins/arm/v7/opdefs/strexd_A88214.d new file mode 100644 index 0000000..2867cea --- /dev/null +++ b/plugins/arm/v7/opdefs/strexd_A88214.d @@ -0,0 +1,69 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STREXD + +@desc Store Register Exclusive Doubleword derives an address from a base register value, and stores a 64-bit doubleword from two registers to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 0 1 1 0 0 Rn(4) Rt(4) Rt2(4) 0 1 1 1 Rd(4) + + @syntax <reg_D> <reg_T> <reg_T2> <mem_access> + + @conv { + + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 1 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rt(4) + + @syntax <reg_D> <reg_T> <reg_T2> <mem_access> + + @conv { + + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_T2 = NextRegister(reg_T) + reg_N = Register(Rn) + mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/strexh_A88215.d b/plugins/arm/v7/opdefs/strexh_A88215.d new file mode 100644 index 0000000..4ca0b6f --- /dev/null +++ b/plugins/arm/v7/opdefs/strexh_A88215.d @@ -0,0 +1,67 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STREXH + +@desc Store Register Exclusive Halfword derives an address from a base register value, and stores a halfword from a register to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 0 1 1 0 0 Rn(4) Rt(4) 1 1 1 1 0 1 0 1 Rd(4) + + @syntax <reg_D> <reg_T> <mem_access> + + @conv { + + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_N = Register(Rn) + mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 1 1 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rt(4) + + @syntax <reg_D> <reg_T> <mem_access> + + @conv { + + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_N = Register(Rn) + mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/strh_A88216.d b/plugins/arm/v7/opdefs/strh_A88216.d new file mode 100644 index 0000000..624b483 --- /dev/null +++ b/plugins/arm/v7/opdefs/strh_A88216.d @@ -0,0 +1,81 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STRH (immediate, Thumb) + +@desc Store Register Halfword (immediate) calculates an address from a base register value and an immediate offset, and stores a halfword from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (t1) { + + @half 1 0 0 0 0 imm5(5) Rn(3) Rt(3) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm5:'0', 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 0 1 0 1 0 Rn(4) Rt(4) imm12(12) + + @syntax ".W" <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + + } + +} + +@encoding (T3) { + + @word 1 1 1 1 1 0 0 0 0 0 1 0 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + index = (P == '1') + add = (U == '1') + wback = (W == '1') + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + + } + +} + diff --git a/plugins/arm/v7/opdefs/strh_A88217.d b/plugins/arm/v7/opdefs/strh_A88217.d new file mode 100644 index 0000000..3b5f97c --- /dev/null +++ b/plugins/arm/v7/opdefs/strh_A88217.d @@ -0,0 +1,53 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STRH (immediate, ARM) + +@desc Store Register Halfword (immediate) calculates an address from a base register value and an immediate offset, and stores a halfword from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (A1) { + + @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) imm4H(4) 1 0 1 1 imm4L(4) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + index = (P == '1') + add = (U == '1') + wback = (P == '0') || (W == '1') + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/strh_A88218.d b/plugins/arm/v7/opdefs/strh_A88218.d new file mode 100644 index 0000000..1e9dc1f --- /dev/null +++ b/plugins/arm/v7/opdefs/strh_A88218.d @@ -0,0 +1,88 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STRH (register) + +@desc Store Register Halfword (register) calculates an address from a base register value and an offset register value, and stores a halfword from a register to memory. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (t1) { + + @half 0 1 0 1 0 0 1 Rm(3) Rn(3) Rt(3) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, true, false) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 0 0 0 1 0 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) + + @syntax ".W" <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(0, imm2) + mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, true, false) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) 0 0 0 0 1 0 1 1 Rm(4) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + index = (P == '1') + add = (U == '1') + wback = (P == '0') || (W == '1') + mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, index, add, wback) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/strht_A88219.d b/plugins/arm/v7/opdefs/strht_A88219.d new file mode 100644 index 0000000..3811572 --- /dev/null +++ b/plugins/arm/v7/opdefs/strht_A88219.d @@ -0,0 +1,92 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STRHT + +@desc Store Register Halfword Unprivileged stores a halfword from a register to memory. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. STRHT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value. + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 0 0 0 1 0 Rn(4) Rt(4) 1 1 1 0 imm8(8) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 U(1) 1 1 0 Rn(4) Rt(4) imm4H(4) 1 0 1 1 imm4L(4) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + add = (U == '1') + imm32 = ZeroExtend(imm4H:imm4L, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + +@encoding (A2) { + + @word cond(4) 0 0 0 0 U(1) 0 1 0 Rn(4) Rt(4) 0 0 0 0 1 0 1 1 Rm(4) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + add = (U == '1') + mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, false, add, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/strt_A88220.d b/plugins/arm/v7/opdefs/strt_A88220.d new file mode 100644 index 0000000..794a0fa --- /dev/null +++ b/plugins/arm/v7/opdefs/strt_A88220.d @@ -0,0 +1,93 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STRT + +@desc Store Register Unprivileged stores a word from a register to memory. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. STRT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 0 0 1 0 0 Rn(4) Rt(4) 1 1 1 0 imm8(8) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 0 0 U(1) 0 1 0 Rn(4) Rt(4) imm12(12) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + add = (U == '1') + imm32 = ZeroExtend(imm12, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + +@encoding (A2) { + + @word cond(4) 0 1 1 0 U(1) 0 1 0 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + add = (U == '1') + shift = DecodeImmShift(type, imm5) + mem_access = MakeMemoryAccess(reg_N, reg_M, shift, false, add, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/sub_A88221.d b/plugins/arm/v7/opdefs/sub_A88221.d new file mode 100644 index 0000000..41ce6b3 --- /dev/null +++ b/plugins/arm/v7/opdefs/sub_A88221.d @@ -0,0 +1,98 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SUB (immediate, Thumb) + +@desc This instruction subtracts an immediate value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +@encoding (t1) { + + @half 0 0 0 1 1 1 1 imm3(3) Rn(3) Rd(3) + + @syntax "subs" <reg_D> <reg_N> <imm32> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm3, 32) + + } + +} + +@encoding (t2) { + + @half 0 0 1 1 1 Rdn(3) imm8(8) + + @syntax "subs" <reg_DN> <imm32> + + @conv { + + reg_DN = Register(Rdn) + imm32 = ZeroExtend(imm8, 32) + + } + +} + +@encoding (T3) { + + @word 1 1 1 1 0 i(1) 0 1 1 0 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) + + @syntax <reg_D> <reg_N> <imm32> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + setflags = (S == '1') + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") + + } + +} + +@encoding (T4) { + + @word 1 1 1 1 0 i(1) 1 0 1 0 1 0 Rn(4) 0 imm3(3) Rd(4) imm8(8) + + @syntax "subw" <reg_D> <reg_N> <imm32> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ZeroExtend(i:imm3:imm8, 32) + + } + +} + diff --git a/plugins/arm/v7/opdefs/sub_A88222.d b/plugins/arm/v7/opdefs/sub_A88222.d new file mode 100644 index 0000000..ef326b8 --- /dev/null +++ b/plugins/arm/v7/opdefs/sub_A88222.d @@ -0,0 +1,51 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SUB (immediate, ARM) + +@desc This instruction subtracts an immediate value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +@encoding (A1) { + + @word cond(4) 0 0 1 0 0 1 0 S(1) Rn(4) Rd(4) imm12(12) + + @syntax <reg_D> <reg_N> <imm32> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + setflags = (S == '1') + imm32 = ARMExpandImm(imm12) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/sub_A88223.d b/plugins/arm/v7/opdefs/sub_A88223.d new file mode 100644 index 0000000..a629250 --- /dev/null +++ b/plugins/arm/v7/opdefs/sub_A88223.d @@ -0,0 +1,93 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SUB (register) + +@desc This instruction subtracts an optionally-shifted register value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +@encoding (t1) { + + @half 0 0 0 1 1 0 1 Rm(3) Rn(3) Rd(3) + + @syntax "subs" <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 1 1 1 0 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <?shift> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm3:imm2) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 0 1 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <?shift> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm5) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/sub_A88224.d b/plugins/arm/v7/opdefs/sub_A88224.d new file mode 100644 index 0000000..5ef4e4d --- /dev/null +++ b/plugins/arm/v7/opdefs/sub_A88224.d @@ -0,0 +1,52 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SUB (register-shifted register) + +@desc This instruction subtracts a register-shifted register value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +@encoding (A1) { + + @word cond(4) 0 0 0 0 0 1 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <reg_shift> + + @conv { + + reg_shift = RegisterShift(type, Rs) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/sub_A88225.d b/plugins/arm/v7/opdefs/sub_A88225.d new file mode 100644 index 0000000..dc54c6b --- /dev/null +++ b/plugins/arm/v7/opdefs/sub_A88225.d @@ -0,0 +1,107 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SUB (SP minus immediate) + +@desc This instruction subtracts an immediate value from the SP value, and writes the result to the destination register. + +@encoding (t1) { + + @half 1 0 1 1 0 0 0 0 1 imm7(7) + + @syntax <SP_0> <SP_1> <imm32> + + @conv { + + imm32 = ZeroExtend(imm7:'00', 32) + SP_0 = Register(13) + SP_1 = Register(13) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 0 i(1) 0 1 1 0 1 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm8(8) + + @syntax <reg_D> <SP> <imm32> + + @conv { + + reg_D = Register(Rd) + setflags = (S == '1') + imm32 = ThumbExpandImm(i:imm3:imm8) + SP = Register(13) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") + + } + +} + +@encoding (T3) { + + @word 1 1 1 1 0 i(1) 1 0 1 0 1 0 1 1 0 1 0 imm3(3) Rd(4) imm8(8) + + @syntax "subw" <reg_D> <SP> <imm32> + + @conv { + + reg_D = Register(Rd) + imm32 = ZeroExtend(i:imm3:imm8, 32) + SP = Register(13) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 0 0 1 0 S(1) 1 1 0 1 Rd(4) imm12(12) + + @syntax <reg_D> <SP> <imm32> + + @conv { + + reg_D = Register(Rd) + setflags = (S == '1') + imm32 = ARMExpandImm(imm12) + SP = Register(13) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/sub_A88226.d b/plugins/arm/v7/opdefs/sub_A88226.d new file mode 100644 index 0000000..02ecada --- /dev/null +++ b/plugins/arm/v7/opdefs/sub_A88226.d @@ -0,0 +1,76 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SUB (SP minus register) + +@desc This instruction subtracts an optionally-shifted register value from the SP value, and writes the result to the destination register. + +@encoding (T1) { + + @word 1 1 1 0 1 0 1 1 1 0 1 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) + + @syntax <reg_D> <SP> <reg_M> <?shift> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm3:imm2) + SP = Register(13) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 0 1 0 S(1) 1 1 0 1 Rd(4) imm5(5) type(2) 0 Rm(4) + + @syntax <reg_D> <SP> <reg_M> <?shift> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm5) + SP = Register(13) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/subs_B9320.d b/plugins/arm/v7/opdefs/subs_B9320.d new file mode 100644 index 0000000..335e614 --- /dev/null +++ b/plugins/arm/v7/opdefs/subs_B9320.d @@ -0,0 +1,44 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2014 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SUBS PC, LR and related instructions (ARM) + +@encoding(A1) { + + @word cond(4) 0 0 1 opcode(4) 1 Rn(4) 1 1 1 1 imm12(12) + + @syntax {c} <Rn> <#const> + + @conv { + + c = Condition(cond) + Rn = Register(Rn) + const = ExpandImmC32(imm12) + + } + + @rules { + + } + +} diff --git a/plugins/arm/v7/opdefs/svc_A88228.d b/plugins/arm/v7/opdefs/svc_A88228.d new file mode 100644 index 0000000..be48545 --- /dev/null +++ b/plugins/arm/v7/opdefs/svc_A88228.d @@ -0,0 +1,61 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SVC (previously SWI) + +@desc Supervisor Call, previously called Software Interrupt, causes a Supervisor Call exception. For more information, see Supervisor Call (SVC) exception on page B1-1209. Software can use this instruction as a call to an operating system to provide a service. In the following cases, the Supervisor Call exception generated by the SVC instruction is taken to Hyp mode: • If the SVC is executed in Hyp mode. • If HCR.TGE is set to 1, and the SVC is executed in Non-secure User mode. For more information, see Supervisor Call exception, when HCR.TGE is set to 1 on page B1-1191 In these cases, the HSR identifies that the exception entry was caused by a Supervisor Call exception, EC value 0x11, see Use of the HSR on page B3-1424. The immediate field in the HSR: • if the SVC is unconditional: — for the Thumb instruction, is the zero-extended value of the imm8 field — for the ARM instruction, is the least-significant 16 bits the imm24 field • if the SVC is conditional, is UNKNOWN. + +@encoding (t1) { + + @half 1 1 0 1 1 1 1 1 imm8(8) + + @syntax <imm32> + + @conv { + + imm32 = ZeroExtend(imm8, 32) + + } + +} + +@encoding (A1) { + + @word cond(4) 1 1 1 1 imm24(24) + + @syntax <imm32> + + @conv { + + imm32 = ZeroExtend(imm24, 32) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/swp_A88229.d b/plugins/arm/v7/opdefs/swp_A88229.d new file mode 100644 index 0000000..2e39015 --- /dev/null +++ b/plugins/arm/v7/opdefs/swp_A88229.d @@ -0,0 +1,52 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SWP, SWPB + +@desc SWP (Swap) swaps a word between registers and memory. SWP loads a word from the memory address given by the value of register <Rn>. The value of register <Rt2> is then stored to the memory address given by the value of <Rn>, and the original loaded value is written to register <Rt>. If the same register is specified for <Rt> and <Rt2>, this instruction swaps the value of the register and the value at the memory address. SWPB (Swap Byte) swaps a byte between registers and memory. SWPB loads a byte from the memory address given by the value of register <Rn>. The value of the least significant byte of register <Rt2> is stored to the memory address given by <Rn>, the original loaded value is zero-extended to a 32-bit word, and the word is written to register <Rt>. If the same register is specified for <Rt> and <Rt2>, this instruction swaps the value of the least significant byte of the register and the byte value at the memory address, and clears the most significant three bytes of the register. For both instructions, the memory system ensures that no other memory access can occur to the memory location between the load access and the store access. Note • The SWP and SWPB instructions rely on the properties of the system beyond the processor to ensure that no stores from other observers can occur between the load access and the store access, and this might not be implemented for all regions of memory on some system implementations. In all cases, SWP and SWPB do ensure that no stores from the processor that executed the SWP or SWPB instruction can occur between the load access and the store access of the SWP or SWPB. • ARM deprecates the use of SWP and SWPB, and strongly recommends that new software uses: LDREX/STREX in preference to SWP — LDREXB/STREXB in preference to SWPB. — • If the translation table entries that relate to a memory location accessed by the SWP or SWPB instruction change, or are seen to change by the executing processor as a result of TLB eviction, this might mean that the translation table attributes, permissions or addresses for the load are different to those for the store. In this case, the architecture makes no guarantee that no memory access occur to these memory locations between the load and store. The Virtualization Extensions make the SWP and SWPB instructions OPTIONAL and deprecated: • If an implementation does not include the SWP and SWPB instructions, the ID_ISAR0.Swap_instrs and ID_ISAR4.SWP_frac fields are zero, see About the Instruction Set Attribute registers on page B7-1950. • In an implementation that includes SWP and SWPB, both instructions are UNDEFINED in Hyp mode. + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 B(1) 0 0 Rn(4) Rt(4) 0 0 0 0 1 0 0 1 Rt2(4) + + @syntax <reg_T> <reg_T2> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + size = (B != 4) + mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + + } + + @rules { + + if (size); chk_call ExtendKeyword("b") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/teq_A88237.d b/plugins/arm/v7/opdefs/teq_A88237.d new file mode 100644 index 0000000..89073f6 --- /dev/null +++ b/plugins/arm/v7/opdefs/teq_A88237.d @@ -0,0 +1,63 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title TEQ (immediate) + +@desc Test Equivalence (immediate) performs a bitwise exclusive OR operation on a register value and an immediate value. It updates the condition flags based on the result, and discards the result. + +@encoding (T1) { + + @word 1 1 1 1 0 i(1) 0 0 1 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm8(8) + + @syntax <reg_N> <imm32> + + @conv { + + reg_N = Register(Rn) + imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 0 0 1 1 Rn(4) 0 0 0 0 imm12(12) + + @syntax <reg_N> <imm32> + + @conv { + + reg_N = Register(Rn) + imm32 = ARMExpandImm_C(imm12, 0) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/teq_A88238.d b/plugins/arm/v7/opdefs/teq_A88238.d new file mode 100644 index 0000000..8187d81 --- /dev/null +++ b/plugins/arm/v7/opdefs/teq_A88238.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title TEQ (register) + +@desc Test Equivalence (register) performs a bitwise exclusive OR operation on a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result. + +@encoding (T1) { + + @word 1 1 1 0 1 0 1 0 1 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm2(2) type(2) Rm(4) + + @syntax <reg_N> <reg_M> <?shift> + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 0 1 1 Rn(4) 0 0 0 0 imm5(5) type(2) 0 Rm(4) + + @syntax <reg_N> <reg_M> <?shift> + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/teq_A88239.d b/plugins/arm/v7/opdefs/teq_A88239.d new file mode 100644 index 0000000..986a7f0 --- /dev/null +++ b/plugins/arm/v7/opdefs/teq_A88239.d @@ -0,0 +1,49 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title TEQ (register-shifted register) + +@desc Test Equivalence (register-shifted register) performs a bitwise exclusive OR operation on a register value and a register-shifted register value. It updates the condition flags based on the result, and discards the result. + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 0 1 1 Rn(4) 0 0 0 0 Rs(4) 0 type(2) 1 Rm(4) + + @syntax <reg_N> <reg_M> <reg_shift> + + @conv { + + reg_shift = RegisterShift(type, Rs) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/tst_A88240.d b/plugins/arm/v7/opdefs/tst_A88240.d new file mode 100644 index 0000000..0ff5121 --- /dev/null +++ b/plugins/arm/v7/opdefs/tst_A88240.d @@ -0,0 +1,63 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title TST (immediate) + +@desc Test (immediate) performs a bitwise AND operation on a register value and an immediate value. It updates the condition flags based on the result, and discards the result. + +@encoding (T1) { + + @word 1 1 1 1 0 i(1) 0 0 0 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm8(8) + + @syntax <reg_N> <imm32> + + @conv { + + reg_N = Register(Rn) + imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 0 0 0 1 Rn(4) 0 0 0 0 imm12(12) + + @syntax <reg_N> <imm32> + + @conv { + + reg_N = Register(Rn) + imm32 = ARMExpandImm_C(imm12, 0) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/tst_A88241.d b/plugins/arm/v7/opdefs/tst_A88241.d new file mode 100644 index 0000000..8777d06 --- /dev/null +++ b/plugins/arm/v7/opdefs/tst_A88241.d @@ -0,0 +1,80 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title TST (register) + +@desc Test (register) performs a bitwise AND operation on a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result. + +@encoding (t1) { + + @half 0 1 0 0 0 0 1 0 0 0 Rm(3) Rn(3) + + @syntax <reg_N> <reg_M> + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 1 0 0 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm2(2) type(2) Rm(4) + + @syntax ".W" <reg_N> <reg_M> <?shift> + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 0 0 1 Rn(4) 0 0 0 0 imm5(5) type(2) 0 Rm(4) + + @syntax <reg_N> <reg_M> <?shift> + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/tst_A88242.d b/plugins/arm/v7/opdefs/tst_A88242.d new file mode 100644 index 0000000..d3fdd9c --- /dev/null +++ b/plugins/arm/v7/opdefs/tst_A88242.d @@ -0,0 +1,49 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title TST (register-shifted register) + +@desc Test (register-shifted register) performs a bitwise AND operation on a register value and a register-shifted register value. It updates the condition flags based on the result, and discards the result. + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 0 0 1 Rn(4) 0 0 0 0 Rs(4) 0 type(2) 1 Rm(4) + + @syntax <reg_N> <reg_M> <reg_shift> + + @conv { + + reg_shift = RegisterShift(type, Rs) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/uadd16_A88243.d b/plugins/arm/v7/opdefs/uadd16_A88243.d new file mode 100644 index 0000000..fcaadee --- /dev/null +++ b/plugins/arm/v7/opdefs/uadd16_A88243.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title UADD16 + +@desc Unsigned Add 16 performs two 16-bit unsigned integer additions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the additions. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/uadd8_A88244.d b/plugins/arm/v7/opdefs/uadd8_A88244.d new file mode 100644 index 0000000..451ca79 --- /dev/null +++ b/plugins/arm/v7/opdefs/uadd8_A88244.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title UADD8 + +@desc Unsigned Add 8 performs four unsigned 8-bit integer additions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the additions. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/uasx_A88245.d b/plugins/arm/v7/opdefs/uasx_A88245.d new file mode 100644 index 0000000..f968527 --- /dev/null +++ b/plugins/arm/v7/opdefs/uasx_A88245.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title UASX + +@desc Unsigned Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, and writes the results to the destination register. It sets the APSR.GE bits according to the results. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/ubfx_A88246.d b/plugins/arm/v7/opdefs/ubfx_A88246.d new file mode 100644 index 0000000..1f9488e --- /dev/null +++ b/plugins/arm/v7/opdefs/ubfx_A88246.d @@ -0,0 +1,67 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title UBFX + +@desc Unsigned Bit Field Extract extracts any number of adjacent bits at any position from a register, zero-extends them to 32 bits, and writes the result to the destination register. + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 1 1 0 0 Rn(4) 0 imm3(3) Rd(4) imm2(2) 0 widthm1(5) + + @syntax <reg_D> <reg_N> <lsbit> <width> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + lsbit = UInt(imm3:imm2) + width = IncWidth(widthm1) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 1 1 1 widthm1(5) Rd(4) lsb(5) 1 0 1 Rn(4) + + @syntax <reg_D> <reg_N> <lsbit> <width> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + lsbit = UInt(lsb) + width = IncWidth(widthm1) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/udf_A88247.d b/plugins/arm/v7/opdefs/udf_A88247.d new file mode 100644 index 0000000..38f818c --- /dev/null +++ b/plugins/arm/v7/opdefs/udf_A88247.d @@ -0,0 +1,69 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title UDF + +@desc Permanently Undefined generates an Undefined Instruction exception. The encodings for UDF used in this section are defined as permanently UNDEFINED in the versions of the architecture specified in this section. Issue C.a of this manual first defines an assembler mnemonic for these encodings. However: • with the Thumb instruction set, ARM deprecates using the UDF instruction in an IT block • in the ARM instruction set, UDF is not conditional. + +@encoding (t1) { + + @half 1 1 0 1 1 1 1 0 imm8(8) + + @syntax <imm32> + + @conv { + + imm32 = ZeroExtend(imm8, 32) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 0 1 1 1 1 1 1 1 imm4(4) 1 0 1 0 imm12(12) + + @syntax ".W" <imm32> + + @conv { + + imm32 = ZeroExtend(imm4:imm12, 32) + + } + +} + +@encoding (A1) { + + @word 1 1 1 0 0 1 1 1 1 1 1 1 imm12(12) 1 1 1 1 imm4(4) + + @syntax <imm32> + + @conv { + + imm32 = ZeroExtend(imm12:imm4, 32) + + } + +} + diff --git a/plugins/arm/v7/opdefs/udiv_A88248.d b/plugins/arm/v7/opdefs/udiv_A88248.d new file mode 100644 index 0000000..eea7947 --- /dev/null +++ b/plugins/arm/v7/opdefs/udiv_A88248.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title UDIV + +@desc Unsigned Divide divides a 32-bit unsigned integer register value by a 32-bit unsigned integer register value, and writes the result to the destination register. The condition flags are not affected. See ARMv7 implementation requirements and options for the divide instructions on page A4-172 for more information about this instruction. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 1 0 1 1 Rn(4) 1 1 1 1 Rd(4) 1 1 1 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 0 0 1 1 Rd(4) 1 1 1 1 Rm(4) 0 0 0 1 Rn(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/uhadd16_A88249.d b/plugins/arm/v7/opdefs/uhadd16_A88249.d new file mode 100644 index 0000000..54da5b0 --- /dev/null +++ b/plugins/arm/v7/opdefs/uhadd16_A88249.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title UHADD16 + +@desc Unsigned Halving Add 16 performs two unsigned 16-bit integer additions, halves the results, and writes the results to the destination register. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/uhadd8_A88250.d b/plugins/arm/v7/opdefs/uhadd8_A88250.d new file mode 100644 index 0000000..759a0a7 --- /dev/null +++ b/plugins/arm/v7/opdefs/uhadd8_A88250.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title UHADD8 + +@desc Unsigned Halving Add 8 performs four unsigned 8-bit integer additions, halves the results, and writes the results to the destination register. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/uhasx_A88251.d b/plugins/arm/v7/opdefs/uhasx_A88251.d new file mode 100644 index 0000000..3751394 --- /dev/null +++ b/plugins/arm/v7/opdefs/uhasx_A88251.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title UHASX + +@desc Unsigned Halving Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, halves the results, and writes the results to the destination register. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/uhsax_A88252.d b/plugins/arm/v7/opdefs/uhsax_A88252.d new file mode 100644 index 0000000..f06b2ba --- /dev/null +++ b/plugins/arm/v7/opdefs/uhsax_A88252.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title UHSAX + +@desc Unsigned Halving Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, halves the results, and writes the results to the destination register. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/uhsub16_A88253.d b/plugins/arm/v7/opdefs/uhsub16_A88253.d new file mode 100644 index 0000000..93f92f7 --- /dev/null +++ b/plugins/arm/v7/opdefs/uhsub16_A88253.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title UHSUB16 + +@desc Unsigned Halving Subtract 16 performs two unsigned 16-bit integer subtractions, halves the results, and writes the results to the destination register. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 0 1 1 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/uhsub8_A88254.d b/plugins/arm/v7/opdefs/uhsub8_A88254.d new file mode 100644 index 0000000..198a095 --- /dev/null +++ b/plugins/arm/v7/opdefs/uhsub8_A88254.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title UHSUB8 + +@desc Unsigned Halving Subtract 8 performs four unsigned 8-bit integer subtractions, halves the results, and writes the results to the destination register. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 1 1 1 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/umaal_A88255.d b/plugins/arm/v7/opdefs/umaal_A88255.d new file mode 100644 index 0000000..34cb707 --- /dev/null +++ b/plugins/arm/v7/opdefs/umaal_A88255.d @@ -0,0 +1,67 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title UMAAL + +@desc Unsigned Multiply Accumulate Accumulate Long multiplies two unsigned 32-bit values to produce a 64-bit value, adds two unsigned 32-bit values, and writes the 64-bit result to two registers. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 1 1 1 0 Rn(4) RdLo(4) RdHi(4) 0 1 1 0 Rm(4) + + @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 0 1 0 0 RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4) + + @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/umlal_A88256.d b/plugins/arm/v7/opdefs/umlal_A88256.d new file mode 100644 index 0000000..00d1903 --- /dev/null +++ b/plugins/arm/v7/opdefs/umlal_A88256.d @@ -0,0 +1,69 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title UMLAL + +@desc Unsigned Multiply Accumulate Long multiplies two unsigned 32-bit values to produce a 64-bit value, and accumulates this with a 64-bit value. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 1 1 1 0 Rn(4) RdLo(4) RdHi(4) 0 0 0 0 Rm(4) + + @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 1 0 1 S(1) RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4) + + @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/umull_A88257.d b/plugins/arm/v7/opdefs/umull_A88257.d new file mode 100644 index 0000000..d2cc321 --- /dev/null +++ b/plugins/arm/v7/opdefs/umull_A88257.d @@ -0,0 +1,69 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title UMULL + +@desc Unsigned Multiply Long multiplies two 32-bit unsigned values to produce a 64-bit result. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 1 0 1 0 Rn(4) RdLo(4) RdHi(4) 0 0 0 0 Rm(4) + + @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 1 0 0 S(1) RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4) + + @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/uqadd16_A88258.d b/plugins/arm/v7/opdefs/uqadd16_A88258.d new file mode 100644 index 0000000..14528c8 --- /dev/null +++ b/plugins/arm/v7/opdefs/uqadd16_A88258.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title UQADD16 + +@desc Unsigned Saturating Add 16 performs two unsigned 16-bit integer additions, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/uqadd8_A88259.d b/plugins/arm/v7/opdefs/uqadd8_A88259.d new file mode 100644 index 0000000..94b8e39 --- /dev/null +++ b/plugins/arm/v7/opdefs/uqadd8_A88259.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title UQADD8 + +@desc Unsigned Saturating Add 8 performs four unsigned 8-bit integer additions, saturates the results to the 8-bit unsigned integer range 0 ≤ x ≤ 28 – 1, and writes the results to the destination register. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/uqasx_A88260.d b/plugins/arm/v7/opdefs/uqasx_A88260.d new file mode 100644 index 0000000..174b08c --- /dev/null +++ b/plugins/arm/v7/opdefs/uqasx_A88260.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title UQASX + +@desc Unsigned Saturating Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/uqsax_A88261.d b/plugins/arm/v7/opdefs/uqsax_A88261.d new file mode 100644 index 0000000..6092e51 --- /dev/null +++ b/plugins/arm/v7/opdefs/uqsax_A88261.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title UQSAX + +@desc Unsigned Saturating Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/uqsub16_A88262.d b/plugins/arm/v7/opdefs/uqsub16_A88262.d new file mode 100644 index 0000000..1f458ff --- /dev/null +++ b/plugins/arm/v7/opdefs/uqsub16_A88262.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title UQSUB16 + +@desc Unsigned Saturating Subtract 16 performs two unsigned 16-bit integer subtractions, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 0 1 1 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/uqsub8_A88263.d b/plugins/arm/v7/opdefs/uqsub8_A88263.d new file mode 100644 index 0000000..37d96e7 --- /dev/null +++ b/plugins/arm/v7/opdefs/uqsub8_A88263.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title UQSUB8 + +@desc Unsigned Saturating Subtract 8 performs four unsigned 8-bit integer subtractions, saturates the results to the 8-bit unsigned integer range 0 ≤ x ≤ 28 – 1, and writes the results to the destination register. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 1 1 1 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/usad8_A88264.d b/plugins/arm/v7/opdefs/usad8_A88264.d new file mode 100644 index 0000000..09d7ece --- /dev/null +++ b/plugins/arm/v7/opdefs/usad8_A88264.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title USAD8 + +@desc Unsigned Sum of Absolute Differences performs four unsigned 8-bit subtractions, and adds the absolute values of the differences together. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 0 1 1 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 1 0 0 0 Rd(4) 1 1 1 1 Rm(4) 0 0 0 1 Rn(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/usada8_A88265.d b/plugins/arm/v7/opdefs/usada8_A88265.d new file mode 100644 index 0000000..dd1efdb --- /dev/null +++ b/plugins/arm/v7/opdefs/usada8_A88265.d @@ -0,0 +1,67 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title USADA8 + +@desc Unsigned Sum of Absolute Differences and Accumulate performs four unsigned 8-bit subtractions, and adds the absolute values of the differences to a 32-bit accumulate operand. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 0 1 1 1 Rn(4) Ra(4) Rd(4) 0 0 0 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <reg_A> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 1 0 0 0 Rd(4) Ra(4) Rm(4) 0 0 0 1 Rn(4) + + @syntax <reg_D> <reg_N> <reg_M> <reg_A> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/usat16_A88267.d b/plugins/arm/v7/opdefs/usat16_A88267.d new file mode 100644 index 0000000..c091dc6 --- /dev/null +++ b/plugins/arm/v7/opdefs/usat16_A88267.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title USAT16 + +@desc Unsigned Saturate 16 saturates two signed 16-bit values to a selected unsigned range. The Q flag is set if the operation saturates. + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 1 0 1 0 Rn(4) 0 0 0 0 Rd(4) 0 0 0 0 sat_imm(4) + + @syntax <reg_D> <saturate_to> <reg_N> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + saturate_to = UInt(sat_imm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 1 1 0 sat_imm(4) Rd(4) 1 1 1 1 0 0 1 1 Rn(4) + + @syntax <reg_D> <saturate_to> <reg_N> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + saturate_to = UInt(sat_imm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/usat_A88266.d b/plugins/arm/v7/opdefs/usat_A88266.d new file mode 100644 index 0000000..55de21a --- /dev/null +++ b/plugins/arm/v7/opdefs/usat_A88266.d @@ -0,0 +1,67 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title USAT + +@desc Unsigned Saturate saturates an optionally-shifted signed value to a selected unsigned range. The Q flag is set if the operation saturates. + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 1 0 sh(1) 0 Rn(4) 0 imm3(3) Rd(4) imm2(2) 0 sat_imm(5) + + @syntax <reg_D> <saturate_to> <reg_N> <?shift> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + saturate_to = UInt(sat_imm) + shift = DecodeImmShift(sh:'0', imm3:imm2) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 1 1 sat_imm(5) Rd(4) imm5(5) sh(1) 0 1 Rn(4) + + @syntax <reg_D> <saturate_to> <reg_N> <?shift> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + saturate_to = UInt(sat_imm) + shift = DecodeImmShift(sh:'0', imm5) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/usax_A88268.d b/plugins/arm/v7/opdefs/usax_A88268.d new file mode 100644 index 0000000..040eedc --- /dev/null +++ b/plugins/arm/v7/opdefs/usax_A88268.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title USAX + +@desc Unsigned Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, and writes the results to the destination register. It sets the APSR.GE bits according to the results. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/usub16_A88269.d b/plugins/arm/v7/opdefs/usub16_A88269.d new file mode 100644 index 0000000..31796d9 --- /dev/null +++ b/plugins/arm/v7/opdefs/usub16_A88269.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title USUB16 + +@desc Unsigned Subtract 16 performs two 16-bit unsigned integer subtractions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the subtractions. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 0 1 1 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/usub8_A88270.d b/plugins/arm/v7/opdefs/usub8_A88270.d new file mode 100644 index 0000000..576894c --- /dev/null +++ b/plugins/arm/v7/opdefs/usub8_A88270.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title USUB8 + +@desc Unsigned Subtract 8 performs four 8-bit unsigned integer subtractions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the subtractions. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 1 1 1 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/uxtab16_A88272.d b/plugins/arm/v7/opdefs/uxtab16_A88272.d new file mode 100644 index 0000000..4fc61d2 --- /dev/null +++ b/plugins/arm/v7/opdefs/uxtab16_A88272.d @@ -0,0 +1,67 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title UXTAB16 + +@desc Unsigned Extend and Add Byte 16 extracts two 8-bit values from a register, zero-extends them to 16 bits each, adds the results to two 16-bit values from another register, and writes the final results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 0 0 1 1 Rn(4) 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <?rotation> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 1 0 0 Rn(4) Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <?rotation> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/uxtab_A88271.d b/plugins/arm/v7/opdefs/uxtab_A88271.d new file mode 100644 index 0000000..fe27d4b --- /dev/null +++ b/plugins/arm/v7/opdefs/uxtab_A88271.d @@ -0,0 +1,67 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title UXTAB + +@desc Unsigned Extend and Add Byte extracts an 8-bit value from a register, zero-extends it to 32 bits, adds the result to the value in another register, and writes the final result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 0 1 0 1 Rn(4) 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <?rotation> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 1 1 0 Rn(4) Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <?rotation> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/uxtah_A88273.d b/plugins/arm/v7/opdefs/uxtah_A88273.d new file mode 100644 index 0000000..3c587d9 --- /dev/null +++ b/plugins/arm/v7/opdefs/uxtah_A88273.d @@ -0,0 +1,67 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title UXTAH + +@desc Unsigned Extend and Add Halfword extracts a 16-bit value from a register, zero-extends it to 32 bits, adds the result to a value from another register, and writes the final result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 0 0 0 1 Rn(4) 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <?rotation> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 1 1 1 Rn(4) Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) + + @syntax <reg_D> <reg_N> <reg_M> <?rotation> + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/uxtb16_A88275.d b/plugins/arm/v7/opdefs/uxtb16_A88275.d new file mode 100644 index 0000000..a30d133 --- /dev/null +++ b/plugins/arm/v7/opdefs/uxtb16_A88275.d @@ -0,0 +1,65 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title UXTB16 + +@desc Unsigned Extend Byte 16 extracts two 8-bit values from a register, zero-extends them to 16 bits each, and writes the results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values. + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) + + @syntax <reg_D> <reg_M> <?rotation> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 1 0 0 1 1 1 1 Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) + + @syntax <reg_D> <reg_M> <?rotation> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/uxtb_A88274.d b/plugins/arm/v7/opdefs/uxtb_A88274.d new file mode 100644 index 0000000..f49ba83 --- /dev/null +++ b/plugins/arm/v7/opdefs/uxtb_A88274.d @@ -0,0 +1,80 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title UXTB + +@desc Unsigned Extend Byte extracts an 8-bit value from a register, zero-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value. + +@encoding (t1) { + + @half 1 0 1 1 0 0 1 0 1 1 Rm(3) Rd(3) + + @syntax <reg_D> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) + + @syntax ".W" <reg_D> <reg_M> <?rotation> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 1 1 0 1 1 1 1 Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) + + @syntax <reg_D> <reg_M> <?rotation> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/uxth_A88276.d b/plugins/arm/v7/opdefs/uxth_A88276.d new file mode 100644 index 0000000..5ae4f4f --- /dev/null +++ b/plugins/arm/v7/opdefs/uxth_A88276.d @@ -0,0 +1,80 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title UXTH + +@desc Unsigned Extend Halfword extracts a 16-bit value from a register, zero-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value. + +@encoding (t1) { + + @half 1 0 1 1 0 0 1 0 1 0 Rm(3) Rd(3) + + @syntax <reg_D> <reg_M> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) + + @syntax ".W" <reg_D> <reg_M> <?rotation> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 1 1 1 1 1 1 1 Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) + + @syntax <reg_D> <reg_M> <?rotation> + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/wfi_A88425.d b/plugins/arm/v7/opdefs/wfi_A88425.d new file mode 100644 index 0000000..f11d033 --- /dev/null +++ b/plugins/arm/v7/opdefs/wfi_A88425.d @@ -0,0 +1,53 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title WFI + +@desc Wait For Interrupt is a hint instruction that permits the processor to enter a low-power state until one of a number of asynchronous events occurs. For more information, see Wait For Interrupt on page B1-1202. In an implementation that includes the Virtualization Extensions, if HCR.TWI is set to 1, execution of a WFI instruction in a Non-secure mode other than Hyp mode generates a Hyp Trap exception if, ignoring the value of the HCR.TWI bit, conditions permit the processor to suspend execution. For more information see Trapping use of the WFI and WFE instructions on page B1-1255. + +@encoding (t1) { + + @half 1 0 1 1 1 1 1 1 0 0 1 1 0 0 0 0 + +} + +@encoding (T2) { + + @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 + + @syntax ".W" + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/plugins/arm/v7/opdefs/yield_A88426.d b/plugins/arm/v7/opdefs/yield_A88426.d new file mode 100644 index 0000000..252c018 --- /dev/null +++ b/plugins/arm/v7/opdefs/yield_A88426.d @@ -0,0 +1,53 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title YIELD + +@desc YIELD is a hint instruction. Software with a multithreading capability can use a YIELD instruction to indicate to the hardware that it is performing a task, for example a spin-lock, that could be swapped out to improve overall system performance. Hardware can use this hint to suspend and resume multiple software threads if it supports the capability. For more information about the recommended use of this instruction see The Yield instruction on page A4-178. + +@encoding (t1) { + + @half 1 0 1 1 1 1 1 1 0 0 0 1 0 0 0 0 + +} + +@encoding (T2) { + + @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 + + @syntax ".W" + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 + + @rules { + + chk_call StoreCondition(cond) + + } + +} + |