1 files changed, 51 insertions, 11 deletions
diff --git a/plugins/arm/v7/opdefs/sub_A88222.d b/plugins/arm/v7/opdefs/sub_A88222.d
index ef326b8..289d045 100644
--- a/plugins/arm/v7/opdefs/sub_A88222.d
+++ b/plugins/arm/v7/opdefs/sub_A88222.d
@@ -2,7 +2,7 @@
 /* Chrysalide - Outil d'analyse de fichiers binaires
  * ##FILE## - traduction d'instructions ARMv7
  *
- * Copyright (C) 2015 Cyrille Bagard
+ * Copyright (C) 2017 Cyrille Bagard
  *
  *  This file is part of Chrysalide.
  *
@@ -23,27 +23,67 @@
 
 @title SUB (immediate, ARM)
 
-@desc This instruction subtracts an immediate value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result.
+@id 221
+
+@desc {
+
+	This instruction subtracts an immediate value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result.
+
+}
 
 @encoding (A1) {
 
 	@word cond(4) 0 0 1 0 0 1 0 S(1) Rn(4) Rd(4) imm12(12)
 
-	@syntax <reg_D> <reg_N> <imm32>
+	@syntax {
+
+		@assert {
+
+			S == 0
+
+		}
+
+		@conv {
+
+			reg_D = Register(Rd)
+			reg_N = Register(Rn)
+			imm32 = ARMExpandImm(imm12)
+
+		}
+
+		@asm sub ?reg_D reg_N imm32
 
-	@conv {
+		@rules {
 
-		reg_D = Register(Rd)
-		reg_N = Register(Rn)
-		setflags = (S == '1')
-		imm32 = ARMExpandImm(imm12)
+			check g_arm_instruction_set_cond(cond)
+
+		}
 
 	}
 
-	@rules {
+	@syntax {
+
+		@assert {
+
+			S == 1
+
+		}
+
+		@conv {
+
+			reg_D = Register(Rd)
+			reg_N = Register(Rn)
+			imm32 = ARMExpandImm(imm12)
+
+		}
+
+		@asm subs ?reg_D reg_N imm32
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
 
-		if (setflags); chk_call ExtendKeyword("s")
-		chk_call StoreCondition(cond)
+		}
 
 	}