diff options
Diffstat (limited to 'plugins/arm/v7/opdefs/sub_A88225.d')
| -rw-r--r-- | plugins/arm/v7/opdefs/sub_A88225.d | 130 |
1 files changed, 100 insertions, 30 deletions
diff --git a/plugins/arm/v7/opdefs/sub_A88225.d b/plugins/arm/v7/opdefs/sub_A88225.d index dc54c6b..96708b9 100644 --- a/plugins/arm/v7/opdefs/sub_A88225.d +++ b/plugins/arm/v7/opdefs/sub_A88225.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title SUB (SP minus immediate) -@desc This instruction subtracts an immediate value from the SP value, and writes the result to the destination register. +@id 224 + +@desc { + + This instruction subtracts an immediate value from the SP value, and writes the result to the destination register. + +} @encoding (t1) { @half 1 0 1 1 0 0 0 0 1 imm7(7) - @syntax <SP_0> <SP_1> <imm32> + @syntax { + + @conv { - @conv { + reg_D = Register(13) + reg_SP = Register(13) + imm32 = ZeroExtend(imm7:'00', 32) - imm32 = ZeroExtend(imm7:'00', 32) - SP_0 = Register(13) - SP_1 = Register(13) + } + + @asm sub ?reg_D reg_SP imm32 } @@ -45,21 +55,43 @@ @word 1 1 1 1 0 i(1) 0 1 1 0 1 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <SP> <imm32> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - setflags = (S == '1') - imm32 = ThumbExpandImm(i:imm3:imm8) - SP = Register(13) + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm sub.w ?reg_D reg_SP imm32 } - @rules { + @syntax { + + @assert { + + S == 1 + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm subs.w ?reg_D reg_SP imm32 } @@ -69,13 +101,17 @@ @word 1 1 1 1 0 i(1) 1 0 1 0 1 0 1 1 0 1 0 imm3(3) Rd(4) imm8(8) - @syntax "subw" <reg_D> <SP> <imm32> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ZeroExtend(i:imm3:imm8, 32) - reg_D = Register(Rd) - imm32 = ZeroExtend(i:imm3:imm8, 32) - SP = Register(13) + } + + @asm subw ?reg_D reg_SP imm32 } @@ -85,21 +121,55 @@ @word cond(4) 0 0 1 0 0 1 0 S(1) 1 1 0 1 Rd(4) imm12(12) - @syntax <reg_D> <SP> <imm32> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ARMExpandImm(imm12) + + } + + @asm sub ?reg_D reg_SP imm32 + + @rules { - @conv { + check g_arm_instruction_set_cond(cond) - reg_D = Register(Rd) - setflags = (S == '1') - imm32 = ARMExpandImm(imm12) - SP = Register(13) + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ARMExpandImm(imm12) + + } + + @asm subs ?reg_D reg_SP imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } |