diff options
Diffstat (limited to 'plugins/arm/v7/opdefs/svc_A88228.d')
| -rw-r--r-- | plugins/arm/v7/opdefs/svc_A88228.d | 36 |
1 files changed, 25 insertions, 11 deletions
diff --git a/plugins/arm/v7/opdefs/svc_A88228.d b/plugins/arm/v7/opdefs/svc_A88228.d index be48545..0ddc95f 100644 --- a/plugins/arm/v7/opdefs/svc_A88228.d +++ b/plugins/arm/v7/opdefs/svc_A88228.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,17 +23,27 @@ @title SVC (previously SWI) -@desc Supervisor Call, previously called Software Interrupt, causes a Supervisor Call exception. For more information, see Supervisor Call (SVC) exception on page B1-1209. Software can use this instruction as a call to an operating system to provide a service. In the following cases, the Supervisor Call exception generated by the SVC instruction is taken to Hyp mode: • If the SVC is executed in Hyp mode. • If HCR.TGE is set to 1, and the SVC is executed in Non-secure User mode. For more information, see Supervisor Call exception, when HCR.TGE is set to 1 on page B1-1191 In these cases, the HSR identifies that the exception entry was caused by a Supervisor Call exception, EC value 0x11, see Use of the HSR on page B3-1424. The immediate field in the HSR: • if the SVC is unconditional: — for the Thumb instruction, is the zero-extended value of the imm8 field — for the ARM instruction, is the least-significant 16 bits the imm24 field • if the SVC is conditional, is UNKNOWN. +@id 227 + +@desc { + + Supervisor Call, previously called Software Interrupt, causes a Supervisor Call exception. For more information, see Supervisor Call (SVC) exception on page B1-1209. Software can use this instruction as a call to an operating system to provide a service. In the following cases, the Supervisor Call exception generated by the SVC instruction is taken to Hyp mode: • If the SVC is executed in Hyp mode. • If HCR.TGE is set to 1, and the SVC is executed in Non-secure User mode. For more information, see Supervisor Call exception, when HCR.TGE is set to 1 on page B1-1191 In these cases, the HSR identifies that the exception entry was caused by a Supervisor Call exception, EC value 0x11, see Use of the HSR on page B3-1424. The immediate field in the HSR: • if the SVC is unconditional: — for the Thumb instruction, is the zero-extended value of the imm8 field — for the ARM instruction, is the least-significant 16 bits the imm24 field • if the SVC is conditional, is UNKNOWN. + +} @encoding (t1) { @half 1 1 0 1 1 1 1 1 imm8(8) - @syntax <imm32> + @syntax { + + @conv { - @conv { + imm32 = ZeroExtend(imm8, 32) - imm32 = ZeroExtend(imm8, 32) + } + + @asm svc imm32 } @@ -43,17 +53,21 @@ @word cond(4) 1 1 1 1 imm24(24) - @syntax <imm32> + @syntax { - @conv { + @conv { - imm32 = ZeroExtend(imm24, 32) + imm32 = ZeroExtend(imm24, 32) - } + } + + @asm svc imm32 + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } |