diff options
Diffstat (limited to 'plugins/arm/v7/opdefs/teq_A88238.d')
| -rw-r--r-- | plugins/arm/v7/opdefs/teq_A88238.d | 44 |
1 files changed, 29 insertions, 15 deletions
diff --git a/plugins/arm/v7/opdefs/teq_A88238.d b/plugins/arm/v7/opdefs/teq_A88238.d index 8187d81..9e80034 100644 --- a/plugins/arm/v7/opdefs/teq_A88238.d +++ b/plugins/arm/v7/opdefs/teq_A88238.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title TEQ (register) -@desc Test Equivalence (register) performs a bitwise exclusive OR operation on a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result. +@id 237 + +@desc { + + Test Equivalence (register) performs a bitwise exclusive OR operation on a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result. + +} @encoding (T1) { @word 1 1 1 0 1 0 1 0 1 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm2(2) type(2) Rm(4) - @syntax <reg_N> <reg_M> <?shift> + @syntax { + + @conv { - @conv { + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) + } + + @asm teq reg_N reg_M ?shift } @@ -45,19 +55,23 @@ @word cond(4) 0 0 0 1 0 0 1 1 Rn(4) 0 0 0 0 imm5(5) type(2) 0 Rm(4) - @syntax <reg_N> <reg_M> <?shift> + @syntax { - @conv { + @conv { - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) - } + } + + @asm teq reg_N reg_M ?shift + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } |