diff options
Diffstat (limited to 'plugins/arm/v7/opdefs/tst_A88242.d')
| -rw-r--r-- | plugins/arm/v7/opdefs/tst_A88242.d | 32 |
1 files changed, 22 insertions, 10 deletions
diff --git a/plugins/arm/v7/opdefs/tst_A88242.d b/plugins/arm/v7/opdefs/tst_A88242.d index d3fdd9c..7ffb302 100644 --- a/plugins/arm/v7/opdefs/tst_A88242.d +++ b/plugins/arm/v7/opdefs/tst_A88242.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,25 +23,37 @@ @title TST (register-shifted register) -@desc Test (register-shifted register) performs a bitwise AND operation on a register value and a register-shifted register value. It updates the condition flags based on the result, and discards the result. +@id 241 + +@desc { + + Test (register-shifted register) performs a bitwise AND operation on a register value and a register-shifted register value. It updates the condition flags based on the result, and discards the result. + +} @encoding (A1) { @word cond(4) 0 0 0 1 0 0 0 1 Rn(4) 0 0 0 0 Rs(4) 0 type(2) 1 Rm(4) - @syntax <reg_N> <reg_M> <reg_shift> + @syntax { - @conv { + @conv { - reg_shift = RegisterShift(type, Rs) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) - } + } + + @asm tst reg_N reg_M shift + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } |