diff options
Diffstat (limited to 'src/arch/arm/v7/opdefs/asr_A8816.d')
| -rw-r--r-- | src/arch/arm/v7/opdefs/asr_A8816.d | 76 |
1 files changed, 37 insertions, 39 deletions
diff --git a/src/arch/arm/v7/opdefs/asr_A8816.d b/src/arch/arm/v7/opdefs/asr_A8816.d index 7c1fda6..006a26c 100644 --- a/src/arch/arm/v7/opdefs/asr_A8816.d +++ b/src/arch/arm/v7/opdefs/asr_A8816.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2015 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,71 +23,69 @@ @title ASR (immediate) -@encoding(t1) { +@desc Arithmetic Shift Right (immediate) shifts a register value right by an immediate number of bits, shifting in copies of its sign bit, and writes the result to the destination register. It can optionally update the condition flags based on the result. - @half 0 0 0 1 0 imm5(5) Rm(3) Rd(3) +@encoding (t1) { - @syntax <Rd> <Rm> <#imm> + @half 0 0 0 1 0 imm5(5) Rm(3) Rd(3) - @conv { + @syntax "asrs" <reg_D> <reg_M> <shift_imm> - Rd = Register(Rd) - Rm = Register(Rm) - imm = FixedShift(2, imm5) + @conv { - } + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_imm = DecodeImmShift('10', imm5) - @rules { - - //setflags = !InITBlock(); - - } + } } -@encoding(T2) { +@encoding (T2) { - @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 1 0 Rm(4) + @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 1 0 Rm(4) - @syntax {S} ".W" <Rd> <Rm> <#imm> + @syntax <reg_D> <reg_M> <shift_imm> - @conv { + @conv { - S = SetFlags(S) - Rd = Register(Rd) - Rm = Register(Rm) - imm = FixedShift(2, imm3:imm2) + reg_D = Register(Rd) + reg_M = Register(Rm) + setflags = (S == '1') + shift_imm = DecodeImmShift('10', imm3:imm2) - } + } - @rules { + @rules { - //if d IN {13,15} || m IN {13,15} then UNPREDICTABLE; + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") - } + } } -@encoding(A1) { +@encoding (A1) { - @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 1 0 0 Rm(4) + @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 1 0 0 Rm(4) - @syntax {S} {c} <Rd> <Rm> <#imm> + @syntax <reg_D> <reg_M> <shift_imm> - @conv { + @conv { - S = SetFlags(S) - c = Condition(cond) - Rd = Register(Rd) - Rm = Register(Rm) - imm = FixedShift(2, imm5) + reg_D = Register(Rd) + reg_M = Register(Rm) + setflags = (S == '1') + shift_imm = DecodeImmShift('10', imm5) - } + } - @rules { + @rules { - //if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) - } + } } + |