diff options
Diffstat (limited to 'src/arch/arm/v7/opdefs/sub_A88225.d')
| -rw-r--r-- | src/arch/arm/v7/opdefs/sub_A88225.d | 99 |
1 files changed, 45 insertions, 54 deletions
diff --git a/src/arch/arm/v7/opdefs/sub_A88225.d b/src/arch/arm/v7/opdefs/sub_A88225.d index e37997f..dc54c6b 100644 --- a/src/arch/arm/v7/opdefs/sub_A88225.d +++ b/src/arch/arm/v7/opdefs/sub_A88225.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2015 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,94 +23,85 @@ @title SUB (SP minus immediate) -@encoding(t1) { +@desc This instruction subtracts an immediate value from the SP value, and writes the result to the destination register. - @half 1 0 1 1 0 0 0 0 1 imm7(7) +@encoding (t1) { - @syntax <SP1> <SP2> <const> + @half 1 0 1 1 0 0 0 0 1 imm7(7) - @conv { + @syntax <SP_0> <SP_1> <imm32> - SP1 = Register(13) - SP2 = Register(13) - const = ZeroExtend(imm7:'00', 9, 32); + @conv { - } + imm32 = ZeroExtend(imm7:'00', 32) + SP_0 = Register(13) + SP_1 = Register(13) - @rules { - - //setflags = FALSE - - } + } } -@encoding(T2) { +@encoding (T2) { - @word 1 1 1 1 0 i(1) 0 1 1 0 1 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm8(8) + @word 1 1 1 1 0 i(1) 0 1 1 0 1 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm8(8) - @syntax {S} ".W" <Rd> <SP> <const> + @syntax <reg_D> <SP> <imm32> - @conv { + @conv { - S = SetFlags(S) - Rd = Register(Rd) - SP = Register(13) - const = ThumbExpandImm(i:imm3:imm8) + reg_D = Register(Rd) + setflags = (S == '1') + imm32 = ThumbExpandImm(i:imm3:imm8) + SP = Register(13) - } + } - @rules { + @rules { - //if Rd == '1111' && S == '1' then SEE CMP (immediate); - //if d == 15 && S == '0' then UNPREDICTABLE; + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") - } + } } -@encoding(T3) { - - @word 1 1 1 1 0 i(1) 1 0 1 0 1 0 1 1 0 1 0 imm3(3) Rd(4) imm8(8) +@encoding (T3) { - @syntax "subw" <Rd> <SP> <const> + @word 1 1 1 1 0 i(1) 1 0 1 0 1 0 1 1 0 1 0 imm3(3) Rd(4) imm8(8) - @conv { + @syntax "subw" <reg_D> <SP> <imm32> - Rd = Register(Rd) - SP = Register(13) - const = ZeroExtend(i:imm3:imm8, 12, 32) + @conv { - } + reg_D = Register(Rd) + imm32 = ZeroExtend(i:imm3:imm8, 32) + SP = Register(13) - @rules { - - //if d == 15 then UNPREDICTABLE; - - } + } } -@encoding(A1) { +@encoding (A1) { - @word cond(4) 0 0 1 0 0 1 0 S(1) 1 1 0 1 Rd(4) imm12(12) + @word cond(4) 0 0 1 0 0 1 0 S(1) 1 1 0 1 Rd(4) imm12(12) - @syntax {S} {c} <Rd> <SP> <const> + @syntax <reg_D> <SP> <imm32> - @conv { + @conv { - S = SetFlags(S) - c = Condition(cond) - Rd = Register(Rd) - SP = Register(13) - const = ARMExpandImm(imm12) + reg_D = Register(Rd) + setflags = (S == '1') + imm32 = ARMExpandImm(imm12) + SP = Register(13) - } + } - @rules { + @rules { - //if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) - } + } } + |