diff options
Diffstat (limited to 'src/arch/arm')
292 files changed, 0 insertions, 32435 deletions
diff --git a/src/arch/arm/Makefile.am b/src/arch/arm/Makefile.am deleted file mode 100644 index 496872a..0000000 --- a/src/arch/arm/Makefile.am +++ /dev/null @@ -1,27 +0,0 @@ - -noinst_LTLIBRARIES = libarcharm.la - -libarcharm_la_SOURCES = \ - cond.h \ - context-int.h \ - context.h context.c \ - instruction-int.h \ - instruction.h instruction.c \ - link.h link.c \ - processor-int.h \ - processor.h processor.c \ - register-int.h \ - register.h register.c - -libarcharm_la_LIBADD = \ - v7/libarcharmv7.la - -libarcharm_la_CFLAGS = $(AM_CFLAGS) - - -AM_CPPFLAGS = $(LIBGTK_CFLAGS) $(LIBXML_CFLAGS) - -AM_CFLAGS = $(DEBUG_CFLAGS) $(WARNING_FLAGS) $(COMPLIANCE_FLAGS) - - -SUBDIRS = v7 diff --git a/src/arch/arm/cond.h b/src/arch/arm/cond.h deleted file mode 100644 index 549d368..0000000 --- a/src/arch/arm/cond.h +++ /dev/null @@ -1,64 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * encoding.h - prototypes pour le décodage des conditions d'exécution ARM - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_ARM_ENCODING_H -#define _ARCH_ARM_ENCODING_H - - - -/** - * Les conditions d'exécutions sont partagées par les architectures ARM : - * - * ARMv7 Instruction Details - * § A8.3 Conditional execution - * - * ARMv8 Instruction Set Overview. - * § 4.3 Condition Codes. - * - */ - -/* Liste des conditions possibles */ -typedef enum _ArmCondCode -{ - ACC_EQ = 0x0, /* Equal */ - ACC_NE = 0x1, /* Not equal */ - ACC_HS = 0x2, /* Unsigned higher or same */ - ACC_LO = 0x3, /* Unsigned lower */ - ACC_MI = 0x4, /* Minus */ - ACC_PL = 0x5, /* Plus or zero */ - ACC_VS = 0x6, /* Overflow set */ - ACC_VC = 0x7, /* Overflow clear */ - ACC_HI = 0x8, /* Unsigned higher */ - ACC_LS = 0x9, /* Unsigned lower or same */ - ACC_GE = 0xa, /* Signed greater than or equal*/ - ACC_LT = 0xb, /* Signed less than */ - ACC_GT = 0xc, /* Signed greater than */ - ACC_LE = 0xd, /* Signed less than or equal */ - ACC_AL = 0xe, /* Always */ - ACC_NV = 0xf, /* (Never) */ - -} ArmCondCode; - - - -#endif /* _ARCH_ARM_ENCODING_H */ diff --git a/src/arch/arm/context-int.h b/src/arch/arm/context-int.h deleted file mode 100644 index 4e7d9a3..0000000 --- a/src/arch/arm/context-int.h +++ /dev/null @@ -1,75 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * context-int.h - prototypes internes pour le contexte lié à l'exécution d'un processeur - * - * Copyright (C) 2015-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_ARM_CONTEXT_INT_H -#define _ARCH_ARM_CONTEXT_INT_H - - -#include "context.h" - - -#include "../context-int.h" - - - -/* Découpage de la zone de désassemblage */ -typedef struct _disass_arm_area -{ - virt_t start; /* Début de la zone */ - virt_t end; /* Fin de la zone */ - - unsigned int marker; /* Type de décodage associé */ - -} disass_arm_area; - - -/* Définition d'un contexte pour processeur ARM (instance) */ -struct _GArmContext -{ - GProcContext parent; /* A laisser en premier */ - - disass_arm_area *areas; /* Désassemblage découpé */ - size_t acount; /* Nombre de zones définies */ - GMutex areas_access; /* Accès aux découpes de zones */ - -}; - - -/* Définition d'un contexte pour processeur ARM (classe) */ -struct _GArmContextClass -{ - GProcContextClass parent; /* A laisser en premier */ - -}; - - - -/* Enregistre l'encodage (générique) utilisé à une adresse. */ -void _g_arm_context_define_encoding(GArmContext *, virt_t, unsigned int); - -/* Indique l'encodage (générique) utilisé à une adresse donnée. */ -unsigned int _g_arm_context_find_encoding(GArmContext *, virt_t); - - - -#endif /* _ARCH_ARM_CONTEXT_INT_H */ diff --git a/src/arch/arm/context.c b/src/arch/arm/context.c deleted file mode 100644 index 15c7bf5..0000000 --- a/src/arch/arm/context.c +++ /dev/null @@ -1,447 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * context.c - contexte lié à l'exécution d'un processeur - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#include "context.h" - - -#include <assert.h> -#include <malloc.h> -#include <string.h> - - -#include "context-int.h" - - - -/* ------------------------ MANIPULATION GLOBALE DU CONTEXTE ------------------------ */ - - -/* Initialise la classe des contextes de processeur ARM. */ -static void g_arm_context_class_init(GArmContextClass *); - -/* Initialise une instance de contexte de processeur ARM. */ -static void g_arm_context_init(GArmContext *); - -/* Supprime toutes les références externes. */ -static void g_arm_context_dispose(GArmContext *); - -/* Procède à la libération totale de la mémoire. */ -static void g_arm_context_finalize(GArmContext *); - -/* Indique l'encodage (générique) utilisé à une adresse donnée. */ -static size_t find_disass_arm_area(disass_arm_area *, virt_t, size_t, size_t); - - - -/* ------------------------- CONTEXTE POUR LA DECOMPILATION ------------------------- */ - -#if 0 -/* Définition d'un contexte pour décompilation ARM (instance) */ -struct _GArmDContext -{ - GDecContext parent; /* A laisser en premier */ - - GDecInstruction *this; /* Représentation de la classe */ - GHashTable *args; /* Correspondance arg./pseudo */ - GHashTable *locals; /* Correspondance var./pseudo */ - size_t locals_count; /* Quantité de var. locales */ - -}; - - -/* Définition d'un contexte pour décompilation ARM (classe) */ -struct _GArmDContextClass -{ - GDecContextClass parent; /* A laisser en premier */ - -}; - - -/* Initialise la classe des contextes de décompilation ARM. */ -static void g_arm_dcontext_class_init(GArmDContextClass *); - -/* Initialise une instance de contexte de décompilation ARM. */ -static void g_arm_dcontext_init(GArmDContext *); - -/* Supprime toutes les références externes. */ -static void g_arm_dcontext_dispose(GArmDContext *); - -/* Procède à la libération totale de la mémoire. */ -static void g_arm_dcontext_finalize(GArmDContext *); -#endif - - - -/* ---------------------------------------------------------------------------------- */ -/* MANIPULATION GLOBALE DU CONTEXTE */ -/* ---------------------------------------------------------------------------------- */ - - -/* Indique le type définit par la GLib pour le contexte de processeur ARM. */ -G_DEFINE_TYPE(GArmContext, g_arm_context, G_TYPE_PROC_CONTEXT); - - -/****************************************************************************** -* * -* Paramètres : klass = classe à initialiser. * -* * -* Description : Initialise la classe des contextes de processeur ARM. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_arm_context_class_init(GArmContextClass *klass) -{ - GObjectClass *object; /* Autre version de la classe */ - - object = G_OBJECT_CLASS(klass); - - object->dispose = (GObjectFinalizeFunc/* ! */)g_arm_context_dispose; - object->finalize = (GObjectFinalizeFunc)g_arm_context_finalize; - -} - - -/****************************************************************************** -* * -* Paramètres : ctx = instance à initialiser. * -* * -* Description : Initialise une instance de contexte de processeur ARM. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_arm_context_init(GArmContext *ctx) -{ - g_mutex_init(&ctx->areas_access); - -} - - -/****************************************************************************** -* * -* Paramètres : ctx = instance d'objet GLib à traiter. * -* * -* Description : Supprime toutes les références externes. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_arm_context_dispose(GArmContext *ctx) -{ - g_mutex_clear(&ctx->areas_access); - - G_OBJECT_CLASS(g_arm_context_parent_class)->dispose(G_OBJECT(ctx)); - -} - - -/****************************************************************************** -* * -* Paramètres : ctx = instance d'objet GLib à traiter. * -* * -* Description : Procède à la libération totale de la mémoire. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_arm_context_finalize(GArmContext *ctx) -{ - G_OBJECT_CLASS(g_arm_context_parent_class)->finalize(G_OBJECT(ctx)); - -} - - -/****************************************************************************** -* * -* Paramètres : - * -* * -* Description : Crée un contexte pour l'exécution du processeur ARM. * -* * -* Retour : Contexte mis en place. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArmContext *g_arm_context_new(void) -{ - GArmContext *result; /* Structure à retourner */ - - result = g_object_new(G_TYPE_ARM_CONTEXT, NULL); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : areas = ensemble des découpages du désassemblage. * -* addr = adresse d'un nouveau point de départ à retrouver. * -* first = indice de la première zone à considérer. * -* last = indice de la dernière zone à considérer. * -* * -* Description : Indique l'encodage (générique) utilisé à une adresse donnée. * -* * -* Retour : Marqueur à priori toujours valide. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static size_t find_disass_arm_area(disass_arm_area *areas, virt_t addr, size_t first, size_t last) -{ - size_t index; /* Indice de cellule idéale */ - size_t mid; /* Division de l'espace */ - - if (first == last) - index = first; - - else - { - mid = first + (last - first + 1) / 2; - - if (areas[mid].start <= addr) - index = find_disass_arm_area(areas, addr, mid, last); - else - index = find_disass_arm_area(areas, addr, first, mid - 1); - - } - - assert(areas[index].start <= addr && addr <= areas[index].end); - - return index; - -} - - -/****************************************************************************** -* * -* Paramètres : ctx = contexte de désassemblage à compléter. * -* addr = adresse d'un nouveau point de départ à créer. * -* marker = forme générique d'un encodage à mémoriser. * -* * -* Description : Enregistre l'encodage (générique) utilisé à une adresse. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -void _g_arm_context_define_encoding(GArmContext *ctx, virt_t addr, unsigned int marker) -{ - size_t selected; /* Zone associée à une adresse */ - - g_mutex_lock(&ctx->areas_access); - - selected = find_disass_arm_area(ctx->areas, addr, 0, ctx->acount - 1); - - //assert(ctx->areas[selected].start != addr || ctx->areas[selected].marker == marker); - - /* S'agit-il d'une redéfinition ? */ - if (ctx->areas[selected].start == addr) - ctx->areas[selected].marker = marker; - - /* Sinon on redivise... */ - else - { - ctx->areas = (disass_arm_area *)realloc(ctx->areas, ++ctx->acount * sizeof(disass_arm_area)); - - memmove(&ctx->areas[selected + 1], &ctx->areas[selected], - (ctx->acount - selected - 1) * sizeof(disass_arm_area)); - - ctx->areas[selected].start = ctx->areas[selected + 1].start; - ctx->areas[selected].end = addr - 1; - ctx->areas[selected].marker = ctx->areas[selected + 1].marker; - - ctx->areas[selected + 1].start = addr; - ctx->areas[selected + 1].marker = marker; - - } - - g_mutex_unlock(&ctx->areas_access); - -} - - -/****************************************************************************** -* * -* Paramètres : ctx = contexte de désassemblage à consulter. * -* addr = adresse d'un nouveau point de départ à retrouver. * -* * -* Description : Indique l'encodage (générique) utilisé à une adresse donnée. * -* * -* Retour : Marqueur à priori toujours valide. * -* * -* Remarques : - * -* * -******************************************************************************/ - -unsigned int _g_arm_context_find_encoding(GArmContext *ctx, virt_t addr) -{ - unsigned int result; /* Identifiant à retourner */ - size_t selected; /* Zone associée à une adresse */ - - g_mutex_lock(&ctx->areas_access); - - selected = find_disass_arm_area(ctx->areas, addr, 0, ctx->acount - 1); - - result = ctx->areas[selected].marker; - - g_mutex_unlock(&ctx->areas_access); - - return result; - -} - - - - - - - -/* ---------------------------------------------------------------------------------- */ -/* CONTEXTE POUR LA DECOMPILATION */ -/* ---------------------------------------------------------------------------------- */ - -#if 0 -/* Indique le type définit par la GLib pour le contexte de décompilation ARM. */ -G_DEFINE_TYPE(GArmDContext, g_arm_dcontext, G_TYPE_DEC_CONTEXT); - - -/****************************************************************************** -* * -* Paramètres : class = classe à initialiser. * -* * -* Description : Initialise la classe des contextes de décompilation ARM. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_arm_dcontext_class_init(GArmDContextClass *class) -{ - GObjectClass *object; /* Autre version de la classe */ - - object = G_OBJECT_CLASS(class); - - object->dispose = (GObjectFinalizeFunc/* ! */)g_arm_dcontext_dispose; - object->finalize = (GObjectFinalizeFunc)g_arm_dcontext_finalize; - -} - - -/****************************************************************************** -* * -* Paramètres : ctx = instance à initialiser. * -* * -* Description : Initialise une instance de contexte de décompilation ARM. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_arm_dcontext_init(GArmDContext *ctx) -{ - -} - - -/****************************************************************************** -* * -* Paramètres : ctx = instance d'objet GLib à traiter. * -* * -* Description : Supprime toutes les références externes. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_arm_dcontext_dispose(GArmDContext *ctx) -{ - G_OBJECT_CLASS(g_arm_dcontext_parent_class)->dispose(G_OBJECT(ctx)); - -} - - -/****************************************************************************** -* * -* Paramètres : ctx = instance d'objet GLib à traiter. * -* * -* Description : Procède à la libération totale de la mémoire. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_arm_dcontext_finalize(GArmDContext *ctx) -{ - G_OBJECT_CLASS(g_arm_dcontext_parent_class)->finalize(G_OBJECT(ctx)); - -} - - -/****************************************************************************** -* * -* Paramètres : - * -* * -* Description : Crée un contexte pour la décompilation ARM. * -* * -* Retour : Contexte mis en place. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArmDContext *g_arm_dcontext_new(void) -{ - GArmDContext *result; /* Structure à retourner */ - - result = g_object_new(G_TYPE_ARM_DCONTEXT, NULL); - - return result; - -} -#endif diff --git a/src/arch/arm/context.h b/src/arch/arm/context.h deleted file mode 100644 index 2b5402d..0000000 --- a/src/arch/arm/context.h +++ /dev/null @@ -1,85 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * context.h - prototypes pour le contexte lié à l'exécution d'un processeur - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_ARM_CONTEXT_H -#define _ARCH_ARM_CONTEXT_H - - -#include <glib-object.h> - - - -/* ------------------------ MANIPULATION GLOBALE DU CONTEXTE ------------------------ */ - - -#define G_TYPE_ARM_CONTEXT g_arm_context_get_type() -#define G_ARM_CONTEXT(obj) (G_TYPE_CHECK_INSTANCE_CAST((obj), g_arm_context_get_type(), GArmContext)) -#define G_IS_ARM_CONTEXT(obj) (G_TYPE_CHECK_INSTANCE_TYPE((obj), g_arm_context_get_type())) -#define G_ARM_CONTEXT_CLASS(klass) (G_TYPE_CHECK_CLASS_CAST((klass), G_TYPE_ARM_CONTEXT, GGArmContextClass)) -#define G_IS_ARM_CONTEXT_CLASS(klass) (G_TYPE_CHECK_CLASS_TYPE((klass), G_TYPE_ARM_CONTEXT)) -#define G_ARM_CONTEXT_GET_CLASS(obj) (G_TYPE_INSTANCE_GET_CLASS((obj), G_TYPE_ARM_CONTEXT, GGArmContextClass)) - - -/* Définition d'un contexte pour processeur ARM (instance) */ -typedef struct _GArmContext GArmContext; - -/* Définition d'un contexte pour processeur ARM (classe) */ -typedef struct _GArmContextClass GArmContextClass; - - -/* Indique le type définit par la GLib pour le contexte de processeur ARM. */ -GType g_arm_context_get_type(void); - -/* Crée un contexte pour l'exécution du processeur ARM. */ -GArmContext *g_arm_context_new(void); - - - -/* ------------------------- CONTEXTE POUR LA DECOMPILATION ------------------------- */ - -#if 0 -#define G_TYPE_ARM_DCONTEXT g_arm_dcontext_get_type() -#define G_ARM_DCONTEXT(obj) (G_TYPE_CHECK_INSTANCE_CAST((obj), g_arm_dcontext_get_type(), GArmDContext)) -#define G_IS_ARM_DCONTEXT(obj) (G_TYPE_CHECK_INSTANCE_TYPE((obj), g_arm_dcontext_get_type())) -#define G_ARM_DCONTEXT_CLASS(klass) (G_TYPE_CHECK_CLASS_CAST((klass), G_TYPE_ARM_DCONTEXT, GGArmDContextClass)) -#define G_IS_ARM_DCONTEXT_CLASS(klass) (G_TYPE_CHECK_CLASS_TYPE((klass), G_TYPE_ARM_DCONTEXT)) -#define G_ARM_DCONTEXT_GET_CLASS(obj) (G_TYPE_INSTANCE_GET_CLASS((obj), G_TYPE_ARM_DCONTEXT, GGArmDContextClass)) - - -/* Définition d'un contexte pour décompilation ARM (instance) */ -typedef struct _GArmDContext GArmDContext; - -/* Définition d'un contexte pour décompilation ARM (classe) */ -typedef struct _GArmDContextClass GArmDContextClass; - - -/* Indique le type définit par la GLib pour le contexte de décompilation ARM. */ -GType g_arm_dcontext_get_type(void); - -/* Crée un contexte pour la décompilation ARM. */ -GArmDContext *g_arm_dcontext_new(void); -#endif - - - -#endif /* _ARCH_ARM_CONTEXT_H */ diff --git a/src/arch/arm/instruction-int.h b/src/arch/arm/instruction-int.h deleted file mode 100644 index 408b44c..0000000 --- a/src/arch/arm/instruction-int.h +++ /dev/null @@ -1,55 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * instruction-int.h - prototypes pour la définition générique interne des instructions ARM - * - * Copyright (C) 2013-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_ARM_INSTRUCTION_INT_H -#define _ARCH_ARM_INSTRUCTION_INT_H - - -#include "instruction.h" -#include "../instruction-int.h" - - - -/* Définition générique d'une instruction d'architecture ARM (instance) */ -struct _GArmInstruction -{ - GArchInstruction parent; /* A laisser en premier */ - - const char *keyword; /* Nom clef de l'instruction */ - char *suffix; /* Complément au nom affiché */ - char *cached_keyword; /* Désignation complète */ - - ArmCondCode cond; /* Condition d'exécution */ - -}; - -/* Définition générique d'une instruction d'architecture ARM (classe) */ -struct _GArmInstructionClass -{ - GArchInstructionClass parent; /* A laisser en premier */ - -}; - - - -#endif /* _ARCH_ARM_INSTRUCTION_INT_H */ diff --git a/src/arch/arm/instruction.c b/src/arch/arm/instruction.c deleted file mode 100644 index bcd0f74..0000000 --- a/src/arch/arm/instruction.c +++ /dev/null @@ -1,272 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * instruction.c - gestion des instructions de la ARM - * - * Copyright (C) 2013-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#include "instruction.h" - - -#include <malloc.h> -#include <string.h> - - -#include "instruction-int.h" -#include "../../common/extstr.h" - - - -/* Initialise la classe des instructions ARM. */ -static void g_arm_instruction_class_init(GArmInstructionClass *); - -/* Initialise une instance de instruction ARM. */ -static void g_arm_instruction_init(GArmInstruction *); - -/* Supprime toutes les références externes. */ -static void g_arm_instruction_dispose(GArmInstruction *); - -/* Procède à la libération totale de la mémoire. */ -static void g_arm_instruction_finalize(GArmInstruction *); - -/* Fournit le nom humain de l'instruction manipulée. */ -static const char *g_arm_instruction_get_keyword(GArmInstruction *, AsmSyntax); - - - -/* Indique le type défini pour une représentation d'une instruction ARM. */ -G_DEFINE_TYPE(GArmInstruction, g_arm_instruction, G_TYPE_ARCH_INSTRUCTION); - - -/****************************************************************************** -* * -* Paramètres : klass = classe à initialiser. * -* * -* Description : Initialise la classe des instructions ARM. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_arm_instruction_class_init(GArmInstructionClass *klass) -{ - GObjectClass *object_class; /* Autre version de la classe */ - GArchInstructionClass *instr; /* Encore une autre vision... */ - - object_class = G_OBJECT_CLASS(klass); - instr = G_ARCH_INSTRUCTION_CLASS(klass); - - object_class->dispose = (GObjectFinalizeFunc/* ! */)g_arm_instruction_dispose; - object_class->finalize = (GObjectFinalizeFunc)g_arm_instruction_finalize; - - instr->get_keyword = (get_instruction_keyword_fc)g_arm_instruction_get_keyword; - -} - - -/****************************************************************************** -* * -* Paramètres : instr = instance à initialiser. * -* * -* Description : Initialise une instance d'instruction ARM. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_arm_instruction_init(GArmInstruction *instr) -{ - instr->cond = ACC_AL; - -} - - -/****************************************************************************** -* * -* Paramètres : instr = instance d'objet GLib à traiter. * -* * -* Description : Supprime toutes les références externes. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_arm_instruction_dispose(GArmInstruction *instr) -{ - G_OBJECT_CLASS(g_arm_instruction_parent_class)->dispose(G_OBJECT(instr)); - -} - - -/****************************************************************************** -* * -* Paramètres : instr = instance d'objet GLib à traiter. * -* * -* Description : Procède à la libération totale de la mémoire. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_arm_instruction_finalize(GArmInstruction *instr) -{ - if (instr->suffix != NULL) - free(instr->suffix); - - if (instr->cached_keyword != NULL) - free(instr->cached_keyword); - - G_OBJECT_CLASS(g_arm_instruction_parent_class)->finalize(G_OBJECT(instr)); - -} - - -/****************************************************************************** -* * -* Paramètres : instr = instruction quelconque à modifier. * -* suffix = chaîne de caractères fournie en complément. * -* * -* Description : Etend la désignation d'un nom d'instruction. * -* * -* Retour : true. * -* * -* Remarques : - * -* * -******************************************************************************/ - -bool g_arm_instruction_extend_keyword(GArmInstruction *instr, const char *suffix) -{ - instr->suffix = stradd(instr->suffix, suffix); - - if (instr->cached_keyword != NULL) - { - free(instr->cached_keyword); - instr->cached_keyword = NULL; - } - - return true; - -} - - -/****************************************************************************** -* * -* Paramètres : instr = instruction d'assemblage à consulter. * -* syntax = type de représentation demandée. * -* * -* Description : Fournit le nom humain de l'instruction manipulée. * -* * -* Retour : Mot clef de bas niveau. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static const char *g_arm_instruction_get_keyword(GArmInstruction *instr, AsmSyntax syntax) -{ - if (instr->cached_keyword == NULL) - { - instr->cached_keyword = strdup(instr->keyword); - - if (instr->suffix != NULL) - instr->cached_keyword = stradd(instr->cached_keyword, instr->suffix); - - } - - return instr->cached_keyword; - -} - - -/****************************************************************************** -* * -* Paramètres : instr = instruction ARM à mettre à jour. * -* cond = condition d'exécution de l'instruction. * -* * -* Description : Définit les conditions d'exécution d'une instruction ARM. * -* * -* Retour : Bilan de l'opération. * -* * -* Remarques : - * -* * -******************************************************************************/ - -bool g_arm_instruction_set_cond(GArmInstruction *instr, ArmCondCode cond) -{ - bool result; /* Bilan à retourner */ - const char *suffix; /* Eventuelle marque à ajouter */ - - instr->cond = cond; - - switch (cond) - { - case ACC_EQ: suffix = "eq"; break; - case ACC_NE: suffix = "ne"; break; - case ACC_HS: suffix = "hs"; break; - case ACC_LO: suffix = "lo"; break; - case ACC_MI: suffix = "mi"; break; - case ACC_PL: suffix = "pl"; break; - case ACC_VS: suffix = "vs"; break; - case ACC_VC: suffix = "vc"; break; - case ACC_HI: suffix = "hi"; break; - case ACC_LS: suffix = "ls"; break; - case ACC_GE: suffix = "ge"; break; - case ACC_LT: suffix = "lt"; break; - case ACC_GT: suffix = "gt"; break; - case ACC_LE: suffix = "le"; break; - case ACC_AL: suffix = NULL; break; - case ACC_NV: suffix = "nv"; break; - } - - if (suffix != NULL) - result = g_arm_instruction_extend_keyword(instr, suffix); - - else - result = true; - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : instr = instruction ARM à consulter. * -* * -* Description : Indique les conditions d'exécution d'une instruction ARM. * -* * -* Retour : Condition d'exécution de l'instruction. * -* * -* Remarques : - * -* * -******************************************************************************/ - -ArmCondCode g_arm_instruction_get_cond(const GArmInstruction *instr) -{ - return instr->cond; - -} diff --git a/src/arch/arm/instruction.h b/src/arch/arm/instruction.h deleted file mode 100644 index 8b0110d..0000000 --- a/src/arch/arm/instruction.h +++ /dev/null @@ -1,67 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * instruction.h - prototypes pour la gestion des instructions ARM - * - * Copyright (C) 2013-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_ARM_INSTRUCTION_H -#define _ARCH_ARM_INSTRUCTION_H - - -#include <glib-object.h> -#include <stdbool.h> -#include <stdint.h> - - -#include "cond.h" -#include "../instruction.h" - - - -#define G_TYPE_ARM_INSTRUCTION g_arm_instruction_get_type() -#define G_ARM_INSTRUCTION(obj) (G_TYPE_CHECK_INSTANCE_CAST((obj), g_arm_instruction_get_type(), GArmInstruction)) -#define G_IS_ARM_INSTRUCTION(obj) (G_TYPE_CHECK_INSTANCE_TYPE((obj), g_arm_instruction_get_type())) -#define G_ARM_INSTRUCTION_CLASS(klass) (G_TYPE_CHECK_CLASS_CAST((klass), G_TYPE_ARM_INSTRUCTION, GArmInstructionClass)) -#define G_IS_ARM_INSTRUCTION_CLASS(klass) (G_TYPE_CHECK_CLASS_TYPE((klass), G_TYPE_ARM_INSTRUCTION)) -#define G_ARM_INSTRUCTION_GET_CLASS(obj) (G_TYPE_INSTANCE_GET_CLASS((obj), G_TYPE_ARM_INSTRUCTION, GArmInstructionClass)) - - -/* Définition d'une instruction d'architecture ARM (instance) */ -typedef struct _GArmInstruction GArmInstruction; - -/* Définition d'une instruction d'architecture ARM (classe) */ -typedef struct _GArmInstructionClass GArmInstructionClass; - - -/* Indique le type défini pour une représentation d'une instruction ARM. */ -GType g_arm_instruction_get_type(void); - -/* Etend la désignation d'un nom d'instruction. */ -bool g_arm_instruction_extend_keyword(GArmInstruction *, const char *); - -/* Définit les conditions d'exécution d'une instruction ARM. */ -bool g_arm_instruction_set_cond(GArmInstruction *, ArmCondCode); - -/* Indique les conditions d'exécution d'une instruction ARM. */ -ArmCondCode g_arm_instruction_get_cond(const GArmInstruction *); - - - -#endif /* _ARCH_ARM_INSTRUCTION_H */ diff --git a/src/arch/arm/link.c b/src/arch/arm/link.c deleted file mode 100644 index 57f0f98..0000000 --- a/src/arch/arm/link.c +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * link.c - édition des liens après la phase de désassemblage ARM - * - * Copyright (C) 2015-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#include "link.h" - - -#include "cond.h" -#include "instruction.h" -#include "../link.h" - - - -/****************************************************************************** -* * -* Paramètres : instr = instruction ARM à traiter. * -* proc = représentation de l'architecture utilisée. * -* context = contexte associé à la phase de désassemblage. * -* format = acès aux données du binaire d'origine. * -* * -* Description : Etablit un lien conditionnel selon une instruction donnée. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -void handle_arm_conditional_branch_as_link(GArchInstruction *instr, GArchProcessor *proc, GProcContext *context, GExeFormat *format) -{ - switch (g_arm_instruction_get_cond(G_ARM_INSTRUCTION(instr))) - { - case ACC_AL: - handle_jump_as_link(instr, proc, context, format); - break; - - case ACC_NV: - break; - - default: - handle_branch_if_true_as_link(instr, proc, context, format); - break; - - } - -} diff --git a/src/arch/arm/link.h b/src/arch/arm/link.h deleted file mode 100644 index 216277d..0000000 --- a/src/arch/arm/link.h +++ /dev/null @@ -1,38 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * link.h - prototypes pour l'édition des liens après la phase de désassemblage ARM - * - * Copyright (C) 2015-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_ARM_LINK_H -#define _ARCH_ARM_LINK_H - - -#include "../instruction.h" -#include "../processor.h" - - - -/* Etablit un lien conditionnel selon une instruction donnée. */ -void handle_arm_conditional_branch_as_link(GArchInstruction *, GArchProcessor *, GProcContext *, GExeFormat *); - - - -#endif /* _ARCH_ARM_LINK_H */ diff --git a/src/arch/arm/processor-int.h b/src/arch/arm/processor-int.h deleted file mode 100644 index 45d4380..0000000 --- a/src/arch/arm/processor-int.h +++ /dev/null @@ -1,50 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * instruction-int.h - prototypes pour la définition générique interne des processeurs ARM - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_ARM_PROCESSOR_INT_H -#define _ARCH_ARM_PROCESSOR_INT_H - - -#include "processor.h" -#include "../processor-int.h" - - - -/* Définition du processeur ARM (instance) */ -struct _GArmProcessor -{ - GArchProcessor parent; /* Instance parente */ - -}; - - -/* Définition du processeur ARM (classe) */ -struct _GArmProcessorClass -{ - GArchProcessorClass parent; /* Classe parente */ - -}; - - - -#endif /* _ARCH_ARM_PROCESSOR_INT_H */ diff --git a/src/arch/arm/processor.c b/src/arch/arm/processor.c deleted file mode 100644 index 4906799..0000000 --- a/src/arch/arm/processor.c +++ /dev/null @@ -1,126 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * processor.c - manipulation du processeur ARM - * - * Copyright (C) 2010-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#include "processor.h" - - -#include "processor-int.h" - - - -/* Initialise la classe des registres ARM. */ -static void g_arm_processor_class_init(GArmProcessorClass *); - -/* Initialise une instance de registre ARM. */ -static void g_arm_processor_init(GArmProcessor *); - -/* Supprime toutes les références externes. */ -static void g_arm_processor_dispose(GArmProcessor *); - -/* Procède à la libération totale de la mémoire. */ -static void g_arm_processor_finalize(GArmProcessor *); - - - -/* Indique le type défini par la GLib pour le processeur ARM. */ -G_DEFINE_TYPE(GArmProcessor, g_arm_processor, G_TYPE_ARCH_PROCESSOR); - - -/****************************************************************************** -* * -* Paramètres : klass = classe à initialiser. * -* * -* Description : Initialise la classe des processeurs ARM. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_arm_processor_class_init(GArmProcessorClass *klass) -{ - GObjectClass *object_class; /* Autre version de la classe */ - - object_class = G_OBJECT_CLASS(klass); - - object_class->dispose = (GObjectFinalizeFunc/* ! */)g_arm_processor_dispose; - object_class->finalize = (GObjectFinalizeFunc)g_arm_processor_finalize; - -} - - -/****************************************************************************** -* * -* Paramètres : proc = instance à initialiser. * -* * -* Description : Initialise une instance de processeur ARM. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_arm_processor_init(GArmProcessor *proc) -{ - -} - - -/****************************************************************************** -* * -* Paramètres : proc = instance d'objet GLib à traiter. * -* * -* Description : Supprime toutes les références externes. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_arm_processor_dispose(GArmProcessor *proc) -{ - G_OBJECT_CLASS(g_arm_processor_parent_class)->dispose(G_OBJECT(proc)); - -} - - -/****************************************************************************** -* * -* Paramètres : proc = instance d'objet GLib à traiter. * -* * -* Description : Procède à la libération totale de la mémoire. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_arm_processor_finalize(GArmProcessor *proc) -{ - G_OBJECT_CLASS(g_arm_processor_parent_class)->finalize(G_OBJECT(proc)); - -} diff --git a/src/arch/arm/processor.h b/src/arch/arm/processor.h deleted file mode 100644 index 7f65def..0000000 --- a/src/arch/arm/processor.h +++ /dev/null @@ -1,53 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * processor.h - prototypes pour la manipulation du processeur ARM - * - * Copyright (C) 2010-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_ARM_PROCESSOR_H -#define _ARCH_ARM_PROCESSOR_H - - -#include <glib-object.h> -#include <stdint.h> - - - -#define G_TYPE_ARM_PROCESSOR g_arm_processor_get_type() -#define G_ARM_PROCESSOR(obj) (G_TYPE_CHECK_INSTANCE_CAST((obj), g_arm_processor_get_type(), GArmProcessor)) -#define G_IS_ARM_PROCESSOR(obj) (G_TYPE_CHECK_INSTANCE_TYPE((obj), g_arm_processor_get_type())) -#define G_ARM_PROCESSOR_CLASS(klass) (G_TYPE_CHECK_CLASS_CAST((klass), G_TYPE_ARM_PROCESSOR, GArmProcessorClass)) -#define G_IS_ARM_PROCESSOR_CLASS(klass) (G_TYPE_CHECK_CLASS_TYPE((klass), G_TYPE_ARM_PROCESSOR)) -#define G_ARM_PROCESSOR_GET_CLASS(obj) (G_TYPE_INSTANCE_GET_CLASS((obj), G_TYPE_ARM_PROCESSOR, GArmProcessorClass)) - - -/* Définition du processeur ARM (instance) */ -typedef struct _GArmProcessor GArmProcessor; - -/* Définition du processeur ARM (classe) */ -typedef struct _GArmProcessorClass GArmProcessorClass; - - -/* Indique le type défini par la GLib pour le processeur ARM. */ -GType g_arm_processor_get_type(void); - - - -#endif /* _ARCH_ARM_PROCESSOR_H */ diff --git a/src/arch/arm/register-int.h b/src/arch/arm/register-int.h deleted file mode 100644 index ec80bdd..0000000 --- a/src/arch/arm/register-int.h +++ /dev/null @@ -1,56 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * register-int.h - définitions internes pour la représentation d'un registre ARM - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_ARM_REGISTER_INT_H -#define _ARCH_ARM_REGISTER_INT_H - - - -#include "register.h" -#include "../register-int.h" - - - -#define MAX_REGNAME_LEN 8 - - -/* Représentation d'un registre ARM (instance) */ -struct _GArmRegister -{ - GArchRegister parent; /* A laisser en premier */ - - uint8_t index; /* Indice du registre */ - -}; - - -/* Représentation d'un registre ARM (classe) */ -struct _GArmRegisterClass -{ - GArchRegisterClass parent; /* A laisser en premier */ - -}; - - - -#endif /* _ARCH_ARM_REGISTER_INT_H */ diff --git a/src/arch/arm/register.c b/src/arch/arm/register.c deleted file mode 100644 index c351f12..0000000 --- a/src/arch/arm/register.c +++ /dev/null @@ -1,200 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * registers.c - aides auxiliaires relatives aux registres ARM - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#include "register.h" - - -#include "register-int.h" -#include "../../common/sort.h" - - - -/* Initialise la classe des registres ARM. */ -static void g_arm_register_class_init(GArmRegisterClass *); - -/* Initialise une instance de registre ARM. */ -static void g_arm_register_init(GArmRegister *); - -/* Supprime toutes les références externes. */ -static void g_arm_register_dispose(GArmRegister *); - -/* Procède à la libération totale de la mémoire. */ -static void g_arm_register_finalize(GArmRegister *); - -/* Produit une empreinte à partir d'un registre. */ -static guint g_arm_register_hash(const GArmRegister *); - -/* Compare un registre avec un autre. */ -static int g_arm_register_compare(const GArmRegister *, const GArmRegister *); - - - -/* Indique le type défini pour une représentation d'un registre ARM. */ -G_DEFINE_TYPE(GArmRegister, g_arm_register, G_TYPE_ARCH_REGISTER); - - -/****************************************************************************** -* * -* Paramètres : klass = classe à initialiser. * -* * -* Description : Initialise la classe des registres Arm. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_arm_register_class_init(GArmRegisterClass *klass) -{ - GObjectClass *object_class; /* Autre version de la classe */ - GArchRegisterClass *register_class; /* Classe de haut niveau */ - - object_class = G_OBJECT_CLASS(klass); - register_class = G_ARCH_REGISTER_CLASS(klass); - - object_class->dispose = (GObjectFinalizeFunc/* ! */)g_arm_register_dispose; - object_class->finalize = (GObjectFinalizeFunc)g_arm_register_finalize; - - register_class->hash = (reg_hash_fc)g_arm_register_hash; - register_class->compare = (reg_compare_fc)g_arm_register_compare; - -} - - -/****************************************************************************** -* * -* Paramètres : reg = instance à initialiser. * -* * -* Description : Initialise une instance de registre ARM. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_arm_register_init(GArmRegister *reg) -{ - -} - - -/****************************************************************************** -* * -* Paramètres : reg = instance d'objet GLib à traiter. * -* * -* Description : Supprime toutes les références externes. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_arm_register_dispose(GArmRegister *reg) -{ - G_OBJECT_CLASS(g_arm_register_parent_class)->dispose(G_OBJECT(reg)); - -} - - -/****************************************************************************** -* * -* Paramètres : reg = instance d'objet GLib à traiter. * -* * -* Description : Procède à la libération totale de la mémoire. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_arm_register_finalize(GArmRegister *reg) -{ - G_OBJECT_CLASS(g_arm_register_parent_class)->finalize(G_OBJECT(reg)); - -} - - -/****************************************************************************** -* * -* Paramètres : reg = registre à consulter. * -* * -* Description : Fournit l'indice d'un registre ARM. * -* * -* Retour : Inditifiant représentant le registre. * -* * -* Remarques : - * -* * -******************************************************************************/ - -uint8_t g_arm_register_get_index(const GArmRegister *reg) -{ - return reg->index; - -} - - -/****************************************************************************** -* * -* Paramètres : reg = opérande à consulter pour le calcul. * -* * -* Description : Produit une empreinte à partir d'un registre. * -* * -* Retour : Bilan de l'opération. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static guint g_arm_register_hash(const GArmRegister *reg) -{ - return reg->index; - -} - - -/****************************************************************************** -* * -* Paramètres : a = premier opérande à consulter. * -* b = second opérande à consulter. * -* * -* Description : Compare un registre avec un autre. * -* * -* Retour : Bilan de la comparaison. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static int g_arm_register_compare(const GArmRegister *a, const GArmRegister *b) -{ - int result; /* Bilan à retourner */ - - result = sort_unsigned_long(b->index, b->index); - - return result; - -} diff --git a/src/arch/arm/register.h b/src/arch/arm/register.h deleted file mode 100644 index cb4e492..0000000 --- a/src/arch/arm/register.h +++ /dev/null @@ -1,56 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * registers.h - prototypes pour les aides auxiliaires relatives aux registres ARM - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_ARM_REGISTER_H -#define _ARCH_ARM_REGISTER_H - - -#include <glib-object.h> -#include <stdint.h> - - - -#define G_TYPE_ARM_REGISTER g_arm_register_get_type() -#define G_ARM_REGISTER(obj) (G_TYPE_CHECK_INSTANCE_CAST((obj), g_arm_register_get_type(), GArmRegister)) -#define G_IS_ARM_REGISTER(obj) (G_TYPE_CHECK_INSTANCE_TYPE((obj), g_arm_register_get_type())) -#define G_ARM_REGISTER_CLASS(klass) (G_TYPE_CHECK_CLASS_CAST((klass), G_TYPE_ARM_REGISTER, GArmRegisterClass)) -#define G_IS_ARM_REGISTER_CLASS(klass) (G_TYPE_CHECK_CLASS_TYPE((klass), G_TYPE_ARM_REGISTER)) -#define G_ARM_REGISTER_GET_CLASS(obj) (G_TYPE_INSTANCE_GET_CLASS((obj), G_TYPE_ARM_REGISTER, GArmRegisterClass)) - - -/* Représentation d'un registre ARM (instance) */ -typedef struct _GArmRegister GArmRegister; - -/* Représentation d'un registre ARM (classe) */ -typedef struct _GArmRegisterClass GArmRegisterClass; - - -/* Indique le type défini pour une représentation d'un registre ARM. */ -GType g_arm_register_get_type(void); - -/* Fournit l'indice d'un registre ARM. */ -uint8_t g_arm_register_get_index(const GArmRegister *); - - - -#endif /* _ARCH_ARM_REGISTER_H */ diff --git a/src/arch/arm/v7/Makefile.am b/src/arch/arm/v7/Makefile.am deleted file mode 100644 index 339bc29..0000000 --- a/src/arch/arm/v7/Makefile.am +++ /dev/null @@ -1,33 +0,0 @@ - -noinst_LTLIBRARIES = libarcharmv7.la - -libarcharmv7_la_SOURCES = \ - arm.h arm.c \ - context.h context.c \ - core.h core.c \ - cregister.h cregister.c \ - fetch.h fetch.c \ - helpers.h helpers.c \ - instruction.h instruction.c \ - link.h link.c \ - post.h post.c \ - processor.h processor.c \ - pseudo.h pseudo.c \ - register.h register.c \ - simd.h simd.c \ - thumb_16.h thumb_16.c \ - thumb_32.h thumb_32.c - -libarcharmv7_la_LIBADD = \ - opcodes/libarcharmv7opcodes.la \ - operands/libarcharmv7operands.la - -libarcharmv7_la_CFLAGS = $(AM_CFLAGS) - - -AM_CPPFLAGS = $(LIBGTK_CFLAGS) $(LIBXML_CFLAGS) - -AM_CFLAGS = $(DEBUG_CFLAGS) $(WARNING_FLAGS) $(COMPLIANCE_FLAGS) - - -SUBDIRS = opdefs opcodes operands diff --git a/src/arch/arm/v7/arm.c b/src/arch/arm/v7/arm.c deleted file mode 100644 index 55593af..0000000 --- a/src/arch/arm/v7/arm.c +++ /dev/null @@ -1,2269 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * arm.c - désassemblage des instructions ARMv7 - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#include "arm.h" - - -#include <stdint.h> - - -#include "simd.h" -#include "opcodes/arm_opcodes.h" -#include "opcodes/opcodes_tmp_arm.h" -#include "../../undefined.h" -#include "../../../common/bconst.h" - - - -/* Désassemble une instruction ARMv7 de données ou autre. */ -static GArchInstruction *process_armv7_arm_data_processing_and_miscellaneous_instructions(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A5.2.1. */ -static GArchInstruction *process_armv7_arm_data_processing_register(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A5.2.2. */ -static GArchInstruction *process_armv7_arm_data_processing_register_shifted_register(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A5.2.3. */ -static GArchInstruction *process_armv7_arm_data_processing_immediate(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A5.2.5. */ -static GArchInstruction *process_armv7_arm_multiply_and_multiply_accumulate(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A5.2.6. */ -static GArchInstruction *process_armv7_arm_saturating_addition_and_subtraction(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A5.2.7. */ -static GArchInstruction *process_armv7_arm_halfword_multiply_and_multiply_accumulate(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A5.2.8. */ -static GArchInstruction *process_armv7_arm_extra_load_store_instructions(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A5.2.9. */ -static GArchInstruction *process_armv7_arm_extra_load_store_instructions_unprivileged(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A5.2.10. */ -static GArchInstruction *process_armv7_arm_synchronization_primitives(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A5.2.11. */ -static GArchInstruction *process_armv7_arm_msr_immediate_and_hints(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A5.2.12. */ -static GArchInstruction *process_armv7_arm_miscellaneous_instructions(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A5.3. */ -static GArchInstruction *process_armv7_arm_load_store_word_and_unsigned_byte(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A5.4. */ -static GArchInstruction *process_armv7_arm_media_instructions(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A5.4.1. */ -static GArchInstruction *process_armv7_arm_parallel_addition_and_subtraction_signed(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A5.4.2. */ -static GArchInstruction *process_armv7_arm_parallel_addition_and_subtraction_unsigned(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A5.4.3. */ -static GArchInstruction *process_armv7_arm_packing_unpacking_saturation_and_reversal(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A5.4.4. */ -static GArchInstruction *process_armv7_arm_signed_multiply_signed_and_unsigned_divide(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A5.5. */ -static GArchInstruction *process_armv7_arm_branch_branch_with_link_and_block_data_transfer(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A5.6. */ -static GArchInstruction *process_armv7_arm_coprocessor_instructions_and_supervisor_call(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A5.7. */ -static GArchInstruction *process_armv7_arm_unconditional_instructions(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A5.7.1. */ -static GArchInstruction *process_armv7_arm_memory_hints_advanced_simd_instructions_and_miscellaneous_instructions(uint32_t); - - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A5.1. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArchInstruction *process_armv7_arm_instruction_set_encoding(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t cond; /* Champ 'cond' à retrouver */ - uint32_t op1; /* Champ 'op1' à retrouver */ - uint32_t op; /* Champ 'op' à retrouver */ - - /** - * Suit les directives de : - * § A5.1 ARM instruction set encoding - */ - - result = NULL; - - cond = (raw >> 28) & 0xf; - op1 = (raw >> 25) & 0x7; - op = (raw >> 4) & 0x1; - - if (cond != b1111) - { - if ((op1 & b110) == b000) - result = process_armv7_arm_data_processing_and_miscellaneous_instructions(raw); - - else if (op1 == b010) - result = process_armv7_arm_load_store_word_and_unsigned_byte(raw); - - else if (op1 == b011) - { - if (op == b0) - result = process_armv7_arm_load_store_word_and_unsigned_byte(raw); - - else/* if (op == b1)*/ - result = process_armv7_arm_media_instructions(raw); - - } - - else if ((op1 & b110) == b100) - result = process_armv7_arm_branch_branch_with_link_and_block_data_transfer(raw); - - else if ((op1 & b110) == b110) - result = process_armv7_arm_coprocessor_instructions_and_supervisor_call(raw); - - } - - else /* if (cond == b1111) */ - result = process_armv7_arm_unconditional_instructions(raw); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 de données ou autre. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_arm_data_processing_and_miscellaneous_instructions(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à retourner */ - uint32_t op; /* Champ 'op' à retrouver */ - uint32_t op1; /* Champ 'op1' à retrouver */ - uint32_t op2; /* Champ 'op2' à retrouver */ - - /** - * Suit les directives de : - * § A5.2 Data-processing and miscellaneous instructions - */ - - result = NULL; - - op = (raw >> 25) & 0x1; - op1 = (raw >> 20) & 0x1f; - op2 = (raw >> 4) & 0xf; - - if (op == b0) - { - if ((op1 & b11001) != b10000) - { - if ((op2 & b0001) == b0000) - result = process_armv7_arm_data_processing_register(raw); - - else if ((op2 & b1001) == b0001) - result = process_armv7_arm_data_processing_register_shifted_register(raw); - - if (result != NULL) goto padpami_found; - - } - - else /* if ((op1 & b11001) == b10000) */ - { - if ((op2 & b1000) == b0000) - result = process_armv7_arm_miscellaneous_instructions(raw); - - else if ((op2 & b1001) == b1000) - result = process_armv7_arm_halfword_multiply_and_multiply_accumulate(raw); - - if (result != NULL) goto padpami_found; - - } - - if ((op1 & b10000) == b00000) - { - if (op2 == b1001) - result = process_armv7_arm_multiply_and_multiply_accumulate(raw); - - if (result != NULL) goto padpami_found; - - } - - if ((op1 & b10000) == b10000) - { - if (op2 == b1001) - result = process_armv7_arm_synchronization_primitives(raw); - - if (result != NULL) goto padpami_found; - - } - - if ((op1 & b10010) != b00010) - { - if (op2 == b1011) - result = process_armv7_arm_extra_load_store_instructions(raw); - - else if ((op2 & b1101) == b1101) - result = process_armv7_arm_extra_load_store_instructions(raw); - - if (result != NULL) goto padpami_found; - - } - - else /* if ((op1 & b10010) != b00010) */ - { - if (op2 == b1011) - result = process_armv7_arm_extra_load_store_instructions_unprivileged(raw); - - else if ((op2 & b1101) == b1101) - result = process_armv7_arm_extra_load_store_instructions(raw); - - if (result != NULL) goto padpami_found; - - } - - } - - else - { - if ((op1 & b11001) != b10000) - result = process_armv7_arm_data_processing_immediate(raw); - - else if (op1 == b10000) - result = armv7_read_arm_instr_mov_immediate(raw); - - else if (op1 == b10100) - result = armv7_read_arm_instr_movt(raw); - - else if ((op1 & b11011) == b10010) - result = process_armv7_arm_msr_immediate_and_hints(raw); - - } - - padpami_found: - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A5.2.1. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_arm_data_processing_register(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à retourner */ - uint32_t op; /* Champ 'op' à retrouver */ - uint32_t imm5; /* Champ 'imm5' à retrouver */ - uint32_t op2; /* Champ 'op2' à retrouver */ - - /** - * Suit les directives de : - * § A5.2.1 Data-processing (register) - */ - - if ((raw & 0x0e000010) != 0x00000000) return NULL; - - result = NULL; - - op = (raw >> 20) & 0x1f; - imm5 = (raw >> 7) & 0x1f; - op2 = (raw >> 5) & 0x3; - - if ((op & b11110) == b00000) - result = armv7_read_arm_instr_and_register(raw); - - else if ((op & b11110) == b00010) - result = armv7_read_arm_instr_eor_register(raw); - - else if ((op & b11110) == b00100) - result = armv7_read_arm_instr_sub_register(raw); - - else if ((op & b11110) == b00110) - result = armv7_read_arm_instr_rsb_register(raw); - - else if ((op & b11110) == b01000) - result = armv7_read_arm_instr_add_register_arm(raw); - - else if ((op & b11110) == b01010) - result = armv7_read_arm_instr_adc_register(raw); - - else if ((op & b11110) == b01100) - result = armv7_read_arm_instr_sbc_register(raw); - - else if ((op & b11110) == b01110) - result = armv7_read_arm_instr_rsc_register(raw); - - /* - else if ((op & b11001) == b10000) - result = process_armv7_arm_data_processing_and_miscellaneous_instructions(raw); - */ - - else if (op == b10001) - result = armv7_read_arm_instr_tst_register(raw); - - else if (op == b10011) - result = armv7_read_arm_instr_teq_register(raw); - - else if (op == b10101) - result = armv7_read_arm_instr_cmp_register(raw); - - else if (op == b10111) - result = armv7_read_arm_instr_cmn_register(raw); - - else if ((op & b11110) == b11000) - result = armv7_read_arm_instr_orr_register(raw); - - else if ((op & b11110) == b11010) - { - if (op2 == b00) - { - if (imm5 == b00000) - result = armv7_read_arm_instr_mov_register_arm(raw); - - else - result = armv7_read_arm_instr_lsl_immediate(raw); - - } - - else if (op2 == b01) - result = armv7_read_arm_instr_lsr_immediate(raw); - - else if (op2 == b10) - result = armv7_read_arm_instr_asr_immediate(raw); - - else if (op2 == b11) - { - if (imm5 == b00000) - result = armv7_read_arm_instr_rrx(raw); - - else - result = armv7_read_arm_instr_ror_immediate(raw); - - } - - } - - else if ((op & b11110) == b11100) - result = armv7_read_arm_instr_bic_register(raw); - - else if ((op & b11110) == b11110) - result = armv7_read_arm_instr_mvn_register(raw); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A5.2.2. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_arm_data_processing_register_shifted_register(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à retourner */ - uint32_t op1; /* Champ 'op1' à retrouver */ - uint32_t op2; /* Champ 'op2' à retrouver */ - - /** - * Suit les directives de : - * § A5.2.2 Data-processing (register-shifted register) - */ - - if ((raw & 0x0e000090) != 0x00000010) return NULL; - - result = NULL; - - op1 = (raw >> 20) & 0x1f; - op2 = (raw >> 5) & 0x3; - - if ((op1 & b11110) == b00000) - result = armv7_read_arm_instr_and_register_shifted_register(raw); - - else if ((op1 & b11110) == b00010) - result = armv7_read_arm_instr_eor_register_shifted_register(raw); - - else if ((op1 & b11110) == b00100) - result = armv7_read_arm_instr_sub_register_shifted_register(raw); - - else if ((op1 & b11110) == b00110) - result = armv7_read_arm_instr_rsb_register_shifted_register(raw); - - else if ((op1 & b11110) == b01000) - result = armv7_read_arm_instr_add_register_shifted_register(raw); - - else if ((op1 & b11110) == b01010) - result = armv7_read_arm_instr_adc_register_shifted_register(raw); - - else if ((op1 & b11110) == b01100) - result = armv7_read_arm_instr_sbc_register_shifted_register(raw); - - else if ((op1 & b11110) == b01110) - result = armv7_read_arm_instr_rsc_register_shifted_register(raw); - -#if 0 - else if ((op1 & b11001) == b10000) - /* See Data-processing and miscellaneous instructions on page A5-196 */ -#endif - - else if (op1 == b10001) - result = armv7_read_arm_instr_tst_register_shifted_register(raw); - - else if (op1 == b10011) - result = armv7_read_arm_instr_teq_register_shifted_register(raw); - - else if (op1 == b10101) - result = armv7_read_arm_instr_cmp_register_shifted_register(raw); - - else if (op1 == b10111) - result = armv7_read_arm_instr_cmn_register_shifted_register(raw); - - else if ((op1 & b11110) == b11000) - result = armv7_read_arm_instr_orr_register_shifted_register(raw); - - else if ((op1 & b11110) == b11010) - { - if (op2 == b00) - result = armv7_read_arm_instr_lsl_register(raw); - - else if (op2 == b01) - result = armv7_read_arm_instr_lsr_register(raw); - - else if (op2 == b10) - result = armv7_read_arm_instr_asr_register(raw); - - else if (op2 == b11) - result = armv7_read_arm_instr_ror_register(raw); - - } - - else if ((op1 & b11110) == b11100) - result = armv7_read_arm_instr_bic_register_shifted_register(raw); - - else if ((op1 & b11110) == b11110) - result = armv7_read_arm_instr_mvn_register_shifted_register(raw); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A5.2.3. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_arm_data_processing_immediate(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à retourner */ - uint32_t op; /* Champ 'op' à retrouver */ - uint32_t rn; /* Champ 'rn' à retrouver */ - - /** - * Suit les directives de : - * § A5.2.3 Data-processing (immediate) - */ - - if ((raw & 0x0e000000) != 0x02000000) return NULL; - - result = NULL; - - op = (raw >> 20) & 0x1f; - rn = (raw >> 16) & 0xf; - - if ((op & b11110) == b00000) - result = armv7_read_arm_instr_and_immediate(raw); - - else if ((op & b11110) == b00010) - result = armv7_read_arm_instr_eor_immediate(raw); - - else if ((op & b11110) == b00100) - { - if (rn == b1111) - result = armv7_read_arm_instr_adr(raw); - - else - result = armv7_read_arm_instr_sub_immediate_arm(raw); - - } - - else if ((op & b11110) == b00110) - result = armv7_read_arm_instr_rsb_immediate(raw); - - else if ((op & b11110) == b01000) - { - if (rn == b1111) - result = armv7_read_arm_instr_adr(raw); - - else - result = armv7_read_arm_instr_add_immediate_arm(raw); - - } - - else if ((op & b11110) == b01010) - result = armv7_read_arm_instr_adc_immediate(raw); - - else if ((op & b11110) == b01100) - result = armv7_read_arm_instr_sbc_immediate(raw); - - else if ((op & b11110) == b01110) - result = armv7_read_arm_instr_rsc_immediate(raw); - - /* - else if ((op & b11110) == b10000) - result = process_armv7_arm_data_processing_and_miscellaneous_instructions(raw); - */ - - else if (op == b10001) - result = armv7_read_arm_instr_tst_immediate(raw); - - else if (op == b10011) - result = armv7_read_arm_instr_teq_immediate(raw); - - else if (op == b10101) - result = armv7_read_arm_instr_cmp_immediate(raw); - - else if (op == b10111) - result = armv7_read_arm_instr_cmn_immediate(raw); - - else if ((op & b11110) == b11000) - result = armv7_read_arm_instr_orr_immediate(raw); - - else if ((op & b11110) == b11010) - result = armv7_read_arm_instr_mov_immediate(raw); - - else if ((op & b11110) == b11100) - result = armv7_read_arm_instr_bic_immediate(raw); - - else if ((op & b11110) == b11110) - result = armv7_read_arm_instr_mvn_immediate(raw); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A5.2.5. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_arm_multiply_and_multiply_accumulate(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à retourner */ - uint32_t op; /* Champ 'op' à retrouver */ - - /** - * Suit les directives de : - * § A5.2.5 Multiply and multiply accumulate - */ - - if ((raw & 0x0f0000f0) != 0x00000090) return NULL; - - result = NULL; - - op = (raw >> 20) & 0xf; - - if ((op & b1110) == b0000) - result = armv7_read_arm_instr_mul(raw); - - else if ((op & b1110) == b0010) - result = armv7_read_arm_instr_mla(raw); - - else if (op == b0100) - result = armv7_read_arm_instr_umaal(raw); - - else if (op == b0101) - result = NULL; /* Non défini */ - - else if (op == b0110) - result = armv7_read_arm_instr_mls(raw); - - else if (op == b0111) - result = NULL; /* Non défini */ - - else if ((op & b1110) == b1000) - result = armv7_read_arm_instr_umull(raw); - - else if ((op & b1110) == b1010) - result = armv7_read_arm_instr_umlal(raw); - - else if ((op & b1110) == b1100) - result = armv7_read_arm_instr_smull(raw); - - else if ((op & b1110) == b1110) - result = armv7_read_arm_instr_smlal(raw); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A5.2.6. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_arm_saturating_addition_and_subtraction(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à retourner */ - uint32_t op; /* Champ 'op' à retrouver */ - - /** - * Suit les directives de : - * § A5.2.6 Saturating addition and subtraction - */ - - if ((raw & 0x0f9000f0) != 0x01000050) return NULL; - - result = NULL; - - op = (raw >> 21) & 0x3; - - if (op == b00) - result = armv7_read_arm_instr_qadd(raw); - - else if (op == b01) - result = armv7_read_arm_instr_qsub(raw); - - else if (op == b10) - result = armv7_read_arm_instr_qdadd(raw); - - else if (op == b11) - result = armv7_read_arm_instr_qdsub(raw); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A5.2.7. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_arm_halfword_multiply_and_multiply_accumulate(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à retourner */ - uint32_t op1; /* Champ 'op1' à retrouver */ - uint32_t op; /* Champ 'op' à retrouver */ - - /** - * Suit les directives de : - * § A5.2.7 Halfword multiply and multiply accumulate - */ - - if ((raw & 0x0f900090) != 0x01000080) return NULL; - - result = NULL; - - op1 = (raw >> 21) & 0x3; - op = (raw >> 5) & 0x1; - - if (op1 == b00) - result = armv7_read_arm_instr_smlabb_smlabt_smlatb_smlatt(raw); - - else if (op1 == b01) - { - if (op == b0) - result = armv7_read_arm_instr_smlawb_smlawt(raw); - - else/* if (op == b1)*/ - result = armv7_read_arm_instr_smulwb_smulwt(raw); - - } - - else if (op1 == b10) - result = armv7_read_arm_instr_smlalbb_smlalbt_smlaltb_smlaltt(raw); - - else if (op1 == b11) - result = armv7_read_arm_instr_smulbb_smulbt_smultb_smultt(raw); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A5.2.8. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_arm_extra_load_store_instructions(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à retourner */ - uint32_t op1; /* Champ 'op1' à retrouver */ - uint32_t rn; /* Champ 'rn' à retrouver */ - uint32_t op2; /* Champ 'op2' à retrouver */ - - /** - * Suit les directives de : - * § A5.2.8 Extra load/store instructions - */ - - if ((raw & 0x0e000090) != 0x00000090) return NULL; - - result = NULL; - - op1 = (raw >> 20) & 0x1f; - rn = (raw >> 16) & 0xf; - op2 = (raw >> 5) & 0x3; - - if (op2 == b01) - { - if ((op1 & b00101) == b00000) - result = armv7_read_arm_instr_strh_register(raw); - - else if ((op1 & b00101) == b00001) - result = armv7_read_arm_instr_ldrh_register(raw); - - else if ((op1 & b00101) == b00100) - result = armv7_read_arm_instr_strh_immediate_arm(raw); - - else/* if ((op1 & b00101) == b00101)*/ - { - if (rn == b1111) - result = armv7_read_arm_instr_ldrh_literal(raw); - - else - result = armv7_read_arm_instr_ldrh_immediate_arm(raw); - - } - - } - - else if (op2 == b10) - { - if ((op1 & b00101) == b00000) - result = armv7_read_arm_instr_ldrd_register(raw); - - else if ((op1 & b00101) == b00001) - result = armv7_read_arm_instr_ldrsb_register(raw); - - else if ((op1 & b00101) == b00100) - { - if (rn == b1111) - result = armv7_read_arm_instr_ldrd_literal(raw); - - else - result = armv7_read_arm_instr_ldrd_immediate(raw); - - } - - else/* if ((op1 & b00101) == b00101)*/ - { - if (rn == b1111) - result = armv7_read_arm_instr_ldrsb_literal(raw); - - else - result = armv7_read_arm_instr_ldrsb_immediate(raw); - - } - - } - - else if (op2 == b11) - { - if ((op1 & b00101) == b00000) - result = armv7_read_arm_instr_strd_register(raw); - - else if ((op1 & b00101) == b00001) - result = armv7_read_arm_instr_ldrsh_register(raw); - - else if ((op1 & b00101) == b00100) - result = armv7_read_arm_instr_strd_immediate(raw); - - else/* if ((op1 & b00101) == b00101)*/ - { - if (rn == b1111) - result = armv7_read_arm_instr_ldrsh_literal(raw); - - else - result = armv7_read_arm_instr_ldrsh_immediate(raw); - - } - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A5.2.9. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_arm_extra_load_store_instructions_unprivileged(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à retourner */ - uint32_t op; /* Champ 'op' à retrouver */ - uint32_t op2; /* Champ 'op2' à retrouver */ - - /** - * Suit les directives de : - * § A5.2.9 Extra load/store instructions, unprivileged - */ - - if ((raw & 0x0f200090) != 0x00200090) return NULL; - - result = NULL; - - op = (raw >> 20) & 0x1; - op2 = (raw >> 5) & 0x3; - - if (op2 == b01) - { - if (op == b0) - result = armv7_read_arm_instr_strht(raw); - - else/* if (op == b1)*/ - result = armv7_read_arm_instr_ldrht(raw); - - } - - else if (op2 == b10) - { - if (op == b1) - result = armv7_read_arm_instr_ldrsbt(raw); - - } - - else if (op2 == b11) - { - if (op == b1) - result = armv7_read_arm_instr_ldrsht(raw); - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A5.2.10. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_arm_synchronization_primitives(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à retourner */ - uint32_t op; /* Champ 'op' à retrouver */ - - /** - * Suit les directives de : - * § A5.2.10 Synchronization primitives - */ - - if ((raw & 0x0f0000f0) != 0x01000090) return NULL; - - result = NULL; - - op = (raw >> 20) & 0xf; - - if ((op & b1011) == b0000) - result = armv7_read_arm_instr_swp_swpb(raw); - - else if (op == b1000) - result = armv7_read_arm_instr_strex(raw); - - else if (op == b1001) - result = armv7_read_arm_instr_ldrex(raw); - - else if (op == b1010) - result = armv7_read_arm_instr_strexd(raw); - - else if (op == b1011) - result = armv7_read_arm_instr_ldrexd(raw); - - else if (op == b1100) - result = armv7_read_arm_instr_strexb(raw); - - else if (op == b1101) - result = armv7_read_arm_instr_ldrexb(raw); - - else if (op == b1110) - result = armv7_read_arm_instr_strexh(raw); - - else if (op == b1111) - result = armv7_read_arm_instr_ldrexh(raw); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A5.2.11. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_arm_msr_immediate_and_hints(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à retourner */ - uint32_t op; /* Champ 'op' à retrouver */ - uint32_t op1; /* Champ 'op1' à retrouver */ - uint32_t op2; /* Champ 'op2' à retrouver */ - - /** - * Suit les directives de : - * § A5.2.11 MSR (immediate), and hints - */ - - if ((raw & 0x0fb00000) != 0x03200000) return NULL; - - result = NULL; - - op = (raw >> 22) & 0x1; - op1 = (raw >> 16) & 0xf; - op2 = (raw >> 0) & 0x1; - - if (op == b0) - { - if (op1 == b0000) - { - if (op2 == b00000000) - result = armv7_read_arm_instr_nop(raw); - - else if (op2 == b00000001) - result = armv7_read_arm_instr_yield(raw); - - else if (op2 == b00000010) - result = armv7_read_arm_instr_wfe(raw); - - else if (op2 == b00000011) - result = armv7_read_arm_instr_wfi(raw); - - else if (op2 == b00000100) - result = armv7_read_arm_instr_sev(raw); - - else if ((op2 & b11110000) == b11110000) - result = armv7_read_arm_instr_dbg(raw); - - } - - else if (op1 == b0100 || (op1 & b1011) == b1000) - result = armv7_read_arm_instr_msr_immediate_a8(raw); - - else if ((op1 & b0011) == b0001 || (op1 & b0010) == b0010) - result = armv7_read_arm_instr_msr_immediate_b9(raw); - - } - - else/* if (op == b1)*/ - result = armv7_read_arm_instr_msr_immediate_b9(raw); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A5.2.12. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_arm_miscellaneous_instructions(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à retourner */ - uint32_t op; /* Champ 'op' à retrouver */ - uint32_t op1; /* Champ 'op1' à retrouver */ - uint32_t b; /* Champ 'b' à retrouver */ - uint32_t op2; /* Champ 'op2' à retrouver */ - - /** - * Suit les directives de : - * § A5.2.12 Miscellaneous instructions - */ - - if ((raw & 0x0f900080) != 0x01000000) return NULL; - - result = NULL; - - op = (raw >> 21) & 0x3; - op1 = (raw >> 16) & 0xf; - b = (raw >> 9) & 0x1; - op2 = (raw >> 4) & 0x7; - - if (op2 == b000) - { - if (b == b1) - { - if ((op & b01) == b00) - result = armv7_read_arm_instr_mrs_banked_register(raw); - - else/* if ((op & b01) == b01)*/ - result = armv7_read_arm_instr_msr_banked_register(raw); - - } - else/* if (b == b0)*/ - { - if ((op & b01) == b00) - result = armv7_read_arm_instr_mrs(raw); - - else if (op == b01) - { - if ((op1 & b0011) == b0000) - result = armv7_read_arm_instr_msr_register_a8(raw); - - else if ((op1 & b0011) == b0001 || (op1 & b0010) == b0010) - result = armv7_read_arm_instr_msr_register_b9(raw); - - } - - else if (op == b11) - result = armv7_read_arm_instr_msr_register_b9(raw); - - } - - } - - else if (op2 == b001) - { - if (op == b01) - result = armv7_read_arm_instr_bx(raw); - - else if (op == b11) - result = armv7_read_arm_instr_clz(raw); - - } - - else if (op2 == b010) - { - if (op == b01) - result = armv7_read_arm_instr_bxj(raw); - - } - - else if (op2 == b011) - { - if (op == b01) - result = armv7_read_arm_instr_blx_register(raw); - - } - - else if (op2 == b101) - result = process_armv7_arm_saturating_addition_and_subtraction(raw); - - else if (op2 == b110) - { - if (op == b11) - result = armv7_read_arm_instr_eret(raw); - - } - - else if (op2 == b111) - { - if (op == b) - result = armv7_read_arm_instr_bkpt(raw); - - else if (op == b) - result = armv7_read_arm_instr_hvc(raw); - - else if (op == b) - result = armv7_read_arm_instr_smc_previously_smi(raw); - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A5.3. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_arm_load_store_word_and_unsigned_byte(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à retourner */ - uint32_t a; /* Champ 'a' à retrouver */ - uint32_t op1; /* Champ 'op1' à retrouver */ - uint32_t rn; /* Champ 'rn' à retrouver */ - uint32_t b; /* Champ 'b' à retrouver */ - - /** - * Suit les directives de : - * § A5.3 Load/store word and unsigned byte - */ - - if ((raw & 0x0c000000) != 0x04000000) return NULL; - - result = NULL; - - a = (raw >> 25) & 0x1; - op1 = (raw >> 20) & 0x1f; - rn = (raw >> 16) & 0xf; - b = (raw >> 4) & 0x1; - - if (a == b0) - { - if ((op1 & b00101) == b00000 && (op1 & b10111) != b00010) - result = armv7_read_arm_instr_str_immediate_arm(raw); - - else if ((op1 & b10111) == b00010) - result = armv7_read_arm_instr_strt(raw); - - else if ((op1 & b00101) == b00001 && (op1 & b10111) != b00011) - { - if (rn != b1111) - result = armv7_read_arm_instr_ldr_immediate_arm(raw); - else - result = armv7_read_arm_instr_ldr_literal(raw); - } - - else if ((op1 & b10111) == b00011) - result = armv7_read_arm_instr_ldrt(raw); - - else if ((op1 & b00101) == b00100 && (op1 & b10110) != b00110) - result = armv7_read_arm_instr_strb_immediate_arm(raw); - - else if ((op1 & b10110) == b00110) - result = armv7_read_arm_instr_strbt(raw); - - else if ((op1 & b00101) == b00101 && (op1 & b10111) != b00111) - { - if (rn != b1111) - result = armv7_read_arm_instr_ldrb_immediate_arm(raw); - else - result = armv7_read_arm_instr_ldrb_literal(raw); - } - - else if ((op1 & b10111) == b00111) - result = armv7_read_arm_instr_ldrbt(raw); - - } - else /*if (a == b1)*/ - { - if ((op1 & b00101) == b00000 && (op1 & b10111) != b00010 && b == b0) - result = armv7_read_arm_instr_str_register(raw); - - else if ((op1 & b10111) == b00010 && b == b0) - result = armv7_read_arm_instr_strt(raw); - - else if ((op1 & b00101) == b00001 && (op1 & b10111) != b00011 && b == b0) - result = armv7_read_arm_instr_ldr_register_arm(raw); - - else if ((op1 & b10111) == b00011 && b == b0) - result = armv7_read_arm_instr_ldrt(raw); - - else if ((op1 & b00101) == b00100 && (op1 & b10110) != b00110 && b == b0) - result = armv7_read_arm_instr_strb_register(raw); - - else if ((op1 & b10110) == b00110 && b == b0) - result = armv7_read_arm_instr_strbt(raw); - - else if ((op1 & b00101) == b00101 && (op1 & b10111) != b00111 && b == b0) - result = armv7_read_arm_instr_ldrb_register(raw); - - else if ((op1 & b10111) == b00111 && b == b0) - result = armv7_read_arm_instr_ldrbt(raw); - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A5.4. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_arm_media_instructions(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à retourner */ - uint32_t cond; /* Champ 'cond' à retrouver */ - uint32_t op1; /* Champ 'op1' à retrouver */ - uint32_t rd; /* Champ 'rd' à retrouver */ - uint32_t op2; /* Champ 'op2' à retrouver */ - uint32_t rn; /* Champ 'rn' à retrouver */ - - /** - * Suit les directives de : - * § A5.4 Media instructions - */ - - if ((raw & 0x0e000010) != 0x06000010) return NULL; - - result = NULL; - - cond = (raw >> 28) & 0xf; - op1 = (raw >> 20) & 0x1f; - rd = (raw >> 12) & 0xf; - op2 = (raw >> 5) & 0x7; - rn = (raw >> 0) & 0xf; - - if ((op1 & b11100) == b00000) - result = process_armv7_arm_parallel_addition_and_subtraction_signed(raw); - - else if ((op1 & b11100) == b00100) - result = process_armv7_arm_parallel_addition_and_subtraction_unsigned(raw); - - else if ((op1 & b11000) == b01000) - result = process_armv7_arm_packing_unpacking_saturation_and_reversal(raw); - - else if ((op1 & b11000) == b10000) - result = process_armv7_arm_signed_multiply_signed_and_unsigned_divide(raw); - - else if (op1 == b11000) - { - if (op2 == b000) - { - if (rd == b1111) - result = armv7_read_arm_instr_usad8(raw); - else - result = armv7_read_arm_instr_usada8(raw); - } - - goto a54_done; - - } - - else if ((op1 & b11110) == b11010) - { - if ((op2 & b011) == b010) - result = armv7_read_arm_instr_sbfx(raw); - - goto a54_done; - - } - - else if ((op1 & b11110) == b11100) - { - if ((op2 & b011) == b000) - { - if (rn == b1111) - result = armv7_read_arm_instr_bfc(raw); - else - result = armv7_read_arm_instr_bfi(raw); - } - - goto a54_done; - - } - - else if ((op1 & b11110) == b11110) - { - if ((op2 & b011) == b010) - result = armv7_read_arm_instr_ubfx(raw); - - goto a54_done; - - } - - else if (op1 == b11111 && op2 == b111 && cond == b1110) - result = armv7_read_arm_instr_ubfx(raw); - - a54_done: - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A5.4.1. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_arm_parallel_addition_and_subtraction_signed(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à retourner */ - uint32_t op1; /* Champ 'op1' à retrouver */ - uint32_t op2; /* Champ 'op2' à retrouver */ - - /** - * Suit les directives de : - * § A5.4.1 Parallel addition and subtraction, signed - */ - - if ((raw & 0x0fc00010) != 0x06000010) return NULL; - - result = NULL; - - op1 = (raw >> 20) & 0x3; - op2 = (raw >> 5) & 0x7; - - if (op1 == b01) - { - if (op2 == b000) - result = armv7_read_arm_instr_sadd16(raw); - - else if (op2 == b001) - result = armv7_read_arm_instr_sasx(raw); - - else if (op2 == b010) - result = armv7_read_arm_instr_ssax(raw); - - else if (op2 == b011) - result = armv7_read_arm_instr_ssub16(raw); - - else if (op2 == b100) - result = armv7_read_arm_instr_sadd8(raw); - - else if (op2 == b111) - result = armv7_read_arm_instr_ssub8(raw); - - } - - else if (op1 == b10) - { - if (op2 == b000) - result = armv7_read_arm_instr_qadd16(raw); - - else if (op2 == b001) - result = armv7_read_arm_instr_qasx(raw); - - else if (op2 == b010) - result = armv7_read_arm_instr_qsax(raw); - - else if (op2 == b011) - result = armv7_read_arm_instr_qsub16(raw); - - else if (op2 == b100) - result = armv7_read_arm_instr_qadd8(raw); - - else if (op2 == b111) - result = armv7_read_arm_instr_qsub8(raw); - - } - - else if (op1 == b11) - { - if (op2 == b000) - result = armv7_read_arm_instr_shadd16(raw); - - else if (op2 == b001) - result = armv7_read_arm_instr_shasx(raw); - - else if (op2 == b010) - result = armv7_read_arm_instr_shsax(raw); - - else if (op2 == b011) - result = armv7_read_arm_instr_shsub16(raw); - - else if (op2 == b100) - result = armv7_read_arm_instr_shadd8(raw); - - else if (op2 == b111) - result = armv7_read_arm_instr_shsub8(raw); - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A5.4.2. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_arm_parallel_addition_and_subtraction_unsigned(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à retourner */ - uint32_t op1; /* Champ 'op1' à retrouver */ - uint32_t op2; /* Champ 'op2' à retrouver */ - - /** - * Suit les directives de : - * § A5.4.2 Parallel addition and subtraction, unsigned - */ - - if ((raw & 0x0fc00010) != 0x06400010) return NULL; - - result = NULL; - - op1 = (raw >> 20) & 0x3; - op2 = (raw >> 5) & 0x7; - - if (op1 == b01) - { - if (op2 == b000) - result = armv7_read_arm_instr_uadd16(raw); - - else if (op2 == b001) - result = armv7_read_arm_instr_uasx(raw); - - else if (op2 == b010) - result = armv7_read_arm_instr_usax(raw); - - else if (op2 == b011) - result = armv7_read_arm_instr_usub16(raw); - - else if (op2 == b100) - result = armv7_read_arm_instr_uadd8(raw); - - else if (op2 == b111) - result = armv7_read_arm_instr_usub8(raw); - - } - - else if (op1 == b10) - { - if (op2 == b000) - result = armv7_read_arm_instr_uqadd16(raw); - - else if (op2 == b001) - result = armv7_read_arm_instr_uqasx(raw); - - else if (op2 == b010) - result = armv7_read_arm_instr_uqsax(raw); - - else if (op2 == b011) - result = armv7_read_arm_instr_uqsub16(raw); - - else if (op2 == b100) - result = armv7_read_arm_instr_uqadd8(raw); - - else if (op2 == b111) - result = armv7_read_arm_instr_uqsub8(raw); - - } - - else if (op1 == b11) - { - if (op2 == b000) - result = armv7_read_arm_instr_uhadd16(raw); - - else if (op2 == b001) - result = armv7_read_arm_instr_uhasx(raw); - - else if (op2 == b010) - result = armv7_read_arm_instr_uhsax(raw); - - else if (op2 == b011) - result = armv7_read_arm_instr_uhsub16(raw); - - else if (op2 == b100) - result = armv7_read_arm_instr_uhadd8(raw); - - else if (op2 == b111) - result = armv7_read_arm_instr_uhsub8(raw); - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A5.4.3. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_arm_packing_unpacking_saturation_and_reversal(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à retourner */ - uint32_t op1; /* Champ 'op1' à retrouver */ - uint32_t a; /* Champ 'a' à retrouver */ - uint32_t op2; /* Champ 'op2' à retrouver */ - - /** - * Suit les directives de : - * § A5.4.3 Packing, unpacking, saturation, and reversal - */ - - if ((raw & 0x0f800010) != 0x06800010) return NULL; - - result = NULL; - - op1 = (raw >> 20) & 0x7; - a = (raw >> 16) & 0xf; - op2 = (raw >> 5) & 0x7; - - if ((op1 & b111) == b000) - { - if ((op2 & b001) == b000) - { - result = armv7_read_arm_instr_pkh(raw); - goto a543_done; - } - else if (op2 == b011) - { - if (a == b1111) - { - result = armv7_read_arm_instr_sxtb16(raw); - goto a543_done; - } - else - { - result = armv7_read_arm_instr_sxtab16(raw); - goto a543_done; - } - } - else if (op2 == b101) - { - result = armv7_read_arm_instr_sel(raw); - goto a543_done; - } - } - - else if ((op1 & b110) == b010 && (op2 & b001) == b000) - { - result = armv7_read_arm_instr_ssat(raw); - goto a543_done; - } - - else if (op1 == b010) - { - if (op2 == b001) - { - result = armv7_read_arm_instr_ssat16(raw); - goto a543_done; - } - else if (op2 == b011) - { - if (a == b1111) - { - result = armv7_read_arm_instr_sxtb(raw); - goto a543_done; - } - else - { - result = armv7_read_arm_instr_sxtab(raw); - goto a543_done; - } - } - } - - else if (op1 == b011) - { - if (op2 == b001) - { - result = armv7_read_arm_instr_rev(raw); - goto a543_done; - } - else if (op2 == b011) - { - if (a == b1111) - { - result = armv7_read_arm_instr_sxth(raw); - goto a543_done; - } - else - { - result = armv7_read_arm_instr_sxtah(raw); - goto a543_done; - } - } - else if (op2 == b101) - { - result = armv7_read_arm_instr_rev16(raw); - goto a543_done; - } - } - - else if (op1 == b100 && op2 == b011) - { - if (a == b1111) - { - result = armv7_read_arm_instr_uxtb16(raw); - goto a543_done; - } - else - { - result = armv7_read_arm_instr_uxtab16(raw); - goto a543_done; - } - } - - else if ((op1 & b110) == b110 && (op2 & b001) == b000) - { - result = armv7_read_arm_instr_usat(raw); - goto a543_done; - } - - else if (op1 == b110) - { - if (op2 == b001) - { - result = armv7_read_arm_instr_usat16(raw); - goto a543_done; - } - else if (op2 == b011) - { - if (a == b1111) - { - result = armv7_read_arm_instr_uxtb(raw); - goto a543_done; - } - else - { - result = armv7_read_arm_instr_uxtab(raw); - goto a543_done; - } - } - } - - else if (op1 == b111) - { - if (op2 == b001) - { - result = armv7_read_arm_instr_rbit(raw); - goto a543_done; - } - else if (op2 == b011) - { - if (a == b1111) - { - result = armv7_read_arm_instr_uxth(raw); - goto a543_done; - } - else - { - result = armv7_read_arm_instr_uxtah(raw); - goto a543_done; - } - } - else if (op2 == b101) - { - result = armv7_read_arm_instr_revsh(raw); - goto a543_done; - } - } - - a543_done: - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A5.4.4. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_arm_signed_multiply_signed_and_unsigned_divide(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à retourner */ - uint32_t op1; /* Champ 'op1' à retrouver */ - uint32_t a; /* Champ 'a' à retrouver */ - uint32_t op2; /* Champ 'op2' à retrouver */ - - /** - * Suit les directives de : - * § A5.4.4 Signed multiply, signed and unsigned divide - */ - - if ((raw & 0x0f800010) != 0x07000010) return NULL; - - result = NULL; - - op1 = (raw >> 20) & 0x7; - a = (raw >> 12) & 0xf; - op2 = (raw >> 5) & 0x7; - - if (op1 == b000) - { - if ((op2 & b110) == b000) - { - if (a != b1111) - result = armv7_read_arm_instr_smlad(raw); - else/* if (a == b1111)*/ - result = armv7_read_arm_instr_smuad(raw); - - } - - else if ((op2 & b110) == b010) - { - if (a != b1111) - result = armv7_read_arm_instr_smlsd(raw); - else/* if (a == b1111)*/ - result = armv7_read_arm_instr_smusd(raw); - - } - - } - - else if (op1 == b001) - { - if (op2 == b000) - result = armv7_read_arm_instr_sdiv(raw); - - } - - else if (op1 == b011) - { - if (op2 == b000) - result = armv7_read_arm_instr_udiv(raw); - - } - - else if (op1 == b100) - { - if ((op2 & b110) == b000) - result = armv7_read_arm_instr_smlald(raw); - - else if ((op2 & b110) == b010) - result = armv7_read_arm_instr_smlsld(raw); - - } - - else if (op1 == b101) - { - if ((op2 & b110) == b000) - { - if (a != b1111) - result = armv7_read_arm_instr_smmla(raw); - else/* if (a == b1111)*/ - result = armv7_read_arm_instr_smmul(raw); - - } - - else if ((op2 & b110) == b110) - result = armv7_read_arm_instr_smmls(raw); - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A5.5. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_arm_branch_branch_with_link_and_block_data_transfer(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à retourner */ - uint32_t op; /* Champ 'op' à retrouver */ - uint32_t rn; /* Champ 'rn' à retrouver */ - uint32_t r; /* Champ 'r' à retrouver */ - - /** - * Suit les directives de : - * § A5.5 Branch, branch with link, and block data transferr - */ - - if ((raw & 0x0c000000) != 0x08000000) return NULL; - - result = NULL; - - op = (raw >> 20) & 0x3f; - rn = (raw >> 16) & 0xf; - r = (raw >> 15) & 0x1; - - if ((op & b111101) == b000000) - result = armv7_read_arm_instr_stmda_stmed(raw); - - else if ((op & b111101) == b000001) - result = armv7_read_arm_instr_ldmda_ldmfa(raw); - - else if ((op & b111101) == b001000) - result = armv7_read_arm_instr_stm_stmia_stmea(raw); - - else if (op == b001001) - result = armv7_read_arm_instr_ldm_ldmia_ldmfd_arm(raw); - - else if (op == b001011) - { - if (rn != b1101) - result = armv7_read_arm_instr_ldm_ldmia_ldmfd_arm(raw); - else /* if (rn == b1101) */ - result = armv7_read_arm_instr_pop_arm(raw); - } - - else if (op == b010000) - result = armv7_read_arm_instr_stmdb_stmfd(raw); - - else if (op == b010010) - { - if (rn != b1101) - result = armv7_read_arm_instr_stmdb_stmfd(raw); - else /* if (rn == b1101) */ - result = armv7_read_arm_instr_push(raw); - } - - else if ((op & b111101) == b010001) - result = armv7_read_arm_instr_ldmdb_ldmea(raw); - - else if ((op & b111101) == b011000) - result = armv7_read_arm_instr_stmib_stmfa(raw); - - else if ((op & b111101) == b011001) - result = armv7_read_arm_instr_ldmib_ldmed(raw); - - else if ((op & b100101) == b000100) - result = armv7_read_arm_instr_stm_user_registers(raw); - - else if ((op & b100101) == b000101) - { - if (r == b0) - result = armv7_read_arm_instr_ldm_user_registers(raw); - else /* if (r == b1) */ - result = armv7_read_arm_instr_ldm_exception_return(raw); - } - - else if ((op & b110000) == b100000) - result = armv7_read_arm_instr_b(raw); - - else if ((op & b110000) == b110000) - result = armv7_read_arm_instr_bl_blx_immediate(raw); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A5.6. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_arm_coprocessor_instructions_and_supervisor_call(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à retourner */ - uint32_t op1; /* Champ 'op1' à retrouver */ - uint32_t rn; /* Champ 'rn' à retrouver */ - uint32_t coproc; /* Champ 'coproc' à retrouver */ - uint32_t op; /* Champ 'op' à retrouver */ - - /** - * Suit les directives de : - * § A5.6 Coprocessor instructions, and Supervisor Call - */ - - if ((raw & 0x0c000000) != 0x0c000000) return NULL; - - result = NULL; - - op1 = (raw >> 20) & 0x3f; - rn = (raw >> 16) & 0xf; - coproc = (raw >> 8) & 0xf; - op = (raw >> 4) & 0x1; - - if ((op1 & b111110) == b000000) - result = g_undef_instruction_new(IBS_UNDEFINED); - - else if ((op1 & b110000) == b110000) - result = armv7_read_arm_instr_svc_previously_swi(raw); - - else if ((coproc & b1110) != b1010) - { - if ((op1 & b100001) == b000000 && (op1 & b111011) != b000000) - result = armv7_read_arm_instr_stc_stc2(raw); - - else if ((op1 & b100001) == b000001 && (op1 & b111011) != b000001) - { - if (rn != b1111) - result = armv7_read_arm_instr_ldc_ldc2_immediate(raw); - else - result = armv7_read_arm_instr_ldc_ldc2_literal(raw); - - } - - else if (op1 == b000100) - result = armv7_read_arm_instr_mcrr_mcrr2(raw); - - else if (op1 == b000101) - result = armv7_read_arm_instr_mrrc_mrrc2(raw); - - - else if ((op1 & b110000) == b100000 && op == b0) - result = armv7_read_arm_instr_cdp_cdp2(raw); - - else if ((op1 & b110001) == b100000 && op == b1) - result = armv7_read_arm_instr_mcr_mcr2(raw); - - else if ((op1 & b110001) == b100001 && op == b1) - result = armv7_read_arm_instr_mrc_mrc2(raw); - - } - - else if ((coproc & b1110) == b1010) - { - /* TODO */ - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A5.7. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_arm_unconditional_instructions(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à retourner */ - uint32_t op1; /* Champ 'op1' à retrouver */ - uint32_t rn; /* Champ 'rn' à retrouver */ - uint32_t op; /* Champ 'op' à retrouver */ - - /** - * Suit les directives de : - * § A5.7 Unconditional instructions - */ - - if ((raw & 0xf0000000) != 0xf0000000) return NULL; - - result = NULL; - - op1 = (raw >> 20) & 0xff; - rn = (raw >> 16) & 0xf; - op = (raw >> 4) & 0x1; - - if ((op1 & b10000000) == b00000000) - result = process_armv7_arm_memory_hints_advanced_simd_instructions_and_miscellaneous_instructions(raw); - - else if ((op1 & b11100101) == b10000100) - result = armv7_read_arm_instr_srs_arm(raw); - - else if ((op1 & b11100101) == b10000001) - result = armv7_read_arm_instr_rfe(raw); - - else if ((op1 & b11100000) == b10100000) - result = armv7_read_arm_instr_bl_blx_immediate(raw); - - else if ((op1 & b11100001) == b11000000 && (op1 & b11111011) != b11000000) - result = armv7_read_arm_instr_stc_stc2(raw); - - else if ((op1 & b11100001) == b11000001 && (op1 & b11111011) != b11000001) - { - if (rn != b1111) - result = armv7_read_arm_instr_ldc_ldc2_immediate(raw); - else/* if (rn == b1111)*/ - result = armv7_read_arm_instr_ldc_ldc2_literal(raw); - } - - else if (op1 == b11000100) - result = armv7_read_arm_instr_mcrr_mcrr2(raw); - - else if (op1 == b11000101) - result = armv7_read_arm_instr_mrrc_mrrc2(raw); - - else if ((op1 & b11110000) == b11100000 && op == b0) - result = armv7_read_arm_instr_cdp_cdp2(raw); - - else if ((op1 & b11110001) == b11100000 && op == b1) - result = armv7_read_arm_instr_mcr_mcr2(raw); - - else if ((op1 & b11110001) == b11100001 && op == b1) - result = armv7_read_arm_instr_mrc_mrc2(raw); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A5.7.1. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_arm_memory_hints_advanced_simd_instructions_and_miscellaneous_instructions(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à retourner */ - uint32_t op1; /* Champ 'op1' à retrouver */ - uint32_t rn; /* Champ 'rn' à retrouver */ - uint32_t op2; /* Champ 'op2' à retrouver */ - - /** - * Suit les directives de : - * § A5.7.1 Memory hints, Advanced SIMD instructions, and miscellaneous instructions - */ - - if ((raw & 0xf8000000) != 0xf0000000) return NULL; - - result = NULL; - - op1 = (raw >> 20) & 0x7f; - rn = (raw >> 16) & 0xf; - op2 = (raw >> 4) & 0xf; - - if (op1 == b0010000) - { - if ((op2 & b0010) == b0000 && (rn & b0001) == b0000) - result = armv7_read_arm_instr_cps_arm(raw); - - else if (op2 == b0000 && (rn & b0001) == b0001) - result = armv7_read_arm_instr_cps_arm(raw); - - } - - else if ((op1 & b1100000) == b0100000) - result = process_armv7_simd_advanced_simd_data_processing_instructions(raw, true); - - else if ((op1 & b1110001) == b1000000) - result = process_armv7_simd_advanced_simd_element_or_structure_load_store_instructions(raw, true); - - else if ((op1 & b1110111) == b1000001) - result = g_undef_instruction_new(IBS_NOP); - - else if ((op1 & b1110111) == b1000101) - result = armv7_read_arm_instr_pli_immediate_literal(raw); - - else if ((op1 & b1110011) == b1000011) - result = g_undef_instruction_new(IBS_UNPREDICTABLE); - - else if ((op1 & b1110111) == b1010101) - { - if (rn != b1111) - result = armv7_read_arm_instr_pld_pldw_immediate(raw); - else - result = g_undef_instruction_new(IBS_UNPREDICTABLE); - - } - - else if ((op1 & b1110111) == b1010101) - { - if (rn != b1111) - result = armv7_read_arm_instr_pld_pldw_immediate(raw); - else - result = armv7_read_arm_instr_pld_literal(raw); - - } - - else if (op1 == b1010011) - result = g_undef_instruction_new(IBS_UNPREDICTABLE); - - else if (op1 == b1010111) - { - if (op2 == b0000) - result = g_undef_instruction_new(IBS_UNPREDICTABLE); - - else if (op2 == b0001) - result = armv7_read_arm_instr_clrex(raw); - - else if ((op2 & b1110) == b0010) - result = g_undef_instruction_new(IBS_UNPREDICTABLE); - - else if (op2 == b0100) - result = armv7_read_arm_instr_dsb(raw); - - else if (op2 == b0101) - result = armv7_read_arm_instr_dmb(raw); - - else if (op2 == b0110) - result = armv7_read_arm_instr_isb(raw); - - else if (op2 == b0111) - result = g_undef_instruction_new(IBS_UNPREDICTABLE); - - else if ((op2 & b1000) == b1000) - result = g_undef_instruction_new(IBS_UNPREDICTABLE); - - } - - else if ((op1 & b1111011) == b1011011) - result = g_undef_instruction_new(IBS_UNPREDICTABLE); - - else if ((op1 & b1110111) == b1100001 && (op2 & b0001) == b0000) - result = g_undef_instruction_new(IBS_NOP); - - else if ((op1 & b1110111) == b1100101 && (op2 & b0001) == b0000) - result = armv7_read_arm_instr_pli_register(raw); - - else if ((op1 & b1110111) == b1110001 && (op2 & b0001) == b0000) - result = armv7_read_arm_instr_pld_pldw_register(raw); - - return result; - -} diff --git a/src/arch/arm/v7/arm.h b/src/arch/arm/v7/arm.h deleted file mode 100644 index 997bf64..0000000 --- a/src/arch/arm/v7/arm.h +++ /dev/null @@ -1,37 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * arm.h - prototypes pour le désassemblage des instructions ARMv7 - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_ARM_V7_ARM_H -#define _ARCH_ARM_V7_ARM_H - - -#include "../../instruction.h" - - - -/* Désassemble une instruction ARMv7 liées au chapitre A5.1. */ -GArchInstruction *process_armv7_arm_instruction_set_encoding(uint32_t raw); - - - -#endif /* _ARCH_ARM_V7_ARM_H */ diff --git a/src/arch/arm/v7/build_tmp_decl.sh b/src/arch/arm/v7/build_tmp_decl.sh deleted file mode 100755 index 0d0feee..0000000 --- a/src/arch/arm/v7/build_tmp_decl.sh +++ /dev/null @@ -1,39 +0,0 @@ -#!/bin/sh - - -arch=$1 -header="opcodes/${arch}_opcodes.h" -headertmp="opcodes/opcodes_tmp_$arch.h" - -echo "#ifndef ${arch}_def_tmp_h" > $headertmp -echo "#define ${arch}_def_tmp_h" >> $headertmp - -target=armv7_read_${arch}_instr - -needed=`grep $target $arch.c | sed "s/.*\(${target}_[^(]*\).*/\1/" | sort | uniq` - -for n in $needed; do - - echo " $n..." - - test -f $header && grep -q "$n(" $header - if [ $? -ne 0 ]; then - - if [ $arch = "simd" ]; then - echo "#define $n(r, a) NULL" >> $headertmp - else - echo "#define $n(r) NULL" >> $headertmp - fi - - else - - echo "$n found in $header" - - fi - -done - -echo "#endif" >> $headertmp - - - diff --git a/src/arch/arm/v7/context.c b/src/arch/arm/v7/context.c deleted file mode 100644 index 8fc7fc1..0000000 --- a/src/arch/arm/v7/context.c +++ /dev/null @@ -1,305 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * context.c - contexte lié à l'exécution d'un processeur - * - * Copyright (C) 2015-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#include "context.h" - - -#include <assert.h> - - -#include "../context-int.h" - - - -/* ------------------------ MANIPULATION GLOBALE DU CONTEXTE ------------------------ */ - - -/* Définition d'un contexte pour processeur ARM (instance) */ -struct _GArmV7Context -{ - GArmContext parent; /* A laisser en premier */ - -}; - - -/* Définition d'un contexte pour processeur ARM (classe) */ -struct _GArmV7ContextClass -{ - GArmContextClass parent; /* A laisser en premier */ - -}; - - -/* Initialise la classe des contextes de processeur ARM. */ -static void g_armv7_context_class_init(GArmV7ContextClass *); - -/* Initialise une instance de contexte de processeur ARM. */ -static void g_armv7_context_init(GArmV7Context *); - -/* Supprime toutes les références externes. */ -static void g_armv7_context_dispose(GArmV7Context *); - -/* Procède à la libération totale de la mémoire. */ -static void g_armv7_context_finalize(GArmV7Context *); - -/* Ajoute une adresse virtuelle comme point de départ de code. */ -static void g_armv7_context_push_drop_point(GArmV7Context *, DisassPriorityLevel, virt_t, va_list); - - - -/* ---------------------------------------------------------------------------------- */ -/* MANIPULATION GLOBALE DU CONTEXTE */ -/* ---------------------------------------------------------------------------------- */ - - -/* Indique le type définit par la GLib pour le contexte de processeur ARM. */ -G_DEFINE_TYPE(GArmV7Context, g_armv7_context, G_TYPE_ARM_CONTEXT); - - -/****************************************************************************** -* * -* Paramètres : klass = classe à initialiser. * -* * -* Description : Initialise la classe des contextes de processeur ARM. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_context_class_init(GArmV7ContextClass *klass) -{ - GObjectClass *object; /* Autre version de la classe */ - GProcContextClass *proc; /* Version parente de la classe*/ - - object = G_OBJECT_CLASS(klass); - - object->dispose = (GObjectFinalizeFunc/* ! */)g_armv7_context_dispose; - object->finalize = (GObjectFinalizeFunc)g_armv7_context_finalize; - - proc = G_PROC_CONTEXT_CLASS(klass); - - proc->push_point = (push_drop_point_fc)g_armv7_context_push_drop_point; - -} - - -/****************************************************************************** -* * -* Paramètres : ctx = instance à initialiser. * -* * -* Description : Initialise une instance de contexte de processeur ARM. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_context_init(GArmV7Context *ctx) -{ - GArmContext *base; /* Autre version du contexte */ - - base = G_ARM_CONTEXT(ctx); - - base->areas = (disass_arm_area *)calloc(1, sizeof(disass_arm_area)); - base->acount = 1; - - base->areas[0].start = 0; - base->areas[0].end = (virt_t)-1; - base->areas[0].marker = AV7IS_ARM; - -} - - -/****************************************************************************** -* * -* Paramètres : ctx = instance d'objet GLib à traiter. * -* * -* Description : Supprime toutes les références externes. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_context_dispose(GArmV7Context *ctx) -{ - G_OBJECT_CLASS(g_armv7_context_parent_class)->dispose(G_OBJECT(ctx)); - -} - - -/****************************************************************************** -* * -* Paramètres : ctx = instance d'objet GLib à traiter. * -* * -* Description : Procède à la libération totale de la mémoire. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_context_finalize(GArmV7Context *ctx) -{ - G_OBJECT_CLASS(g_armv7_context_parent_class)->finalize(G_OBJECT(ctx)); - -} - - -/****************************************************************************** -* * -* Paramètres : - * -* * -* Description : Crée un contexte pour l'exécution du processeur ARM. * -* * -* Retour : Contexte mis en place. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArmV7Context *g_armv7_context_new(void) -{ - GArmV7Context *result; /* Structure à retourner */ - - result = g_object_new(G_TYPE_ARMV7_CONTEXT, NULL); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : ctx = contexte de désassemblage à compléter. * -* level = indication de priorité et d'origine de l'adresse. * -* addr = adresse d'un nouveau point de départ à traiter. * -* ap = forme générique d'un encodage à mémoriser. * -* * -* Description : Ajoute une adresse virtuelle comme point de départ de code. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_context_push_drop_point(GArmV7Context *ctx, DisassPriorityLevel level, virt_t addr, va_list ap) -{ - ArmV7InstrSet marker; /* Type de jeu d'instructions */ - - switch (level) - { - case DPL_ENTRY_POINT: - case DPL_SYMBOL: - - if (addr & 0x1) - { - addr -= 0x1; - marker = AV7IS_THUMB; - } - else - marker = AV7IS_ARM; - - break; - - default: - - /** - * Les messages de GCC annoncent parfois les choses très clairement : - * - * context.c:233:33: warning: 'ArmV7InstrSet' is promoted to 'int' when passed through '...' - * marker = va_arg(ap, ArmV7InstrSet); - * ^ - * context.c:233:33: note: (so you should pass 'int' not 'ArmV7InstrSet' to 'va_arg') - * context.c:233:33: note: if this code is reached, the program will abort - * - */ - - marker = (ArmV7InstrSet)va_arg(ap, unsigned int); - - /** - * Attention : toute adresse impaire est destinée à du mode Thumb. - * - * Mais la réciproque n'est pas vraie : le mode Thumb peut aussi - * manipuler des adresses paires. - */ - assert(((addr & 0x1) && marker == AV7IS_THUMB) || (addr & 0x1) == 0); - - addr &= ~0x1; - - break; - - } - - g_armv7_context_define_encoding(ctx, addr, marker); - - G_PROC_CONTEXT_CLASS(g_armv7_context_parent_class)->push_point(G_PROC_CONTEXT(ctx), level, addr, ap); - -} - - -/****************************************************************************** -* * -* Paramètres : ctx = contexte de désassemblage à compléter. * -* addr = adresse d'un nouveau point de départ à créer. * -* marker = forme générique d'un encodage à mémoriser. * -* * -* Description : Enregistre l'encodage (générique) utilisé à une adresse. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -void g_armv7_context_define_encoding(GArmV7Context *ctx, virt_t addr, ArmV7InstrSet marker) -{ - _g_arm_context_define_encoding(G_ARM_CONTEXT(ctx), addr, marker); - -} - - -/****************************************************************************** -* * -* Paramètres : ctx = contexte de désassemblage à consulter. * -* addr = adresse d'un nouveau point de départ à retrouver. * -* * -* Description : Indique l'encodage (générique) utilisé à une adresse donnée. * -* * -* Retour : Marqueur à priori toujours valide. * -* * -* Remarques : - * -* * -******************************************************************************/ - -ArmV7InstrSet g_armv7_context_find_encoding(GArmV7Context *ctx, virt_t addr) -{ - return (ArmV7InstrSet)_g_arm_context_find_encoding(G_ARM_CONTEXT(ctx), addr); - -} diff --git a/src/arch/arm/v7/context.h b/src/arch/arm/v7/context.h deleted file mode 100644 index 2c3ff03..0000000 --- a/src/arch/arm/v7/context.h +++ /dev/null @@ -1,81 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * context.h - prototypes pour le contexte lié à l'exécution d'un processeur - * - * Copyright (C) 2015-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_ARM_V7_CONTEXT_H -#define _ARCH_ARM_V7_CONTEXT_H - - -#include <glib-object.h> - - -#include "../../vmpa.h" - - - -/* ------------------------ MANIPULATION GLOBALE DU CONTEXTE ------------------------ */ - - -#define G_TYPE_ARMV7_CONTEXT g_armv7_context_get_type() -#define G_ARMV7_CONTEXT(obj) (G_TYPE_CHECK_INSTANCE_CAST((obj), g_armv7_context_get_type(), GArmV7Context)) -#define G_IS_ARMV7_CONTEXT(obj) (G_TYPE_CHECK_INSTANCE_TYPE((obj), g_armv7_context_get_type())) -#define G_ARMV7_CONTEXT_CLASS(klass) (G_TYPE_CHECK_CLASS_CAST((klass), G_TYPE_ARMV7_CONTEXT, GGArmV7ContextClass)) -#define G_IS_ARMV7_CONTEXT_CLASS(klass) (G_TYPE_CHECK_CLASS_TYPE((klass), G_TYPE_ARMV7_CONTEXT)) -#define G_ARMV7_CONTEXT_GET_CLASS(obj) (G_TYPE_INSTANCE_GET_CLASS((obj), G_TYPE_ARMV7_CONTEXT, GGArmV7ContextClass)) - - -/* Définition d'un contexte pour processeur ARM (instance) */ -typedef struct _GArmV7Context GArmV7Context; - -/* Définition d'un contexte pour processeur ARM (classe) */ -typedef struct _GArmV7ContextClass GArmV7ContextClass; - - -/* Indique le type définit par la GLib pour le contexte de processeur ARM. */ -GType g_armv7_context_get_type(void); - -/* Crée un contexte pour l'exécution du processeur ARM. */ -GArmV7Context *g_armv7_context_new(void); - - -/* Jeux d'instructions possibles avec ARM v7 */ -typedef enum _ArmV7InstrSet -{ - AV7IS_ARM, /* Encodage classique */ - AV7IS_THUMB, /* Encodage compressé */ - AV7IS_JAZELLE, /* Encodage JVM */ - AV7IS_THUMBEE, /* Encodage dense + JIT/AOT */ - - AV7IS_COUNT - -} ArmV7InstrSet; - - -/* Enregistre l'encodage (générique) utilisé à une adresse. */ -void g_armv7_context_define_encoding(GArmV7Context *, virt_t, ArmV7InstrSet); - -/* Indique l'encodage (générique) utilisé à une adresse donnée. */ -ArmV7InstrSet g_armv7_context_find_encoding(GArmV7Context *, virt_t); - - - -#endif /* _ARCH_ARM_V7_CONTEXT_H */ diff --git a/src/arch/arm/v7/core.c b/src/arch/arm/v7/core.c deleted file mode 100644 index a2d0e45..0000000 --- a/src/arch/arm/v7/core.c +++ /dev/null @@ -1,66 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * core.c - chargement et déchargement des mécanismes internes de l'architecture ARMv7 - * - * Copyright (C) 2016-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#include "core.h" - - - -/****************************************************************************** -* * -* Paramètres : - * -* * -* Description : Met en place les mécanismes internes de l'architecture ARMv7.* -* * -* Retour : Bilan de l'opération. * -* * -* Remarques : - * -* * -******************************************************************************/ - -bool init_armv7_core(void) -{ - bool result; /* Bilan à renvoyer */ - - result = true; - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : - * -* * -* Description : Supprime les mécanismes internes de l'architecture ARMv7. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -void exit_armv7_core(void) -{ - -} diff --git a/src/arch/arm/v7/core.h b/src/arch/arm/v7/core.h deleted file mode 100644 index b4c254f..0000000 --- a/src/arch/arm/v7/core.h +++ /dev/null @@ -1,40 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * core.h - prototypes pour le chargement et le déchargement des mécanismes internes de l'architecture ARMv7 - * - * Copyright (C) 2016-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_ARM_V7_CORE_H -#define _ARCH_ARM_V7_CORE_H - - -#include <stdbool.h> - - - -/* Met en place les mécanismes internes de l'architecture ARMv7. */ -bool init_armv7_core(void); - -/* Supprime les mécanismes internes de l'architecture ARMv7. */ -void exit_armv7_core(void); - - - -#endif /* _ARCH_ARM_V7_CORE_H */ diff --git a/src/arch/arm/v7/cregister.c b/src/arch/arm/v7/cregister.c deleted file mode 100644 index 33564f0..0000000 --- a/src/arch/arm/v7/cregister.c +++ /dev/null @@ -1,212 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * cregisters.c - aides auxiliaires relatives aux registres de co-processeur ARMv7 - * - * Copyright (C) 2016-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#include "cregister.h" - - -#include <stdio.h> - - -#include "../register-int.h" - - - -/* Représentation d'un registre de co-processeur ARMv7 (instance) */ -struct _GArmV7CRegister -{ - GArmRegister parent; /* Instance parente */ - -}; - - -/* Représentation d'un registre de co-processeur ARMv7 (classe) */ -struct _GArmV7CRegisterClass -{ - GArmRegisterClass parent; /* Classe parente */ - -}; - - - -/* Initialise la classe des registres de co-processeur ARMv7. */ -static void g_armv7_cregister_class_init(GArmV7CRegisterClass *); - -/* Initialise une instance de registre de co-processeur ARMv7. */ -static void g_armv7_cregister_init(GArmV7CRegister *); - -/* Supprime toutes les références externes. */ -static void g_armv7_cregister_dispose(GArmV7CRegister *); - -/* Procède à la libération totale de la mémoire. */ -static void g_armv7_cregister_finalize(GArmV7CRegister *); - -/* Traduit un registre en version humainement lisible. */ -static void g_armv7_cregister_print(const GArmV7CRegister *, GBufferLine *, AsmSyntax); - - - -/* Indique le type défini pour une représentation d'un registre de co-processeur ARMv7. */ -G_DEFINE_TYPE(GArmV7CRegister, g_armv7_cregister, G_TYPE_ARM_REGISTER); - - -/****************************************************************************** -* * -* Paramètres : klass = classe à initialiser. * -* * -* Description : Initialise la classe des registres de co-processeur ARMv7. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_cregister_class_init(GArmV7CRegisterClass *klass) -{ - GObjectClass *object_class; /* Autre version de la classe */ - GArchRegisterClass *reg_class; /* Classe de haut niveau */ - - object_class = G_OBJECT_CLASS(klass); - reg_class = G_ARCH_REGISTER_CLASS(klass); - - object_class->dispose = (GObjectFinalizeFunc/* ! */)g_armv7_cregister_dispose; - object_class->finalize = (GObjectFinalizeFunc)g_armv7_cregister_finalize; - - reg_class->print = (reg_print_fc)g_armv7_cregister_print; - -} - - -/****************************************************************************** -* * -* Paramètres : reg = instance à initialiser. * -* * -* Description : Initialise une instance de registre de co-processeur ARMv7. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_cregister_init(GArmV7CRegister *reg) -{ - -} - - -/****************************************************************************** -* * -* Paramètres : reg = instance d'objet GLib à traiter. * -* * -* Description : Supprime toutes les références externes. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_cregister_dispose(GArmV7CRegister *reg) -{ - G_OBJECT_CLASS(g_armv7_cregister_parent_class)->dispose(G_OBJECT(reg)); - -} - - -/****************************************************************************** -* * -* Paramètres : reg = instance d'objet GLib à traiter. * -* * -* Description : Procède à la libération totale de la mémoire. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_cregister_finalize(GArmV7CRegister *reg) -{ - G_OBJECT_CLASS(g_armv7_cregister_parent_class)->finalize(G_OBJECT(reg)); - -} - - -/****************************************************************************** -* * -* Paramètres : index = indice du registre correspondant. * -* * -* Description : Crée une réprésentation de registre de co-processeur ARMv7. * -* * -* Retour : Adresse de la structure mise en place. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArmV7CRegister *g_armv7_cregister_new(uint8_t index) -{ - GArmV7CRegister *result; /* Structure à retourner */ - - result = g_object_new(G_TYPE_ARMV7_CREGISTER, NULL); - - G_ARM_REGISTER(result)->index = index; - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : reg = registre à transcrire. * -* line = ligne tampon où imprimer l'opérande donné. * -* syntax = type de représentation demandée. * -* * -* Description : Traduit un registre en version humainement lisible. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_cregister_print(const GArmV7CRegister *reg, GBufferLine *line, AsmSyntax syntax) -{ - char key[MAX_REGNAME_LEN]; /* Mot clef principal */ - size_t klen; /* Taille de ce mot clef */ - - switch (G_ARM_REGISTER(reg)->index) - { - case 0 ... 15: - klen = snprintf(key, MAX_REGNAME_LEN, "c%hhu", G_ARM_REGISTER(reg)->index); - break; - default: - klen = snprintf(key, MAX_REGNAME_LEN, "c??"); - break; - } - - g_buffer_line_append_text(line, BLC_ASSEMBLY, key, klen, RTT_REGISTER, NULL); - -} diff --git a/src/arch/arm/v7/cregister.h b/src/arch/arm/v7/cregister.h deleted file mode 100644 index 5d3a6cf..0000000 --- a/src/arch/arm/v7/cregister.h +++ /dev/null @@ -1,56 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * cregisters.h - prototypes pour les aides auxiliaires relatives aux registres de co-processeur ARMv7 - * - * Copyright (C) 2016-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_ARM_V7_CREGISTER_H -#define _ARCH_ARM_V7_CREGISTER_H - - -#include <glib-object.h> -#include <stdint.h> - - - -#define G_TYPE_ARMV7_CREGISTER g_armv7_cregister_get_type() -#define G_ARMV7_CREGISTER(obj) (G_TYPE_CHECK_INSTANCE_CAST((obj), g_armv7_cregister_get_type(), GArmV7CRegister)) -#define G_IS_ARMV7_CREGISTER(obj) (G_TYPE_CHECK_INSTANCE_TYPE((obj), g_armv7_cregister_get_type())) -#define G_ARMV7_CREGISTER_CLASS(klass) (G_TYPE_CHECK_CLASS_CAST((klass), G_TYPE_ARMV7_CREGISTER, GArmV7CRegisterClass)) -#define G_IS_ARMV7_CREGISTER_CLASS(klass) (G_TYPE_CHECK_CLASS_TYPE((klass), G_TYPE_ARMV7_CREGISTER)) -#define G_ARMV7_CREGISTER_GET_CLASS(obj) (G_TYPE_INSTANCE_GET_CLASS((obj), G_TYPE_ARMV7_CREGISTER, GArmV7CRegisterClass)) - - -/* Représentation d'un registre de co-processeur ARMv7 (instance) */ -typedef struct _GArmV7CRegister GArmV7CRegister; - -/* Représentation d'un registre de co-processeur ARMv7 (classe) */ -typedef struct _GArmV7CRegisterClass GArmV7CRegisterClass; - - -/* Indique le type défini pour une représentation d'un registre de co-processeur ARMv7. */ -GType g_armv7_cregister_get_type(void); - -/* Crée une réprésentation de registre de co-processeur ARMv7. */ -GArmV7CRegister *g_armv7_cregister_new(uint8_t); - - - -#endif /* _ARCH_ARM_V7_CREGISTER_H */ diff --git a/src/arch/arm/v7/fetch.c b/src/arch/arm/v7/fetch.c deleted file mode 100644 index dee9aa2..0000000 --- a/src/arch/arm/v7/fetch.c +++ /dev/null @@ -1,521 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * fetch.c - ajouts de sauts à traiter durant la phase de désassemblage - * - * Copyright (C) 2015-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#include "fetch.h" - - -#include <assert.h> -#include <stdio.h> - - -#include <i18n.h> - - -#include "operands/offset.h" -#include "../register.h" -#include "../../raw.h" -#include "../../../format/format.h" -#include "../../../format/preload.h" - - - -/****************************************************************************** -* * -* Paramètres : instr = instruction ARMv7 à traiter. * -* proc = représentation de l'architecture utilisée. * -* context = contexte associé à la phase de désassemblage. * -* format = acès aux données du binaire d'origine. * -* iset = type de jeu d'instructions courant à faire suivre. * -* * -* Description : Complète un désassemblage accompli pour une instruction. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -void help_fetching_with_instruction_b_with_orig(GArchInstruction *instr, GArchProcessor *proc, GArmV7Context *context, GExeFormat *format, ArmV7InstrSet iset) -{ - const mrange_t *range; /* Emplacementt d'instruction */ - virt_t pc; /* Position dans l'exécution */ - GImmOperand *op; /* Opérande numérique en place */ - int32_t offset; /* Décallage encodé en dur */ - virt_t target; /* Adresse virtuelle visée */ - - range = g_arch_instruction_get_range(instr); - - pc = get_virt_addr(get_mrange_addr(range)); - - - - - switch (iset) - { - case AV7IS_ARM: - pc += 8; - break; - case AV7IS_THUMB: - pc += 4; - break; - default: - assert(0); - break; - } - - - - //pc += get_mrange_length(range); - - op = G_IMM_OPERAND(g_arch_instruction_get_operand(instr, 0)); - - if (g_imm_operand_get_value(op, MDS_32_BITS_SIGNED, &offset)) - g_imm_operand_set_value(op, MDS_32_BITS_UNSIGNED, pc + offset); - - else assert(0); - - g_object_unref(G_OBJECT(op)); - - target = pc + offset; - - //g_armv7_context_define_encoding(context, target, iset); - g_proc_context_push_drop_point(G_PROC_CONTEXT(context), DPL_OTHER, target, iset); - -} - - -/****************************************************************************** -* * -* Paramètres : instr = instruction ARMv7 à traiter. * -* proc = représentation de l'architecture utilisée. * -* context = contexte associé à la phase de désassemblage. * -* format = acès aux données du binaire d'origine. * -* iset = type de jeu d'instructions courant à faire suivre. * -* * -* Description : Complète un désassemblage accompli pour une instruction. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -void help_fetching_with_instruction_bl_with_orig(GArchInstruction *instr, GArchProcessor *proc, GArmV7Context *context, GExeFormat *format, ArmV7InstrSet iset) -{ - const mrange_t *range; /* Emplacementt d'instruction */ - virt_t pc; /* Position dans l'exécution */ - GImmOperand *op; /* Opérande numérique en place */ - int32_t offset; /* Décallage encodé en dur */ - virt_t target; /* Adresse virtuelle visée */ - - range = g_arch_instruction_get_range(instr); - - pc = get_virt_addr(get_mrange_addr(range)); - - /** - * Qu'on se trouve en mode Thumb ou ARM, l'instruction - * ne peut qu'être encodée sur 4 octets. - */ - - assert(get_mrange_length(range) == 4); - - switch (iset) - { - case AV7IS_ARM: - pc += 8; - break; - case AV7IS_THUMB: - pc += 4; - break; - default: - assert(0); - break; - } - - op = G_IMM_OPERAND(g_arch_instruction_get_operand(instr, 0)); - - if (g_imm_operand_get_value(op, MDS_32_BITS_SIGNED, &offset)) - g_imm_operand_set_value(op, MDS_32_BITS_UNSIGNED, pc + offset); - - else assert(0); - - g_object_unref(G_OBJECT(op)); - - target = pc + offset; - - //g_armv7_context_define_encoding(context, target, iset); - g_proc_context_push_drop_point(G_PROC_CONTEXT(context), DPL_OTHER, target, iset); - -} - - -/****************************************************************************** -* * -* Paramètres : instr = instruction ARMv7 à traiter. * -* proc = représentation de l'architecture utilisée. * -* context = contexte associé à la phase de désassemblage. * -* format = acès aux données du binaire d'origine. * -* iset = type de jeu d'instructions courant à inverser. * -* * -* Description : Complète un désassemblage accompli pour une instruction. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -void help_fetching_with_instruction_blx_with_dest(GArchInstruction *instr, GArchProcessor *proc, GArmV7Context *context, GExeFormat *format, ArmV7InstrSet iset) -{ - const mrange_t *range; /* Emplacementt d'instruction */ - virt_t pc; /* Position dans l'exécution */ - GImmOperand *op; /* Opérande numérique en place */ - int32_t offset; /* Décallage encodé en dur */ - virt_t target; /* Adresse virtuelle visée */ - - range = g_arch_instruction_get_range(instr); - - pc = get_virt_addr(get_mrange_addr(range)); - - /** - * Qu'on se trouve en mode Thumb ou ARM, l'instruction - * ne peut qu'être encodée sur 4 octets. - */ - - assert(get_mrange_length(range) == 4); - - pc += 4; - pc -= pc % 4; - - op = G_IMM_OPERAND(g_arch_instruction_get_operand(instr, 0)); - - if (g_imm_operand_get_value(op, MDS_32_BITS_SIGNED, &offset)) - g_imm_operand_set_value(op, MDS_32_BITS_UNSIGNED, pc + offset); - - else assert(0); - - g_object_unref(G_OBJECT(op)); - - target = pc + offset; - - //g_armv7_context_define_encoding(context, target, iset); - g_proc_context_push_drop_point(G_PROC_CONTEXT(context), DPL_OTHER, target, iset); - -} - - -/****************************************************************************** -* * -* Paramètres : instr = instruction ARMv7 à traiter. * -* proc = représentation de l'architecture utilisée. * -* context = contexte associé à la phase de désassemblage. * -* format = acès aux données du binaire d'origine. * -* iset = type de jeu d'instructions courant à faire suivre. * -* * -* Description : Complète un désassemblage accompli pour une instruction. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -void help_fetching_with_instruction_bx_with_orig(GArchInstruction *instr, GArchProcessor *proc, GArmV7Context *context, GExeFormat *format, ArmV7InstrSet iset) -{ - GArchOperand *op; /* Opérande numérique en place */ - GArmRegister *reg; /* Registre matériel manipulé */ - bool is_pc; /* Nature de ce même registre */ - const mrange_t *range; /* Emplacementt d'instruction */ - virt_t pc; /* Position dans l'exécution */ - - op = g_arch_instruction_get_operand(instr, 0); - assert(G_IS_REGISTER_OPERAND(op)); - - /** - * On ne sait agir qu'avec le seul contenu facilement prédictible : pc ! - */ - - reg = G_ARM_REGISTER(g_register_operand_get_register(G_REGISTER_OPERAND(op))); - - is_pc = (g_arm_register_get_index(reg) == 15 /* pc */); - - g_object_unref(G_OBJECT(reg)); - - if (!is_pc) goto hfwibwo_no_pc; - - /** - * On bascule alors le mode de décodage à cette adresse... - */ - - range = g_arch_instruction_get_range(instr); - - pc = get_virt_addr(get_mrange_addr(range)); - - switch (iset) - { - case AV7IS_ARM: - pc += 8; - //g_armv7_context_define_encoding(context, - g_proc_context_push_drop_point(G_PROC_CONTEXT(context), DPL_OTHER, pc, AV7IS_THUMB); - break; - case AV7IS_THUMB: - pc += 4; - //g_armv7_context_define_encoding(context, - g_proc_context_push_drop_point(G_PROC_CONTEXT(context), DPL_OTHER, pc, AV7IS_ARM); - break; - default: - assert(0); - break; - } - - hfwibwo_no_pc: - - g_object_unref(G_OBJECT(op)); - -} - - -/****************************************************************************** -* * -* Paramètres : instr = instruction ARMv7 à traiter. * -* proc = représentation de l'architecture utilisée. * -* context = contexte associé à la phase de désassemblage. * -* format = acès aux données du binaire d'origine. * -* * -* Description : Complète un désassemblage accompli pour une instruction. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -void help_fetching_with_instruction_cb_n_z(GArchInstruction *instr, GArchProcessor *proc, GArmV7Context *context, GExeFormat *format) -{ - const mrange_t *range; /* Emplacementt d'instruction */ - virt_t pc; /* Position dans l'exécution */ - GImmOperand *op; /* Opérande numérique en place */ - uint32_t offset; /* Décallage encodé en dur */ - virt_t target; /* Adresse virtuelle visée */ - - range = g_arch_instruction_get_range(instr); - - pc = get_virt_addr(get_mrange_addr(range)); - - /** - * En mode Thumb, pc a pour valeur l'adresse courante plus 4. - */ - - pc += 4; - - op = G_IMM_OPERAND(g_arch_instruction_get_operand(instr, 1)); - - if (g_imm_operand_get_value(op, MDS_32_BITS_UNSIGNED, &offset)) - g_imm_operand_set_value(op, MDS_32_BITS_UNSIGNED, pc + offset); - - else assert(0); - - g_object_unref(G_OBJECT(op)); - - target = pc + offset; - - //g_armv7_context_define_encoding(context, target, AV7IS_THUMB); - g_proc_context_push_drop_point(G_PROC_CONTEXT(context), DPL_OTHER, target, AV7IS_THUMB); - -} - - -/****************************************************************************** -* * -* Paramètres : instr = instruction ARMv7 à traiter. * -* proc = représentation de l'architecture utilisée. * -* context = contexte associé à la phase de désassemblage. * -* format = acès aux données du binaire d'origine. * -* iset = type de jeu d'instructions courant. * -* * -* Description : Complète un désassemblage accompli pour une instruction. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -void help_fetching_with_instruction_ldr_literal_with_orig(GArchInstruction *instr, GArchProcessor *proc, GArmV7Context *context, GExeFormat *format, ArmV7InstrSet iset) -{ - const mrange_t *range; /* Emplacementt d'instruction */ - phys_t phys_pc; /* Position dans l'exécution */ - GArchOperand *op; /* Opérande de surcouche */ - uint32_t offset; /* Décallage encodé en dur */ - bool ret; /* Bilan d'une récupération */ - off_t val_offset; /* Position de valeur à lire */ - vmpa2t loaded_addr; /* Adresse de valeur chargée */ - mrange_t loaded_range; /* Espace de chargement */ - GBinContent *content; /* Contenu binaire à relire */ - uint32_t target; /* Adresse virtuelle visée */ - vmpa2t pos; /* Tête de lecture de valeur */ - VMPA_BUFFER(loc); /* Adresse au format texte */ - GPreloadInfo *info; /* Informations préchargées */ - GArchInstruction *loaded; /* Instruction de valeur */ - bool inserted; /* Bilan d'une insertion */ - char *desc; /* Description d'accompagnement*/ - GDbComment *comment; /* Définition de commentaire */ - GArchOperand *new; /* Instruction de ciblage */ - - /* Récupération de l'adresse visée par le chargement */ - - range = g_arch_instruction_get_range(instr); - - phys_pc = get_phy_addr(get_mrange_addr(range)); - - phys_pc &= ~3; - //phys_pc = (phys_pc + 3) & ~3; - - switch (iset) - { - case AV7IS_ARM: - phys_pc += 8; - break; - case AV7IS_THUMB: - phys_pc += 4; - break; - default: - assert(0); - break; - } - - g_arch_instruction_lock_operands(instr); - - op = _g_arch_instruction_get_operand(instr, 1); - assert(G_IS_IMM_OPERAND(op)); - - ret = g_imm_operand_get_value(G_IMM_OPERAND(op), MDS_32_BITS_UNSIGNED, &offset); - if (!ret) - { - assert(0); - g_object_unref(G_OBJECT(op)); - g_arch_instruction_unlock_operands(instr); - return; - } - - /* Transformations et conservation d'une position de chargement */ - - val_offset = phys_pc + offset; - - if (!g_exe_format_translate_offset_into_vmpa(format, val_offset, &loaded_addr)) - { - assert(0); - g_object_unref(G_OBJECT(op)); - g_arch_instruction_unlock_operands(instr); - return; - } - - init_mrange(&loaded_range, &loaded_addr, 4); - - /* Lecture de la valeur vers laquelle renvoyer */ - - content = g_binary_format_get_content(G_BIN_FORMAT(format)); - - copy_vmpa(&pos, &loaded_addr); - - ret = g_binary_content_read_u32(content, &pos, SRE_LITTLE /* FIXME */, &target); - g_object_unref(G_OBJECT(content)); - - if (!ret) - { - g_object_unref(G_OBJECT(op)); - g_arch_instruction_unlock_operands(instr); - return; - } - - /* Réalise l'intégration de la valeur chargée */ - - copy_vmpa(&pos, &loaded_addr); - - info = G_PRELOAD_INFO(context); - - loaded = g_raw_instruction_new_from_value(&pos, MDS_32_BITS_UNSIGNED, target); - - inserted = g_preload_info_add_instruction(info, loaded); - - if (inserted) - { - /* Commentaire associé */ - - vmpa2_virt_to_string(get_mrange_addr(range), MDS_32_BITS, loc, NULL); - asprintf(&desc, _("Value used @ %s"), loc); - - g_preload_info_lock_comments(info); - - comment = _g_preload_info_find_comment_at(info, &loaded_addr); - - if (comment != NULL) - { - g_db_comment_add_static_text(comment, "\n"); - g_db_comment_add_dynamic_text(comment, desc); - } - - else - { - comment = g_db_comment_new_inlined(&loaded_addr, BLF_HAS_CODE, false); - g_db_item_set_volatile(G_DB_ITEM(comment), true); - - g_db_comment_add_dynamic_text(comment, desc); - - _g_preload_info_add_comment(info, comment); - - } - - g_preload_info_unlock_comments(info); - - } - - /* Mise à jour de l'affichage et conclusion */ - - new = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, target); - _g_arch_instruction_replace_operand(instr, op, new); - - g_object_unref(G_OBJECT(op)); - g_arch_instruction_unlock_operands(instr); - - - - //exit(0); - - - - //target = pc + offset; - - - if (target & 0x1) - iset = AV7IS_THUMB; - //else - // iset = AV7IS_ARM; - - //g_armv7_context_define_encoding(context, target, AV7IS_THUMB); - g_proc_context_push_drop_point(G_PROC_CONTEXT(context), DPL_OTHER, target, iset); - - - //exit(0); - -} diff --git a/src/arch/arm/v7/fetch.h b/src/arch/arm/v7/fetch.h deleted file mode 100644 index ece4b42..0000000 --- a/src/arch/arm/v7/fetch.h +++ /dev/null @@ -1,112 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * fetch.h - prototypes pour les ajouts de sauts à traiter durant la phase de désassemblage - * - * Copyright (C) 2015-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_ARM_V7_FETCH_H -#define _ARCH_ARM_V7_FETCH_H - - -#include "context.h" -#include "../../instruction.h" - - - -/* Complète un désassemblage accompli pour une instruction. */ -void help_fetching_with_instruction_b_with_orig(GArchInstruction *, GArchProcessor *, GArmV7Context *, GExeFormat *, ArmV7InstrSet); - - -static inline void help_fetching_with_instruction_b_from_arm(GArchInstruction *ins, GArchProcessor *proc, GArmV7Context *ctx, GExeFormat *fmt) -{ - help_fetching_with_instruction_b_with_orig(ins, proc, ctx, fmt, AV7IS_ARM); -} - -static inline void help_fetching_with_instruction_b_from_thumb(GArchInstruction *ins, GArchProcessor *proc, GArmV7Context *ctx, GExeFormat *fmt) -{ - help_fetching_with_instruction_b_with_orig(ins, proc, ctx, fmt, AV7IS_THUMB); -} - - -/* Complète un désassemblage accompli pour une instruction. */ -void help_fetching_with_instruction_bl_with_orig(GArchInstruction *, GArchProcessor *, GArmV7Context *, GExeFormat *, ArmV7InstrSet); - - -static inline void help_fetching_with_instruction_bl_from_arm(GArchInstruction *ins, GArchProcessor *proc, GArmV7Context *ctx, GExeFormat *fmt) -{ - help_fetching_with_instruction_bl_with_orig(ins, proc, ctx, fmt, AV7IS_ARM); -} - -static inline void help_fetching_with_instruction_bl_from_thumb(GArchInstruction *ins, GArchProcessor *proc, GArmV7Context *ctx, GExeFormat *fmt) -{ - help_fetching_with_instruction_bl_with_orig(ins, proc, ctx, fmt, AV7IS_THUMB); -} - - -/* Complète un désassemblage accompli pour une instruction. */ -void help_fetching_with_instruction_blx_with_dest(GArchInstruction *, GArchProcessor *, GArmV7Context *, GExeFormat *, ArmV7InstrSet); - - -static inline void help_fetching_with_instruction_blx_from_arm(GArchInstruction *ins, GArchProcessor *proc, GArmV7Context *ctx, GExeFormat *fmt) -{ - help_fetching_with_instruction_blx_with_dest(ins, proc, ctx, fmt, AV7IS_THUMB); -} - -static inline void help_fetching_with_instruction_blx_from_thumb(GArchInstruction *ins, GArchProcessor *proc, GArmV7Context *ctx, GExeFormat *fmt) -{ - help_fetching_with_instruction_blx_with_dest(ins, proc, ctx, fmt, AV7IS_ARM); -} - - -/* Complète un désassemblage accompli pour une instruction. */ -void help_fetching_with_instruction_bx_with_orig(GArchInstruction *, GArchProcessor *, GArmV7Context *, GExeFormat *, ArmV7InstrSet); - - -static inline void help_fetching_with_instruction_bx_from_arm(GArchInstruction *ins, GArchProcessor *proc, GArmV7Context *ctx, GExeFormat *fmt) -{ - help_fetching_with_instruction_bx_with_orig(ins, proc, ctx, fmt, AV7IS_ARM); -} - -static inline void help_fetching_with_instruction_bx_from_thumb(GArchInstruction *ins, GArchProcessor *proc, GArmV7Context *ctx, GExeFormat *fmt) -{ - help_fetching_with_instruction_bx_with_orig(ins, proc, ctx, fmt, AV7IS_THUMB); -} - - -/* Complète un désassemblage accompli pour une instruction. */ -void help_fetching_with_instruction_cb_n_z(GArchInstruction *, GArchProcessor *, GArmV7Context *, GExeFormat *); - -/* Complète un désassemblage accompli pour une instruction. */ -void help_fetching_with_instruction_ldr_literal_with_orig(GArchInstruction *, GArchProcessor *, GArmV7Context *, GExeFormat *, ArmV7InstrSet); - - -static inline void help_fetching_with_instruction_ldr_literal_from_arm(GArchInstruction *ins, GArchProcessor *proc, GArmV7Context *ctx, GExeFormat *fmt) -{ - help_fetching_with_instruction_ldr_literal_with_orig(ins, proc, ctx, fmt, AV7IS_ARM); -} - -static inline void help_fetching_with_instruction_ldr_literal_from_thumb(GArchInstruction *ins, GArchProcessor *proc, GArmV7Context *ctx, GExeFormat *fmt) -{ - help_fetching_with_instruction_ldr_literal_with_orig(ins, proc, ctx, fmt, AV7IS_THUMB); -} - - - -#endif /* _ARCH_ARM_V7_FETCH_H */ diff --git a/src/arch/arm/v7/helpers.c b/src/arch/arm/v7/helpers.c deleted file mode 100644 index 4fa3667..0000000 --- a/src/arch/arm/v7/helpers.c +++ /dev/null @@ -1,275 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * helpers.c - aide à la mise en place des opérandes ARMv7 - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#include "helpers.h" - - -#include "register.h" -#include "../../register.h" -#include "../../immediate.h" -#include "../../../common/asm.h" -#include "../../../common/bconst.h" - - - -/****************************************************************************** -* * -* Paramètres : x = valeur sur 32 bits maximum à traiter. * -* shift = nombre de décallages visés. * -* * -* Description : Effectue une rotation vers la droit d'une valeur. * -* * -* Retour : Adresse de la structure mise en place. * -* * -* Remarques : Correspond à la pseudo fonction 'ROR_C'. * -* * -******************************************************************************/ - -GArchOperand *ror_armv7_imm(uint32_t x, unsigned int shift) -{ - GArchOperand *result; /* Opérande à faire remonter */ - uint32_t val32; /* Valeur sur 32 bits */ - - shift %= 32; - - val32 = (x >> shift) | (x << (32 - shift)); - - result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, val32); - - return result; - -} - - - - - - - - - - - - -#if 0 - -// Shift_C() -// ========= -(bits(N), bit) Shift_C(bits(N) value, SRType type, integer amount, bit carry_in) -assert !(type == SRType_RRX && amount != 1); -if amount == 0 then -(result, carry_out) = (value, carry_in); -else -case type of - -when SRType_LSL -(result, carry_out) = LSL_C(value, amount); - -when SRType_LSR -(result, carry_out) - -when SRType_ASR -(result, carry_out) - -when SRType_ROR -(result, carry_out) - -when SRType_RRX -(result, carry_out) -= LSR_C(value, amount); -= ASR_C(value, amount); -= ROR_C(value, amount); -= RRX_C(value, carry_in); - -#endif - - - - - - -/****************************************************************************** -* * -* Paramètres : value = valeur sur 32 bits maximum à traiter. * -* topbit = valeur du bit de poids fort manipulé. * -* size = taille de la valeur finale à constituer. * -* * -* Description : Crée un opérande de valeur immédiate avec extension de signe.* -* * -* Retour : Adresse de la structure mise en place. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArchOperand *sign_extend_armv7_imm(uint32_t value, bool topbit, unsigned int size) -{ - GArchOperand *result; /* Opérande à faire remonter */ - unsigned int msb; /* Position du premier bit à 1 */ - MemoryDataSize mds; /* Conversion de la taille */ - uint32_t val4; /* Valeur sur 4 bits */ - uint32_t val8; /* Valeur sur 8 bits */ - uint32_t val16; /* Valeur sur 16 bits */ - uint32_t val32; /* Valeur sur 32 bits */ - unsigned int i; /* Boucle de parcours */ - - result = NULL; - - topbit &= msb_32(value, &msb); - - switch (size) - { - -#define SIGN_EXTEND_CASE(sz) \ - case sz: \ - mds = MDS_ ## sz ## _BITS_SIGNED; \ - val ## sz = value; \ - if (topbit) \ - for (i = msb; i < sz; i++) \ - val ## sz |= (1 << i); \ - result = g_imm_operand_new_from_value(mds, val ## sz); \ - break; - - SIGN_EXTEND_CASE(4); - SIGN_EXTEND_CASE(8); - SIGN_EXTEND_CASE(16); - SIGN_EXTEND_CASE(32); - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : value = valeur sur 32 bits maximum à traiter. * -* * -* Description : Etend une valeur immédiate en mode 'Thumb' ARMv7. * -* * -* Retour : Adresse de la structure mise en place. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArchOperand *thumb_expand_armv7_imm(uint32_t value) -{ - GArchOperand *result; /* Opérande à faire remonter */ - uint8_t byte; /* Octet à reproduire */ - uint32_t val32; /* Valeur sur 32 bits */ - uint32_t unrotated; /* Transformation à décaller */ - - result = NULL; - - if (((value >> 10) & b11) == b00) - { - byte = value & 0xff; - - switch ((value >> 8) & b11) - { - case b00: - result = zero_extend_armv7_imm(byte, 32); - break; - - case b01: - if (byte == 0) return NULL; - val32 = byte << 16 | byte; - result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, val32); - break; - - case b10: - if (byte == 0) return NULL; - val32 = byte << 24 | byte << 8; - result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, val32); - break; - - case b11: - if (byte == 0) return NULL; - val32 = byte << 24 | byte << 16 | byte << 8 | byte; - result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, val32); - break; - - } - - } - else - { - unrotated = 1 << 7 | (value & 0x3f); - result = ror_armv7_imm(unrotated, (value >> 7) & 0x1f); - } - - return result; - -} - - - - - - -/****************************************************************************** -* * -* Paramètres : value = valeur sur 32 bits maximum à traiter. * -* size = taille de la valeur finale à constituer. * -* * -* Description : Réalise un simple transtypage de valeur entière. * -* * -* Retour : Adresse de la structure mise en place. * -* * -* Remarques : Correspond à la pseudo fonction 'ZeroExtend'. * -* * -******************************************************************************/ - -GArchOperand *zero_extend_armv7_imm(uint32_t value, unsigned int size) -{ - GArchOperand *result; /* Opérande à faire remonter */ - MemoryDataSize mds; /* Conversion de la taille */ - uint32_t val4; /* Valeur sur 4 bits */ - uint32_t val8; /* Valeur sur 8 bits */ - uint32_t val16; /* Valeur sur 16 bits */ - uint32_t val32; /* Valeur sur 32 bits */ - - result = NULL; - - switch (size) - { - -#define ZERO_EXTEND_CASE(sz) \ - case sz: \ - mds = MDS_ ## sz ## _BITS_UNSIGNED; \ - val ## sz = value; \ - result = g_imm_operand_new_from_value(mds, val ## sz); \ - break; - - ZERO_EXTEND_CASE(4); - ZERO_EXTEND_CASE(8); - ZERO_EXTEND_CASE(16); - ZERO_EXTEND_CASE(32); - - } - - return result; - -} diff --git a/src/arch/arm/v7/helpers.h b/src/arch/arm/v7/helpers.h deleted file mode 100644 index aed7f3f..0000000 --- a/src/arch/arm/v7/helpers.h +++ /dev/null @@ -1,439 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * helpers.h - prototypes pour l'aide à la mise en place des opérandes ARMv7 - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_ARM_V7_HELPERS_H -#define _ARCH_ARM_V7_HELPERS_H - - -#include "cregister.h" -#include "pseudo.h" -#include "operands/coproc.h" -#include "operands/estate.h" -#include "operands/limitation.h" -#include "operands/maccess.h" -#include "operands/offset.h" -#include "operands/reglist.h" -#include "operands/rotation.h" -#include "operands/shift.h" -#include "../register.h" -#include "../../operand.h" - - - - - -#define BarrierLimitation(opt) \ - ({ \ - GArchOperand *__result; \ - __result = g_armv7_limitation_operand_new(opt); \ - __result; \ - }) - - -#define BitDiff(msb, lsb) \ - ({ \ - GArchOperand *__result; \ - uint32_t __width; \ - __width = g_imm_operand_get_raw_value(G_IMM_OPERAND(msb)); \ - __width -= g_imm_operand_get_raw_value(G_IMM_OPERAND(lsb)); \ - __width += 1; \ - __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __width); \ - __result; \ - }) - - -#define BuildImm8(val) \ - ({ \ - GArchOperand *__result; \ - __result = g_imm_operand_new_from_value(MDS_8_BITS_UNSIGNED, (uint8_t)val); \ - __result; \ - }) - - -#define BuildImm16(val) \ - ({ \ - GArchOperand *__result; \ - __result = g_imm_operand_new_from_value(MDS_16_BITS_UNSIGNED, (uint16_t)val); \ - __result; \ - }) - - -#define CoProcessor(idx) \ - ({ \ - GArchOperand *__result; \ - __result = g_armv7_coproc_operand_new(idx); \ - __result; \ - }) - - -#define CRegister(idx) \ - ({ \ - GArchOperand *__result; \ - GArmV7CRegister *__reg; \ - __reg = g_armv7_cregister_new(idx); \ - if (__reg == NULL) \ - __result = NULL; \ - else \ - __result = g_register_operand_new(G_ARCH_REGISTER(__reg)); \ - __result; \ - }) - - -#define IncWidth(widthm1) \ - ({ \ - GArchOperand *__result; \ - uint32_t __width; \ - __width = widthm1 + 1; \ - __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __width); \ - __result; \ - }) - - -#define DecodeImmShift(type, imm5) \ - ({ \ - GArchOperand *__result; \ - SRType __shift_t; \ - uint32_t __shift_n; \ - GArchOperand *__op_n; \ - if (!armv7_decode_imm_shift(type, imm5, &__shift_t, &__shift_n)) \ - __result = NULL; \ - else \ - { \ - __op_n = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __shift_n); \ - __result = g_armv7_shift_operand_new(__shift_t, __op_n); \ - } \ - __result; \ - }) - - -#define EndianState(big) \ - ({ \ - GArchOperand *__result; \ - __result = g_armv7_endian_operand_new(big); \ - __result; \ - }) - - -#define MakeMemoryAccess(base, off, shift, index, add, wback) \ - ({ \ - GArchOperand *__result; \ - GArchOperand *__offset; \ - if (off != NULL) \ - __offset = g_armv7_offset_operand_new(add, off); \ - else \ - __offset = NULL; \ - __result = g_armv7_maccess_operand_new(base, __offset, shift, index, wback); \ - __result; \ - }) - - -#define NextRegister(prev) \ - ({ \ - GRegisterOperand *__prev_op; \ - GArchRegister *__reg; \ - uint8_t __id; \ - __prev_op = G_REGISTER_OPERAND(prev); \ - __reg = g_register_operand_get_register(__prev_op); \ - __id = g_arm_register_get_index(G_ARM_REGISTER(__reg)); \ - Register(__id + 1); \ - }) - - -#define RawValue(val) \ - ({ \ - GArchOperand *__result; \ - __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, (uint32_t)val); \ - __result; \ - }) - - -#define Register(idx) \ - ({ \ - GArchOperand *__result; \ - GArmV7Register *__reg; \ - __reg = g_armv7_register_new(idx); \ - if (__reg == NULL) \ - __result = NULL; \ - else \ - __result = g_register_operand_new(G_ARCH_REGISTER(__reg)); \ - __result; \ - }) - - -#define RegisterShift(shift_t, rs) \ - ({ \ - GArchOperand *__result; \ - GArchOperand *__reg; \ - __reg = Register(rs); \ - if (__reg == NULL) \ - __result = NULL; \ - else \ - __result = g_armv7_shift_operand_new(shift_t, __reg); \ - __result; \ - }) - - -#define Rotation(val5) \ - ({ \ - GArchOperand *__result; \ - uint8_t __rot; \ - GArchOperand *__rot_op; \ - __rot = val5; \ - __rot_op = g_imm_operand_new_from_value(MDS_8_BITS_UNSIGNED, __rot); \ - __result = g_armv7_rotation_operand_new(__rot_op); \ - if (__result == NULL) \ - g_object_unref(G_OBJECT(__rot_op)); \ - __result; \ - }) - - -#define UInt(val) \ - ({ \ - GArchOperand *__result; \ - __result = g_imm_operand_new_from_value(MDS_8_BITS_UNSIGNED, (uint8_t)val); \ - __result; \ - }) - - - - -//#define DecodeImmShift(raw_type, raw_imm5); -//g_armv7_shift_operand_new(SRType type, GArchOperand *value) - - - -//#define MakeMemoryAccess(base, off, shift, index, add, wback) NULL - -//g_armv7_maccess_operand_new(GArchOperand *base, GArchOperand *offset, GArchOperand *shift, bool indexed, bool writeb) - -//g_armv7_offset_operand_new(add, off) - - - - -//////////////////// - -#define Imm16(imm16) \ - ({ \ - GArchOperand *__result; \ - __result = g_imm_operand_new_from_value(MDS_16_BITS_UNSIGNED, (uint16_t)imm16); \ - __result; \ - }) - -#define ARMExpandImm_C(imm12, c) \ - ({ \ - GArchOperand *__result; \ - uint32_t __val; \ - if (armv7_arm_expand_imm_c(imm12, (bool []) { c }, &__val)) \ - __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __val); \ - else \ - __result = NULL; \ - __result; \ - }) - -#define ARMExpandImm(imm12) \ - ({ \ - GArchOperand *__result; \ - uint32_t __val; \ - if (armv7_arm_expand_imm(imm12, &__val)) \ - __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __val); \ - else \ - __result = NULL; \ - __result; \ - }) - -#define ThumbExpandImm_C(imm12, c) \ - ({ \ - GArchOperand *__result; \ - uint32_t __val; \ - if (armv7_thumb_expand_imm_c(imm12, (bool []) { c }, &__val)) \ - __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __val); \ - else \ - __result = NULL; \ - __result; \ - }) - -#define ThumbExpandImm(imm12) \ - ({ \ - GArchOperand *__result; \ - uint32_t __val; \ - if (armv7_thumb_expand_imm(imm12, &__val)) \ - __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __val); \ - else \ - __result = NULL; \ - __result; \ - }) - - - - - - - -#define DecodeImmShiftValue(imm5) \ - ({ \ - GArchOperand *__result; \ - uint32_t __shift_n; \ - if (!armv7_decode_imm_shift(0, imm5, (SRType []) { 0 }, &__shift_n)) \ - __result = NULL; \ - else \ - __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __shift_n); \ - __result; \ - }) - - -#if 0 -// DecodeRegShift() -// ================ -SRType DecodeRegShift(bits(2) type) -case type of -when '00' shift_t = SRType_LSL; -when '01' shift_t = SRType_LSR; -when '10' shift_t = SRType_ASR; -when '11' shift_t = SRType_ROR; -return shift_t; -#endif - - - -#define ZeroExtend(x, i) \ - ({ \ - MemoryDataSize __mds; \ - uint ## i ## _t __val; \ - __mds = MDS_ ## i ## _BITS_UNSIGNED; \ - __val = armv7_zero_extend(x, 0/**/, i); \ - g_imm_operand_new_from_value(__mds, __val); \ - }) - - - -#define Zeros(i) \ - ({ \ - MemoryDataSize __mds; \ - uint ## i ## _t __val; \ - __mds = MDS_ ## i ## _BITS_UNSIGNED; \ - __val = 0; \ - g_imm_operand_new_from_value(__mds, __val); \ - }) - - - - - - - - -/** - * Glue purement interne. - */ - - -#define MakeAccessOffset(add, off) \ - g_armv7_offset_operand_new(add, off) - - -#define MakeShiftedMemoryAccess(base, off, shift, wr) \ - g_armv7_maccess_operand_new(base, off, shift, wr) - - -#define _MakeMemoryAccess(base, off, wr) \ - MakeShiftedMemoryAccess(base, off, NULL, wr) - -/* -#define MakeMemoryAccess(base, off, add, wr) \ - ({ \ - GArchOperand *__off; \ - __off = MakeAccessOffset(add, off); \ - _MakeMemoryAccess(base, __off, wr); \ - }) -*/ - -#define MakeMemoryNotIndexed(base, wr) \ - _MakeMemoryAccess(base, NULL, wr) - - - - - - - - -// type == '10', pas 2 ! (FIXME) -#define FixedShift(type, imm5) \ - ({ \ - GArchOperand *__result; \ - uint32_t __shift_n; \ - __shift_n = imm5; \ - __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __shift_n); \ - __result; \ - }) - - - - - -/** - * Glue purement interne pour les listes de registres. - */ - -#define RegistersList(mask) \ - ({ \ - GArchOperand *__result; \ - __result = g_armv7_reglist_operand_new(); \ - if (!g_armv7_reglist_load_registers(G_ARMV7_REGLIST_OPERAND(__result), mask)) \ - { \ - g_object_unref(G_OBJECT(__result)); \ - __result = NULL; \ - } \ - __result; \ - }) - - -#define ListFromRegister(regop) \ - ({ \ - GArchOperand *__result; \ - GArmV7Register *__reg; \ - __result = g_armv7_reglist_operand_new(); \ - __reg = G_ARMV7_REGISTER(regop); \ - g_armv7_reglist_add_register(G_ARMV7_REGLIST_OPERAND(__result), __reg); \ - __result; \ - }) - - - - -/* Effectue une rotation vers la droit d'une valeur. */ -GArchOperand *ror_armv7_imm(uint32_t, unsigned int); - -/* Crée un opérande de valeur immédiate avec extension de signe. */ -GArchOperand *sign_extend_armv7_imm(uint32_t, bool, unsigned int); - -/* Etend une valeur immédiate en mode 'Thumb' ARMv7. */ -GArchOperand *thumb_expand_armv7_imm(uint32_t); - -/* Réalise un simple transtypage de valeur entière. */ -GArchOperand *zero_extend_armv7_imm(uint32_t, unsigned int); - - - -#endif /* _ARCH_ARM_V7_HELPERS_H */ diff --git a/src/arch/arm/v7/instruction.c b/src/arch/arm/v7/instruction.c deleted file mode 100644 index d9e4275..0000000 --- a/src/arch/arm/v7/instruction.c +++ /dev/null @@ -1,284 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * instruction.c - gestion des instructions ARMv7 - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#include "instruction.h" - - -#include <assert.h> -#ifndef NDEBUG -# include <string.h> -#endif - - -#include "../instruction-int.h" - - - -/* Définition d'une instruction d'architecture ARMv7 (instance) */ -struct _GArmV7Instruction -{ - GArmInstruction parent; /* Instance parente */ - - char encoding; /* Encodage de l'instruction */ - - bool setflags; /* Mise à jour des drapeaux */ - -}; - - -/* Définition d'une instruction d'architecture ARMv7 (classe) */ -struct _GArmV7InstructionClass -{ - GArmInstructionClass parent; /* Classe parente */ - -}; - - -/* Initialise la classe des instructions ARMv7. */ -static void g_armv7_instruction_class_init(GArmV7InstructionClass *); - -/* Initialise une instance d'instruction ARMv7. */ -static void g_armv7_instruction_init(GArmV7Instruction *); - -/* Supprime toutes les références externes. */ -static void g_armv7_instruction_dispose(GArmV7Instruction *); - -/* Procède à la libération totale de la mémoire. */ -static void g_armv7_instruction_finalize(GArmV7Instruction *); - -/* Indique l'encodage d'une instruction de façon détaillée. */ -static const char *g_armv7_instruction_get_encoding(const GArmV7Instruction *); - - -/* Indique le type défini pour une représentation d'une instruction ARMv7. */ -G_DEFINE_TYPE(GArmV7Instruction, g_armv7_instruction, G_TYPE_ARM_INSTRUCTION); - - -/****************************************************************************** -* * -* Paramètres : klass = classe à initialiser. * -* * -* Description : Initialise la classe des instructions ARMv7. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_instruction_class_init(GArmV7InstructionClass *klass) -{ - GObjectClass *object_class; /* Autre version de la classe */ - GArchInstructionClass *instr; /* Encore une autre vision... */ - - object_class = G_OBJECT_CLASS(klass); - instr = G_ARCH_INSTRUCTION_CLASS(klass); - - object_class->dispose = (GObjectFinalizeFunc/* ! */)g_armv7_instruction_dispose; - object_class->finalize = (GObjectFinalizeFunc)g_armv7_instruction_finalize; - - instr->get_encoding = (get_instruction_encoding_fc)g_armv7_instruction_get_encoding; - -} - - -/****************************************************************************** -* * -* Paramètres : instr = instance à initialiser. * -* * -* Description : Initialise une instance d'instruction ARMv7. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_instruction_init(GArmV7Instruction *instr) -{ - -} - - -/****************************************************************************** -* * -* Paramètres : instr = instance d'objet GLib à traiter. * -* * -* Description : Supprime toutes les références externes. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_instruction_dispose(GArmV7Instruction *instr) -{ - G_OBJECT_CLASS(g_armv7_instruction_parent_class)->dispose(G_OBJECT(instr)); - -} - - -/****************************************************************************** -* * -* Paramètres : instr = instance d'objet GLib à traiter. * -* * -* Description : Procède à la libération totale de la mémoire. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_instruction_finalize(GArmV7Instruction *instr) -{ - G_OBJECT_CLASS(g_armv7_instruction_parent_class)->finalize(G_OBJECT(instr)); - -} - - -/****************************************************************************** -* * -* Paramètres : keyword = définition du nom humaine de l'instruction. * -* * -* Description : Crée une instruction pour l'architecture ARMv7. * -* * -* Retour : Adresse de la structure mise en place. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArchInstruction *g_armv7_instruction_new(const char *keyword) -{ - GArchInstruction *result; /* Structure à retourner */ - - result = g_object_new(G_TYPE_ARMV7_INSTRUCTION, NULL); - - G_ARM_INSTRUCTION(result)->keyword = keyword; - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : instr = instruction quelconque à consulter. * -* * -* Description : Indique l'encodage d'une instruction de façon détaillée. * -* * -* Retour : Description humaine de l'encodage utilisé. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static const char *g_armv7_instruction_get_encoding(const GArmV7Instruction *instr) -{ - const char *result; /* Description à retourner */ - - switch (instr->encoding) - { - case 't': - result = "Thumb/16"; - break; - - case 'T': - result = "Thumb/32"; - break; - - default: - result = "ARM"; - break; - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : instr = instruction quelconque à modifier. * -* encoding = encodage de l'instruction. * -* * -* Description : Précise l'encodage d'une instruction ARMv7 dans le détail. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -void g_armv7_instruction_set_encoding(GArmV7Instruction *instr, const char *encoding) -{ - assert(strlen(encoding) == 1); - assert(encoding[0] == 'A' || encoding[0] == 'T' || encoding[0] == 't'); - - instr->encoding = encoding[0]; - -} - - -/****************************************************************************** -* * -* Paramètres : instr = instruction ARMv7 à mettre à jour. * -* set = statut à enregistrer. * -* * -* Description : Définit si une instruction ARMv7 met à jour les drapeaux. * -* * -* Retour : Bilan de l'opération. * -* * -* Remarques : - * -* * -******************************************************************************/ - -bool g_armv7_instruction_define_setflags(GArmV7Instruction *instr, bool set) -{ - instr->setflags = set; - - return true; - -} - - -/****************************************************************************** -* * -* Paramètres : instr = instruction ARMv7 à consulter. * -* * -* Description : Indique si une instruction ARMv7 met à jour les drapeaux. * -* * -* Retour : Statut des incidences de l'instruction. * -* * -* Remarques : - * -* * -******************************************************************************/ - -bool g_armv7_instruction_get_setflags(const GArmV7Instruction *instr) -{ - return instr->setflags; - -} diff --git a/src/arch/arm/v7/instruction.h b/src/arch/arm/v7/instruction.h deleted file mode 100644 index 4b3c006..0000000 --- a/src/arch/arm/v7/instruction.h +++ /dev/null @@ -1,69 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * instruction.h - prototypes pour la gestion des instructions ARMv7 - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_ARM_V7_INSTRUCTION_H -#define _ARCH_ARM_V7_INSTRUCTION_H - - -#include <glib-object.h> -#include <stdbool.h> -#include <stdint.h> - - -#include "../../instruction.h" - - - -#define G_TYPE_ARMV7_INSTRUCTION g_armv7_instruction_get_type() -#define G_ARMV7_INSTRUCTION(obj) (G_TYPE_CHECK_INSTANCE_CAST((obj), g_armv7_instruction_get_type(), GArmV7Instruction)) -#define G_IS_ARMV7_INSTRUCTION(obj) (G_TYPE_CHECK_INSTANCE_TYPE((obj), g_armv7_instruction_get_type())) -#define G_ARMV7_INSTRUCTION_CLASS(klass) (G_TYPE_CHECK_CLASS_CAST((klass), G_TYPE_ARMV7_INSTRUCTION, GArmV7InstructionClass)) -#define G_IS_ARMV7_INSTRUCTION_CLASS(klass) (G_TYPE_CHECK_CLASS_TYPE((klass), G_TYPE_ARMV7_INSTRUCTION)) -#define G_ARMV7_INSTRUCTION_GET_CLASS(obj) (G_TYPE_INSTANCE_GET_CLASS((obj), G_TYPE_ARMV7_INSTRUCTION, GArmV7InstructionClass)) - - -/* Définition d'une instruction d'architecture ARMv7 (instance) */ -typedef struct _GArmV7Instruction GArmV7Instruction; - -/* Définition d'une instruction d'architecture ARMv7 (classe) */ -typedef struct _GArmV7InstructionClass GArmV7InstructionClass; - - -/* Indique le type défini pour une représentation d'une instruction ARMv7. */ -GType g_armv7_instruction_get_type(void); - -/* Crée une instruction pour l'architecture ARMv7. */ -GArchInstruction *g_armv7_instruction_new(const char *); - -/* Précise l'encodage d'une instruction ARMv7 dans le détail. */ -void g_armv7_instruction_set_encoding(GArmV7Instruction *, const char *); - -/* Définit si une instruction ARMv7 met à jour les drapeaux. */ -bool g_armv7_instruction_define_setflags(GArmV7Instruction *, bool); - -/* Indique si une instruction ARMv7 met à jour les drapeaux. */ -bool g_armv7_instruction_get_setflags(const GArmV7Instruction *); - - - -#endif /* _ARCH_ARM_V7_INSTRUCTION_H */ diff --git a/src/arch/arm/v7/link.c b/src/arch/arm/v7/link.c deleted file mode 100644 index 68cde7b..0000000 --- a/src/arch/arm/v7/link.c +++ /dev/null @@ -1,114 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * link.c - édition des liens après la phase de désassemblage ARM v7 - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#include "link.h" - - -#include <assert.h> - - -#include "operands/reglist.h" -#include "../register.h" - - - -/****************************************************************************** -* * -* Paramètres : instr = instruction ARM à traiter. * -* proc = représentation de l'architecture utilisée. * -* context = contexte associé à la phase de désassemblage. * -* format = acès aux données du binaire d'origine. * -* * -* Description : Encadre les sauts à partir de registres ARMv7. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -void handle_armv7_conditional_branch_from_register(GArchInstruction *instr, GArchProcessor *proc, GProcContext *context, GExeFormat *format) -{ - GArchOperand *op; /* Opérande numérique en place */ - GArmRegister *reg; /* Registre matériel manipulé */ - - op = g_arch_instruction_get_operand(instr, 0); - assert(G_IS_REGISTER_OPERAND(op)); - - reg = G_ARM_REGISTER(g_register_operand_get_register(G_REGISTER_OPERAND(op))); - - if (g_arm_register_get_index(reg) == 14 /* lr */) - g_arch_instruction_set_flag(instr, AIF_RETURN_POINT); - - else - g_arch_instruction_set_flag(instr, AIF_RETURN_POINT); /* FIXME : jump inconnu ! */ - - g_object_unref(G_OBJECT(reg)); - - g_object_unref(G_OBJECT(op)); - -} - - -/****************************************************************************** -* * -* Paramètres : instr = instruction ARM à traiter. * -* proc = représentation de l'architecture utilisée. * -* context = contexte associé à la phase de désassemblage. * -* format = acès aux données du binaire d'origine. * -* * -* Description : Détecte les fins de procédures à base d'instructions 'pop'. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -void handle_armv7_return_from_pop(GArchInstruction *instr, GArchProcessor *proc, GProcContext *context, GExeFormat *format) -{ - GArchOperand *op; /* Opérande numérique en place */ - GArmV7RegListOperand *reglist; /* Autre version de l'instance */ - size_t count; /* Nombre de registres présents*/ - size_t i; /* Boucle de parcours */ - GArmRegister *reg; /* Registre matériel manipulé */ - - op = g_arch_instruction_get_operand(instr, 0); - assert(G_IS_ARMV7_REGLIST_OPERAND(op)); - - reglist = G_ARMV7_REGLIST_OPERAND(op); - - count = g_armv7_reglist_count_registers(reglist); - - for (i = 0; i < count; i++) - { - reg = G_ARM_REGISTER(g_armv7_reglist_operand_get_register(reglist, i)); - - if (g_arm_register_get_index(reg) == 15 /* pc */) - g_arch_instruction_set_flag(instr, AIF_RETURN_POINT); - - } - - g_object_unref(G_OBJECT(op)); - -} diff --git a/src/arch/arm/v7/link.h b/src/arch/arm/v7/link.h deleted file mode 100644 index d4e2a60..0000000 --- a/src/arch/arm/v7/link.h +++ /dev/null @@ -1,41 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * link.h - prototypes pour l'édition des liens après la phase de désassemblage ARM v7 - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_ARM_V7_LINK_H -#define _ARCH_ARM_V7_LINK_H - - -#include "context.h" -#include "../../instruction.h" - - - -/* Encadre les sauts à partir de registres ARMv7. */ -void handle_armv7_conditional_branch_from_register(GArchInstruction *, GArchProcessor *, GProcContext *, GExeFormat *); - -/* Détecte les fins de procédures à base d'instructions 'pop'. */ -void handle_armv7_return_from_pop(GArchInstruction *, GArchProcessor *, GProcContext *, GExeFormat *); - - - -#endif /* _ARCH_ARM_V7_LINK_H */ diff --git a/src/arch/arm/v7/opcodes/Makefile.am b/src/arch/arm/v7/opcodes/Makefile.am deleted file mode 100644 index fb00143..0000000 --- a/src/arch/arm/v7/opcodes/Makefile.am +++ /dev/null @@ -1,26 +0,0 @@ - -# Initialement, ce Makefile est conçu sans définition de am__depfiles_maybe. -# Est-ce parce que GENERATED_FILES est vide et qu'il n'y a donc pas de code -# source ? En tout cas, au premier écrasement de gencode.mk, tous les fichiers -# sont regénérés, et am__depfiles_maybe apparaît enfin. Mais trop tard : -# des fichiers .Plo sont attendus mais non créés par l'ancien Makefile. -# On force les choses ici. -am__depfiles_maybe = depfiles - -include gencode.mk - -noinst_LTLIBRARIES = libarcharmv7opcodes.la - -libarcharmv7opcodes_la_SOURCES = $(GENERATED_FILES) - -libarcharmv7opcodes_la_LIBADD = - -libarcharmv7opcodes_la_CFLAGS = $(AM_CFLAGS) - - -AM_CPPFLAGS = $(LIBGTK_CFLAGS) $(LIBXML_CFLAGS) - -AM_CFLAGS = $(DEBUG_CFLAGS) $(WARNING_FLAGS) $(COMPLIANCE_FLAGS) - - -EXTRA_DIST = opcodes_tmp_arm.h opcodes_tmp_simd.h opcodes_tmp_thumb_16.h opcodes_tmp_thumb_32.h diff --git a/src/arch/arm/v7/opcodes/opcodes_tmp_arm.h b/src/arch/arm/v7/opcodes/opcodes_tmp_arm.h deleted file mode 100644 index 4106cbd..0000000 --- a/src/arch/arm/v7/opcodes/opcodes_tmp_arm.h +++ /dev/null @@ -1,56 +0,0 @@ -#ifndef arm_def_tmp_h -#define arm_def_tmp_h -#define armv7_read_arm_instr_cps_arm(r) NULL -#define armv7_read_arm_instr_eret(r) NULL -#define armv7_read_arm_instr_hvc(r) NULL -#define armv7_read_arm_instr_isb(r) NULL -#define armv7_read_arm_instr_ldc_ldc2_immediate(r) NULL -#define armv7_read_arm_instr_ldc_ldc2_literal(r) NULL -#define armv7_read_arm_instr_ldmda_ldmfa(r) NULL -#define armv7_read_arm_instr_ldmdb_ldmea(r) NULL -#define armv7_read_arm_instr_ldm_exception_return(r) NULL -#define armv7_read_arm_instr_ldmib_ldmed(r) NULL -#define armv7_read_arm_instr_ldm_ldmia_ldmfd_arm(r) NULL -#define armv7_read_arm_instr_ldm_user_registers(r) NULL -#define armv7_read_arm_instr_mrs(r) NULL -#define armv7_read_arm_instr_mrs_banked_register(r) NULL -#define armv7_read_arm_instr_msr_banked_register(r) NULL -#define armv7_read_arm_instr_msr_immediate_a8(r) NULL -#define armv7_read_arm_instr_msr_immediate_b9(r) NULL -#define armv7_read_arm_instr_msr_register_a8(r) NULL -#define armv7_read_arm_instr_msr_register_b9(r) NULL -#define armv7_read_arm_instr_pkh(r) NULL -#define armv7_read_arm_instr_pld_literal(r) NULL -#define armv7_read_arm_instr_pld_pldw_immediate(r) NULL -#define armv7_read_arm_instr_pld_pldw_register(r) NULL -#define armv7_read_arm_instr_pli_immediate_literal(r) NULL -#define armv7_read_arm_instr_pli_register(r) NULL -#define armv7_read_arm_instr_rfe(r) NULL -#define armv7_read_arm_instr_smc_previously_smi(r) NULL -#define armv7_read_arm_instr_smlabb_smlabt_smlatb_smlatt(r) NULL -#define armv7_read_arm_instr_smlalbb_smlalbt_smlaltb_smlaltt(r) NULL -#define armv7_read_arm_instr_smlawb_smlawt(r) NULL -#define armv7_read_arm_instr_smulbb_smulbt_smultb_smultt(r) NULL -#define armv7_read_arm_instr_smulwb_smulwt(r) NULL -#define armv7_read_arm_instr_smusd(r) NULL -#define armv7_read_arm_instr_srs_arm(r) NULL -#define armv7_read_arm_instr_ssat(r) NULL -#define armv7_read_arm_instr_ssat16(r) NULL -#define armv7_read_arm_instr_ssax(r) NULL -#define armv7_read_arm_instr_ssub16(r) NULL -#define armv7_read_arm_instr_ssub8(r) NULL -#define armv7_read_arm_instr_stc_stc2(r) NULL -#define armv7_read_arm_instr_stmda_stmed(r) NULL -#define armv7_read_arm_instr_stmdb_stmfd(r) NULL -#define armv7_read_arm_instr_stmib_stmfa(r) NULL -#define armv7_read_arm_instr_stm_stmia_stmea(r) NULL -#define armv7_read_arm_instr_stm_user_registers(r) NULL -#define armv7_read_arm_instr_sub_register_shifted_register(r) NULL -#define armv7_read_arm_instr_sxtab(r) NULL -#define armv7_read_arm_instr_sxtab16(r) NULL -#define armv7_read_arm_instr_sxtah(r) NULL -#define armv7_read_arm_instr_sxtb(r) NULL -#define armv7_read_arm_instr_sxtb16(r) NULL -#define armv7_read_arm_instr_sxth(r) NULL -#define armv7_read_arm_instr_wfe(r) NULL -#endif diff --git a/src/arch/arm/v7/opcodes/opcodes_tmp_simd.h b/src/arch/arm/v7/opcodes/opcodes_tmp_simd.h deleted file mode 100644 index 1d7023e..0000000 --- a/src/arch/arm/v7/opcodes/opcodes_tmp_simd.h +++ /dev/null @@ -1,138 +0,0 @@ -#ifndef simd_def_tmp_h -#define simd_def_tmp_h -#define armv7_read_simd_instr_vaba_vabal(r, a) NULL -#define armv7_read_simd_instr_vabd_floating_point(r, a) NULL -#define armv7_read_simd_instr_vabd_vabdl_integer(r, a) NULL -#define armv7_read_simd_instr_vabs(r, a) NULL -#define armv7_read_simd_instr_vacge_vacgt_vacle_vaclt(r, a) NULL -#define armv7_read_simd_instr_vadd_floating_point(r, a) NULL -#define armv7_read_simd_instr_vaddhn(r, a) NULL -#define armv7_read_simd_instr_vadd_integer(r, a) NULL -#define armv7_read_simd_instr_vaddl_vaddw(r, a) NULL -#define armv7_read_simd_instr_vand_register(r, a) NULL -#define armv7_read_simd_instr_vbic_immediate(r, a) NULL -#define armv7_read_simd_instr_vbic_register(r, a) NULL -#define armv7_read_simd_instr_vbif_vbit_vbsl(r, a) NULL -#define armv7_read_simd_instr_vceq_immediate_0(r, a) NULL -#define armv7_read_simd_instr_vceq_register(r, a) NULL -#define armv7_read_simd_instr_vcge_immediate_0(r, a) NULL -#define armv7_read_simd_instr_vcge_register(r, a) NULL -#define armv7_read_simd_instr_vcgt_immediate_0(r, a) NULL -#define armv7_read_simd_instr_vcgt_register(r, a) NULL -#define armv7_read_simd_instr_vcle_immediate_0(r, a) NULL -#define armv7_read_simd_instr_vcls(r, a) NULL -#define armv7_read_simd_instr_vclt_immediate_0(r, a) NULL -#define armv7_read_simd_instr_vclz(r, a) NULL -#define armv7_read_simd_instr_vcmp_vcmpe(r, a) NULL -#define armv7_read_simd_instr_vcnt(r, a) NULL -#define armv7_read_simd_instr_vcvt_between_double_precision_and_single_precision(r, a) NULL -#define armv7_read_simd_instr_vcvt_between_floating_point_and_fixed_point_advanced_simd(r, a) NULL -#define armv7_read_simd_instr_vcvt_between_floating_point_and_fixed_point_floating_point(r, a) NULL -#define armv7_read_simd_instr_vcvtb_vcvtt(r, a) NULL -#define armv7_read_simd_instr_vcvt_vcvtr_between_floating_point_and_integer_floating_point(r, a) NULL -#define armv7_read_simd_instr_vdiv(r, a) NULL -#define armv7_read_simd_instr_vdup_arm_core_register(r, a) NULL -#define armv7_read_simd_instr_vdup_scalar(r, a) NULL -#define armv7_read_simd_instr_veor(r, a) NULL -#define armv7_read_simd_instr_vext(r, a) NULL -#define armv7_read_simd_instr_vfma_vfms(r, a) NULL -#define armv7_read_simd_instr_vfnma_vfnms(r, a) NULL -#define armv7_read_simd_instr_vhadd_vhsub(r, a) NULL -#define armv7_read_simd_instr_vld1_multiple_single_elements(r, a) NULL -#define armv7_read_simd_instr_vld1_single_element_to_all_lanes(r, a) NULL -#define armv7_read_simd_instr_vld1_single_element_to_one_lane(r, a) NULL -#define armv7_read_simd_instr_vld2_multiple_2_element_structures(r, a) NULL -#define armv7_read_simd_instr_vld2_single_2_element_structure_to_all_lanes(r, a) NULL -#define armv7_read_simd_instr_vld2_single_2_element_structure_to_one_lane(r, a) NULL -#define armv7_read_simd_instr_vld3_multiple_3_element_structures(r, a) NULL -#define armv7_read_simd_instr_vld3_single_3_element_structure_to_all_lanes(r, a) NULL -#define armv7_read_simd_instr_vld3_single_3_element_structure_to_one_lane(r, a) NULL -#define armv7_read_simd_instr_vld4_multiple_4_element_structures(r, a) NULL -#define armv7_read_simd_instr_vld4_single_4_element_structure_to_all_lanes(r, a) NULL -#define armv7_read_simd_instr_vld4_single_4_element_structure_to_one_lane(r, a) NULL -#define armv7_read_simd_instr_vldm(r, a) NULL -#define armv7_read_simd_instr_vldr(r, a) NULL -#define armv7_read_simd_instr_vmax_vmin_floating_point(r, a) NULL -#define armv7_read_simd_instr_vmax_vmin_integer(r, a) NULL -#define armv7_read_simd_instr_vmla_vmlal_vmls_vmlsl_by_scalar(r, a) NULL -#define armv7_read_simd_instr_vmla_vmlal_vmls_vmlsl_integer(r, a) NULL -#define armv7_read_simd_instr_vmla_vmls_floating_point(r, a) NULL -#define armv7_read_simd_instr_vmov_arm_core_register_to_scalar(r, a) NULL -#define armv7_read_simd_instr_vmov_between_arm_core_register_and_single_precision_register(r, a) NULL -#define armv7_read_simd_instr_vmov_between_two_arm_core_registers_and_a_doubleword_extension_register(r, a) NULL -#define armv7_read_simd_instr_vmov_between_two_arm_core_registers_and_two_single_precision_registers(r, a) NULL -#define armv7_read_simd_instr_vmov_immediate(r, a) NULL -#define armv7_read_simd_instr_vmovl(r, a) NULL -#define armv7_read_simd_instr_vmov_register(r, a) NULL -#define armv7_read_simd_instr_vmov_scalar_to_arm_core_register(r, a) NULL -#define armv7_read_simd_instr_vmrs(r, a) NULL -#define armv7_read_simd_instr_vmrs_b9(r, a) NULL -#define armv7_read_simd_instr_vmsr(r, a) NULL -#define armv7_read_simd_instr_vmsr_b9(r, a) NULL -#define armv7_read_simd_instr_vmul_floating_point(r, a) NULL -#define armv7_read_simd_instr_vmul_vmull_by_scalar(r, a) NULL -#define armv7_read_simd_instr_vmul_vmull_integer_and_polynomial(r, a) NULL -#define armv7_read_simd_instr_vmvn_immediate(r, a) NULL -#define armv7_read_simd_instr_vmvn_register(r, a) NULL -#define armv7_read_simd_instr_vneg(r, a) NULL -#define armv7_read_simd_instr_vnmla_vnmls_vnmul(r, a) NULL -#define armv7_read_simd_instr_vorn_register(r, a) NULL -#define armv7_read_simd_instr_vorr_immediate(r, a) NULL -#define armv7_read_simd_instr_vorr_register(r, a) NULL -#define armv7_read_simd_instr_vpadal(r, a) NULL -#define armv7_read_simd_instr_vpadd_floating_point(r, a) NULL -#define armv7_read_simd_instr_vpadd_integer(r, a) NULL -#define armv7_read_simd_instr_vpaddl(r, a) NULL -#define armv7_read_simd_instr_vpmax_vpmin_floating_point(r, a) NULL -#define armv7_read_simd_instr_vpmax_vpmin_integer(r, a) NULL -#define armv7_read_simd_instr_vpop(r, a) NULL -#define armv7_read_simd_instr_vpush(r, a) NULL -#define armv7_read_simd_instr_vqabs(r, a) NULL -#define armv7_read_simd_instr_vqadd(r, a) NULL -#define armv7_read_simd_instr_vqdmlal_vqdmlsl(r, a) NULL -#define armv7_read_simd_instr_vqdmulh(r, a) NULL -#define armv7_read_simd_instr_vqdmull(r, a) NULL -#define armv7_read_simd_instr_vqneg(r, a) NULL -#define armv7_read_simd_instr_vqrdmulh(r, a) NULL -#define armv7_read_simd_instr_vqrshl(r, a) NULL -#define armv7_read_simd_instr_vqrshrn_vqrshrun(r, a) NULL -#define armv7_read_simd_instr_vqshl_register(r, a) NULL -#define armv7_read_simd_instr_vqshl_vqshlu_immediate(r, a) NULL -#define armv7_read_simd_instr_vqshrn_vqshrun(r, a) NULL -#define armv7_read_simd_instr_vqsub(r, a) NULL -#define armv7_read_simd_instr_vraddhn(r, a) NULL -#define armv7_read_simd_instr_vrecps(r, a) NULL -#define armv7_read_simd_instr_vrev16_vrev32_vrev64(r, a) NULL -#define armv7_read_simd_instr_vrhadd(r, a) NULL -#define armv7_read_simd_instr_vrshl(r, a) NULL -#define armv7_read_simd_instr_vrshr(r, a) NULL -#define armv7_read_simd_instr_vrshrn(r, a) NULL -#define armv7_read_simd_instr_vrsqrts(r, a) NULL -#define armv7_read_simd_instr_vrsra(r, a) NULL -#define armv7_read_simd_instr_vrsubhn(r, a) NULL -#define armv7_read_simd_instr_vshl_immediate(r, a) NULL -#define armv7_read_simd_instr_vshll(r, a) NULL -#define armv7_read_simd_instr_vshl_register(r, a) NULL -#define armv7_read_simd_instr_vshr(r, a) NULL -#define armv7_read_simd_instr_vshrn(r, a) NULL -#define armv7_read_simd_instr_vsli(r, a) NULL -#define armv7_read_simd_instr_vsqrt(r, a) NULL -#define armv7_read_simd_instr_vsra(r, a) NULL -#define armv7_read_simd_instr_vsri(r, a) NULL -#define armv7_read_simd_instr_vst1_multiple_single_elements(r, a) NULL -#define armv7_read_simd_instr_vst1_single_element_from_one_lane(r, a) NULL -#define armv7_read_simd_instr_vst2_multiple_2_element_structures(r, a) NULL -#define armv7_read_simd_instr_vst2_single_2_element_structure_from_one_lane(r, a) NULL -#define armv7_read_simd_instr_vst3_multiple_3_element_structures(r, a) NULL -#define armv7_read_simd_instr_vst3_single_3_element_structure_from_one_lane(r, a) NULL -#define armv7_read_simd_instr_vst4_multiple_4_element_structures(r, a) NULL -#define armv7_read_simd_instr_vst4_single_4_element_structure_from_one_lane(r, a) NULL -#define armv7_read_simd_instr_vstm(r, a) NULL -#define armv7_read_simd_instr_vstr(r, a) NULL -#define armv7_read_simd_instr_vsub_floating_point(r, a) NULL -#define armv7_read_simd_instr_vsubhn(r, a) NULL -#define armv7_read_simd_instr_vsub_integer(r, a) NULL -#define armv7_read_simd_instr_vsubl_vsubw(r, a) NULL -#define armv7_read_simd_instr_vtbl_vtbx(r, a) NULL -#define armv7_read_simd_instr_vtst(r, a) NULL -#endif diff --git a/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h b/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h deleted file mode 100644 index 1968037..0000000 --- a/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef thumb_16_def_tmp_h -#define thumb_16_def_tmp_h -#define armv7_read_thumb_16_instr_cps_thumb(r) NULL -#define armv7_read_thumb_16_instr_it(r) NULL -#define armv7_read_thumb_16_instr_ldm_ldmia_ldmfd_thumb(r) NULL -#define armv7_read_thumb_16_instr_stm_stmia_stmea(r) NULL -#define armv7_read_thumb_16_instr_sxtb(r) NULL -#define armv7_read_thumb_16_instr_sxth(r) NULL -#define armv7_read_thumb_16_instr_wfe(r) NULL -#endif diff --git a/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h b/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h deleted file mode 100644 index 1ed547c..0000000 --- a/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h +++ /dev/null @@ -1,59 +0,0 @@ -#ifndef thumb_32_def_tmp_h -#define thumb_32_def_tmp_h -#define armv7_read_thumb_32_instr_b_mrs(r) NULL -#define armv7_read_thumb_32_instr_b_msr_register(r) NULL -#define armv7_read_thumb_32_instr_cps_thumb(r) NULL -#define armv7_read_thumb_32_instr_enterx_leavex(r) NULL -#define armv7_read_thumb_32_instr_eret(r) NULL -#define armv7_read_thumb_32_instr_hvc(r) NULL -#define armv7_read_thumb_32_instr_isb(r) NULL -#define armv7_read_thumb_32_instr_ldc_ldc2_immediate(r) NULL -#define armv7_read_thumb_32_instr_ldc_ldc2_literal(r) NULL -#define armv7_read_thumb_32_instr_ldmdb_ldmea(r) NULL -#define armv7_read_thumb_32_instr_ldm_ldmia_ldmfd_thumb(r) NULL -#define armv7_read_thumb_32_instr_mrs(r) NULL -#define armv7_read_thumb_32_instr_mrs_banked_register(r) NULL -#define armv7_read_thumb_32_instr_msr_banked_register(r) NULL -#define armv7_read_thumb_32_instr_msr_register(r) NULL -#define armv7_read_thumb_32_instr_pkh(r) NULL -#define armv7_read_thumb_32_instr_pld_immediate(r) NULL -#define armv7_read_thumb_32_instr_pld_literal(r) NULL -#define armv7_read_thumb_32_instr_pld_pldw_immediate(r) NULL -#define armv7_read_thumb_32_instr_pld_pldw_register(r) NULL -#define armv7_read_thumb_32_instr_pld_register(r) NULL -#define armv7_read_thumb_32_instr_pli_immediate_literal(r) NULL -#define armv7_read_thumb_32_instr_pli_register(r) NULL -#define armv7_read_thumb_32_instr_rfe(r) NULL -#define armv7_read_thumb_32_instr_smc_previously_smi(r) NULL -#define armv7_read_thumb_32_instr_smlabb_smlabt_smlatb_smlatt(r) NULL -#define armv7_read_thumb_32_instr_smlalbb_smlalbt_smlaltb_smlaltt(r) NULL -#define armv7_read_thumb_32_instr_smlawb_smlawt(r) NULL -#define armv7_read_thumb_32_instr_smulbb_smulbt_smultb_smultt(r) NULL -#define armv7_read_thumb_32_instr_smulwb_smulwt(r) NULL -#define armv7_read_thumb_32_instr_smusd(r) NULL -#define armv7_read_thumb_32_instr_sqadd16(r) NULL -#define armv7_read_thumb_32_instr_sqadd8(r) NULL -#define armv7_read_thumb_32_instr_sqasx(r) NULL -#define armv7_read_thumb_32_instr_sqsax(r) NULL -#define armv7_read_thumb_32_instr_sqsub16(r) NULL -#define armv7_read_thumb_32_instr_sqsub8(r) NULL -#define armv7_read_thumb_32_instr_srs_thumb(r) NULL -#define armv7_read_thumb_32_instr_ssat(r) NULL -#define armv7_read_thumb_32_instr_ssat16(r) NULL -#define armv7_read_thumb_32_instr_ssax(r) NULL -#define armv7_read_thumb_32_instr_ssub16(r) NULL -#define armv7_read_thumb_32_instr_ssub8(r) NULL -#define armv7_read_thumb_32_instr_stc_stc2(r) NULL -#define armv7_read_thumb_32_instr_stmdb_stmfd(r) NULL -#define armv7_read_thumb_32_instr_stm_stmia_stmea(r) NULL -#define armv7_read_thumb_32_instr_sub_register_thumb(r) NULL -#define armv7_read_thumb_32_instr_subs_pc_lr_thumb(r) NULL -#define armv7_read_thumb_32_instr_sxtab(r) NULL -#define armv7_read_thumb_32_instr_sxtab16(r) NULL -#define armv7_read_thumb_32_instr_sxtah(r) NULL -#define armv7_read_thumb_32_instr_sxtb(r) NULL -#define armv7_read_thumb_32_instr_sxtb16(r) NULL -#define armv7_read_thumb_32_instr_sxth(r) NULL -#define armv7_read_thumb_32_instr_tbb_tbh(r) NULL -#define armv7_read_thumb_32_instr_wfe(r) NULL -#endif diff --git a/src/arch/arm/v7/opdefs/Makefile.am b/src/arch/arm/v7/opdefs/Makefile.am deleted file mode 100644 index a702d10..0000000 --- a/src/arch/arm/v7/opdefs/Makefile.am +++ /dev/null @@ -1,301 +0,0 @@ - -include ../../../../../tools/d2c/d2c.mk - - -D2C_BIN = ../../../../../tools/d2c/d2c -GEN_BIN = ../../../../../tools/d2c/d2c_genmakefile.sh - -D2C_TYPE = raw - -D2C_OUTDIR = $(PWD)/.. - -D2C_ARCH = armv7 -D2C_HEADER = _ARCH_ARM_V7 - -D2C_ENCODINGS = \ - -e A=arm_ \ - -e t=thumb_16_ \ - -e T=thumb_32_ - -D2C_MACROS = \ - -M SetFlags=g_armv7_instruction_define_setflags \ - -M Condition=g_arm_instruction_set_cond \ - -M "ExpandImmC32=g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, " \ - -M SignExtend=sign_extend_armv7_imm \ - -M SetInsFlag=g_arch_instruction_set_flag \ - -M StoreCondition=g_arm_instruction_set_cond \ - -M ExtendKeyword=g_arm_instruction_extend_keyword - -D2C_OPERANDS = \ - -n BarrierLimitation \ - -n BitDiff \ - -n IncWidth \ - -n DecodeImmShift \ - -n MakeMemoryAccess \ - -n Register \ - -n RegisterShift \ - -n UInt \ - -n ZeroExtend - -FIXED_C_INCLUDES = \ - \n\#include \"..\/helpers.h\" \ - \n\#include \"..\/instruction.h\" \ - \n\#include \"..\/fetch.h\" \ - \n\#include \"..\/link.h\" \ - \n\#include \"..\/post.h\" \ - \n\#include \"..\/..\/instruction.h\" \ - \n\#include \"..\/..\/link.h\" \ - \n\#include \"..\/..\/..\/link.h\" \ - \n\#include \"..\/..\/..\/..\/common\/bconst.h\" \ - \n\n - -FIXED_H_INCLUDES = \ - \n\#include \<stdint.h\> \ - \n \ - \n\#include \"..\/..\/..\/instruction.h\" \ - \n\n - - -# for i in $(seq 1 426); do test -f *A88$i.d && (ls *A88$i.d | sed 's/^/\t/' | sed 's/$/\t\t\t\t\t\t\\/') ; done -ARMV7_DEFS = \ - adc_A881.d \ - adc_A882.d \ - adc_A883.d \ - add_A884.d \ - add_A885.d \ - add_A886.d \ - add_A887.d \ - add_A888.d \ - add_A889.d \ - add_A8810.d \ - add_A8811.d \ - adr_A8812.d \ - and_A8813.d \ - and_A8814.d \ - and_A8815.d \ - asr_A8816.d \ - asr_A8817.d \ - b_A8818.d \ - bfc_A8819.d \ - bfi_A8820.d \ - bic_A8821.d \ - bic_A8822.d \ - bic_A8823.d \ - bkpt_A8824.d \ - bl_A8825.d \ - blx_A8826.d \ - bx_A8827.d \ - bxj_A8828.d \ - cb_A8829.d \ - cdp_A8830.d \ - clrex_A8832.d \ - clz_A8833.d \ - cmn_A8834.d \ - cmn_A8835.d \ - cmn_A8836.d \ - cmp_A8837.d \ - cmp_A8838.d \ - cmp_A8839.d \ - dbg_A8842.d \ - dmb_A8843.d \ - dsb_A8844.d \ - eor_A8846.d \ - eor_A8847.d \ - eor_A8848.d \ - ldr_A8862.d \ - ldr_A8863.d \ - ldr_A8864.d \ - ldr_A8865.d \ - ldr_A8866.d \ - ldrb_A8867.d \ - ldrb_A8868.d \ - ldrb_A8869.d \ - ldrb_A8870.d \ - ldrbt_A8871.d \ - ldrd_A8872.d \ - ldrd_A8873.d \ - ldrd_A8874.d \ - ldrex_A8875.d \ - ldrexb_A8876.d \ - ldrexd_A8877.d \ - ldrexh_A8878.d \ - ldrh_A8879.d \ - ldrh_A8880.d \ - ldrh_A8881.d \ - ldrh_A8882.d \ - ldrht_A8883.d \ - ldrsb_A8884.d \ - ldrsb_A8885.d \ - ldrsb_A8886.d \ - ldrsbt_A8887.d \ - ldrsh_A8888.d \ - ldrsh_A8889.d \ - ldrsh_A8890.d \ - ldrsht_A8891.d \ - ldrt_A8892.d \ - lsl_A8894.d \ - lsl_A8895.d \ - lsr_A8896.d \ - lsr_A8897.d \ - mcr_A8898.d \ - mcrr_A8899.d \ - mla_A88100.d \ - mls_A88101.d \ - mov_A88102.d \ - mov_A88103.d \ - mov_A88104.d \ - movt_A88106.d \ - mrc_A88107.d \ - mrrc_A88108.d \ - mul_A88114.d \ - mvn_A88115.d \ - mvn_A88116.d \ - mvn_A88117.d \ - nop_A88119.d \ - orn_A88120.d \ - orn_A88121.d \ - orr_A88122.d \ - orr_A88123.d \ - orr_A88124.d \ - pop_A88131.d \ - pop_A88132.d \ - push_A88133.d \ - qadd_A88134.d \ - qadd16_A88135.d \ - qadd8_A88136.d \ - qasx_A88137.d \ - qdadd_A88138.d \ - qdsub_A88139.d \ - qsax_A88140.d \ - qsub_A88141.d \ - qsub16_A88142.d \ - qsub8_A88143.d \ - rbit_A88144.d \ - rev_A88145.d \ - rev16_A88146.d \ - revsh_A88147.d \ - ror_A88149.d \ - ror_A88150.d \ - rrx_A88151.d \ - rsb_A88152.d \ - rsb_A88153.d \ - rsb_A88154.d \ - rsc_A88155.d \ - rsc_A88156.d \ - rsc_A88157.d \ - sadd16_A88158.d \ - sadd8_A88159.d \ - sasx_A88160.d \ - sbc_A88161.d \ - sbc_A88162.d \ - sbc_A88163.d \ - sbfx_A88164.d \ - sdiv_A88165.d \ - sel_A88166.d \ - setend_A88167.d \ - sev_A88168.d \ - shadd16_A88169.d \ - shadd8_A88170.d \ - shasx_A88171.d \ - shsax_A88172.d \ - shsub16_A88173.d \ - shsub8_A88174.d \ - smlad_A88177.d \ - smlal_A88178.d \ - smlald_A88180.d \ - smlsd_A88182.d \ - smlsld_A88183.d \ - smmla_A88184.d \ - smmls_A88185.d \ - smmul_A88186.d \ - smuad_A88187.d \ - smull_A88189.d \ - str_A88203.d \ - str_A88204.d \ - str_A88205.d \ - strb_A88206.d \ - strb_A88207.d \ - strb_A88208.d \ - strbt_A88209.d \ - strd_A88210.d \ - strd_A88211.d \ - strex_A88212.d \ - strexb_A88213.d \ - strexd_A88214.d \ - strexh_A88215.d \ - strh_A88216.d \ - strh_A88217.d \ - strh_A88218.d \ - strht_A88219.d \ - strt_A88220.d \ - sub_A88221.d \ - sub_A88222.d \ - sub_A88223.d \ - sub_A88225.d \ - svc_A88228.d \ - swp_A88229.d \ - teq_A88237.d \ - teq_A88238.d \ - teq_A88239.d \ - tst_A88240.d \ - tst_A88241.d \ - tst_A88242.d \ - uadd16_A88243.d \ - uadd8_A88244.d \ - uasx_A88245.d \ - ubfx_A88246.d \ - udf_A88247.d \ - udiv_A88248.d \ - uhadd16_A88249.d \ - uhadd8_A88250.d \ - uhasx_A88251.d \ - uhsax_A88252.d \ - uhsub16_A88253.d \ - uhsub8_A88254.d \ - umaal_A88255.d \ - umlal_A88256.d \ - umull_A88257.d \ - uqadd16_A88258.d \ - uqadd8_A88259.d \ - uqasx_A88260.d \ - uqsax_A88261.d \ - uqsub16_A88262.d \ - uqsub8_A88263.d \ - usad8_A88264.d \ - usada8_A88265.d \ - usat_A88266.d \ - usat16_A88267.d \ - usax_A88268.d \ - usub16_A88269.d \ - usub8_A88270.d \ - uxtab_A88271.d \ - uxtab16_A88272.d \ - uxtah_A88273.d \ - uxtb_A88274.d \ - uxtb16_A88275.d \ - uxth_A88276.d \ - wfi_A88425.d \ - yield_A88426.d - -# subs_B9320.d - -# make dist procède répertoire par répertoire. Or le répertoire opcodes utilise -# le contenu du répertoire opdefs. Il faut donc générer les fichiers nécessaires -# au répertoire opcodes. Et comme on ne peut pas compléter la règle dist, on -# ajoute à la distribution les cibles marquant la génération. (1/2) - -EXTRA_DIST = $(ARMV7_DEFS) $(ARMV7_DEFS:.d=.g) - -# Après coup, on supprime les fichiers inutiles de la distribution/ (2/2) - -dist-hook: - cd $(distdir) && rm $(ARMV7_DEFS:.d=.g) - -all: $(ARMV7_DEFS:.d=.g) fmk.done d2c_final_rules - -fmk.done: $(ARMV7_DEFS) - $(GEN_BIN) ../opcodes/ ../opdefs/.gen ../../../../../tools/d2c/globalgen.mk arm thumb_32 thumb_16 - touch $@ - -clean: - rm -rf $(ARMV7_DEFS:.d=.g) .gen fmk.done diff --git a/src/arch/arm/v7/opdefs/adc_A881.d b/src/arch/arm/v7/opdefs/adc_A881.d deleted file mode 100644 index 6bc66e2..0000000 --- a/src/arch/arm/v7/opdefs/adc_A881.d +++ /dev/null @@ -1,74 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title ADC (immediate) - -@desc Add with Carry (immediate) adds an immediate value and the Carry flag value to a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -@encoding (T1) { - - @word 1 1 1 1 0 i(1) 0 1 0 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - - @syntax <reg_D> <reg_N> <imm32> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ThumbExpandImm(i:imm3:imm8) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 0 1 0 1 S(1) Rn(4) Rd(4) imm12(12) - - @syntax <reg_D> <reg_N> <imm32> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ARMExpandImm(imm12) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/adc_A882.d b/src/arch/arm/v7/opdefs/adc_A882.d deleted file mode 100644 index 27ce6ad..0000000 --- a/src/arch/arm/v7/opdefs/adc_A882.d +++ /dev/null @@ -1,92 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title ADC (register) - -@desc Add with Carry (register) adds a register value, the Carry flag value, and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -@encoding (t1) { - - @half 0 1 0 0 0 0 0 1 0 1 Rm(3) Rdn(3) - - @syntax "adcs" <reg_DN> <reg_M> - - @conv { - - reg_DN = Register(Rdn) - reg_M = Register(Rm) - - } - -} - -@encoding (T2) { - - @word 1 1 1 0 1 0 1 1 0 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <?shift> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 1 0 1 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <?shift> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/adc_A883.d b/src/arch/arm/v7/opdefs/adc_A883.d deleted file mode 100644 index a9c56d8..0000000 --- a/src/arch/arm/v7/opdefs/adc_A883.d +++ /dev/null @@ -1,52 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title ADC (register-shifted register) - -@desc Add with Carry (register-shifted register) adds a register value, the Carry flag value, and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. - -@encoding (A1) { - - @word cond(4) 0 0 0 0 1 0 1 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <reg_shift> - - @conv { - - reg_shift = RegisterShift(type, Rs) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/add_A8810.d b/src/arch/arm/v7/opdefs/add_A8810.d deleted file mode 100644 index 2047276..0000000 --- a/src/arch/arm/v7/opdefs/add_A8810.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title ADD (SP plus register, Thumb) - -@desc This instruction adds an optionally-shifted register value to the SP value, and writes the result to the destination register. - -@encoding (t1) { - - @half 0 1 0 0 0 1 0 0 DM(1) 1 1 0 1 Rdm(3) - - @syntax <reg_DM_1> <SP> <reg_DM_2> - - @conv { - - reg_DM_1 = Register(DM:Rdm) - reg_DM_2 = Register(DM:Rdm) - SP = Register(13) - - } - -} - -@encoding (t2) { - - @half 0 1 0 0 0 1 0 0 1 Rm(4) 1 0 1 - - @syntax <SP> <reg_M> - - @conv { - - reg_M = Register(Rm) - SP = Register(13) - - } - -} - -@encoding (T3) { - - @word 1 1 1 0 1 0 1 1 0 0 0 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - - @syntax <reg_D> <SP> <reg_M> <?shift> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) - SP = Register(13) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") - - } - -} - diff --git a/src/arch/arm/v7/opdefs/add_A8811.d b/src/arch/arm/v7/opdefs/add_A8811.d deleted file mode 100644 index 5b6c0d1..0000000 --- a/src/arch/arm/v7/opdefs/add_A8811.d +++ /dev/null @@ -1,52 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title ADD (SP plus register, ARM) - -@desc This instruction adds an optionally-shifted register value to the SP value, and writes the result to the destination register. - -@encoding (A1) { - - @word cond(4) 0 0 0 0 1 0 0 S(1) 1 1 0 1 Rd(4) imm5(5) type(2) 0 Rm(4) - - @syntax <reg_D> <SP> <reg_M> <?shift> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) - SP = Register(13) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/add_A884.d b/src/arch/arm/v7/opdefs/add_A884.d deleted file mode 100644 index 8b624a7..0000000 --- a/src/arch/arm/v7/opdefs/add_A884.d +++ /dev/null @@ -1,98 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title ADD (immediate, Thumb) - -@desc This instruction adds an immediate value to a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -@encoding (t1) { - - @half 0 0 0 1 1 1 0 imm3(3) Rn(3) Rd(3) - - @syntax "adds" <reg_D> <reg_N> <imm32> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm3, 32) - - } - -} - -@encoding (t2) { - - @half 0 0 1 1 0 Rdn(3) imm8(8) - - @syntax "adds" <reg_DN> <imm32> - - @conv { - - reg_DN = Register(Rdn) - imm32 = ZeroExtend(imm8, 32) - - } - -} - -@encoding (T3) { - - @word 1 1 1 1 0 i(1) 0 1 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - - @syntax <reg_D> <reg_N> <imm32> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ThumbExpandImm(i:imm3:imm8) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") - - } - -} - -@encoding (T4) { - - @word 1 1 1 1 0 i(1) 1 0 0 0 0 0 Rn(4) 0 imm3(3) Rd(4) imm8(8) - - @syntax "addw" <reg_D> <reg_N> <imm32> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ZeroExtend(i:imm3:imm8, 32) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/add_A885.d b/src/arch/arm/v7/opdefs/add_A885.d deleted file mode 100644 index 0f4a919..0000000 --- a/src/arch/arm/v7/opdefs/add_A885.d +++ /dev/null @@ -1,51 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title ADD (immediate, ARM) - -@desc This instruction adds an immediate value to a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -@encoding (A1) { - - @word cond(4) 0 0 1 0 1 0 0 S(1) Rn(4) Rd(4) imm12(12) - - @syntax <reg_D> <reg_N> <imm32> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ARMExpandImm(imm12) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/add_A886.d b/src/arch/arm/v7/opdefs/add_A886.d deleted file mode 100644 index e4f9e00..0000000 --- a/src/arch/arm/v7/opdefs/add_A886.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title ADD (register, Thumb) - -@desc This instruction adds a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -@encoding (t1) { - - @half 0 0 0 1 1 0 0 Rm(3) Rn(3) Rd(3) - - @syntax "adds" <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (t2) { - - @half 0 1 0 0 0 1 0 0 DN(1) Rm(4) Rdn(3) - - @syntax <reg_DN> <reg_M> - - @conv { - - reg_DN = Register(DN:Rdn) - reg_M = Register(Rm) - - } - -} - -@encoding (T3) { - - @word 1 1 1 0 1 0 1 1 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <?shift> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") - - } - -} - diff --git a/src/arch/arm/v7/opdefs/add_A887.d b/src/arch/arm/v7/opdefs/add_A887.d deleted file mode 100644 index 18400a6..0000000 --- a/src/arch/arm/v7/opdefs/add_A887.d +++ /dev/null @@ -1,52 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title ADD (register, ARM) - -@desc This instruction adds a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -@encoding (A1) { - - @word cond(4) 0 0 0 0 1 0 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <?shift> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/add_A888.d b/src/arch/arm/v7/opdefs/add_A888.d deleted file mode 100644 index 5549145..0000000 --- a/src/arch/arm/v7/opdefs/add_A888.d +++ /dev/null @@ -1,52 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title ADD (register-shifted register) - -@desc Add (register-shifted register) adds a register value and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. - -@encoding (A1) { - - @word cond(4) 0 0 0 0 1 0 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <reg_shift> - - @conv { - - reg_shift = RegisterShift(type, Rs) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/add_A889.d b/src/arch/arm/v7/opdefs/add_A889.d deleted file mode 100644 index 5fab17c..0000000 --- a/src/arch/arm/v7/opdefs/add_A889.d +++ /dev/null @@ -1,123 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title ADD (SP plus immediate) - -@desc This instruction adds an immediate value to the SP value, and writes the result to the destination register. - -@encoding (t1) { - - @half 1 0 1 0 1 Rd(3) imm8(8) - - @syntax <reg_D> <SP> <imm32> - - @conv { - - reg_D = Register(Rd) - imm32 = ZeroExtend(imm8:'00', 32) - SP = Register(13) - - } - -} - -@encoding (t2) { - - @half 1 0 1 1 0 0 0 0 0 imm7(7) - - @syntax <SP_0> <SP_1> <imm32> - - @conv { - - imm32 = ZeroExtend(imm7:'00', 32) - SP_0 = Register(13) - SP_1 = Register(13) - - } - -} - -@encoding (T3) { - - @word 1 1 1 1 0 i(1) 0 1 0 0 0 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm8(8) - - @syntax <reg_D> <SP> <imm32> - - @conv { - - reg_D = Register(Rd) - setflags = (S == '1') - imm32 = ThumbExpandImm(i:imm3:imm8) - SP = Register(13) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") - - } - -} - -@encoding (T4) { - - @word 1 1 1 1 0 i(1) 1 0 0 0 0 0 1 1 0 1 0 imm3(3) Rd(4) imm8(8) - - @syntax "addw" <reg_D> <SP> <imm32> - - @conv { - - reg_D = Register(Rd) - imm32 = ZeroExtend(i:imm3:imm8, 32) - SP = Register(13) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 0 1 0 0 S(1) 1 1 0 1 Rd(4) imm12(12) - - @syntax <reg_D> <SP> <imm32> - - @conv { - - reg_D = Register(Rd) - setflags = (S == '1') - imm32 = ARMExpandImm(imm12) - SP = Register(13) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/adr_A8812.d b/src/arch/arm/v7/opdefs/adr_A8812.d deleted file mode 100644 index 16615cb..0000000 --- a/src/arch/arm/v7/opdefs/adr_A8812.d +++ /dev/null @@ -1,114 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title ADR - -@desc This instruction adds an immediate value to the PC value to form a PC-relative address, and writes the result to the destination register. - -@encoding (t1) { - - @half 1 0 1 0 0 Rd(3) imm8(8) - - @syntax <reg_D> <imm32> - - @conv { - - reg_D = Register(Rd) - imm32 = ZeroExtend(imm8:'00', 32) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 0 i(1) 1 0 1 0 1 0 1 1 1 1 0 imm3(3) Rd(4) imm8(8) - - @syntax ".W" <reg_D> <imm32> - - @conv { - - reg_D = Register(Rd) - imm32 = ZeroExtend(i:imm3:imm8, 32) - - } - -} - -@encoding (T3) { - - @word 1 1 1 1 0 i(1) 1 0 0 0 0 0 1 1 1 1 0 imm3(3) Rd(4) imm8(8) - - @syntax ".W" <reg_D> <imm32> - - @conv { - - reg_D = Register(Rd) - imm32 = ZeroExtend(i:imm3:imm8, 32) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 0 1 0 0 0 1 1 1 1 Rd(4) imm12(12) - - @syntax <reg_D> <imm32> - - @conv { - - reg_D = Register(Rd) - imm32 = ARMExpandImm(imm12) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - -@encoding (A2) { - - @word cond(4) 0 0 1 0 0 1 0 0 1 1 1 1 Rd(4) imm12(12) - - @syntax <reg_D> <imm32> - - @conv { - - reg_D = Register(Rd) - imm32 = ARMExpandImm(imm12) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/and_A8813.d b/src/arch/arm/v7/opdefs/and_A8813.d deleted file mode 100644 index 3e1d0ed..0000000 --- a/src/arch/arm/v7/opdefs/and_A8813.d +++ /dev/null @@ -1,74 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title AND (immediate) - -@desc This instruction performs a bitwise AND of a register value and an immediate value, and writes the result to the destination register. - -@encoding (T1) { - - @word 1 1 1 1 0 i(1) 0 0 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - - @syntax <reg_D> <reg_N> <imm32> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 0 0 0 0 S(1) Rn(4) Rd(4) imm12(12) - - @syntax <reg_D> <reg_N> <imm32> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ARMExpandImm_C(imm12, 0) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/and_A8814.d b/src/arch/arm/v7/opdefs/and_A8814.d deleted file mode 100644 index 77f7e55..0000000 --- a/src/arch/arm/v7/opdefs/and_A8814.d +++ /dev/null @@ -1,92 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title AND (register) - -@desc This instruction performs a bitwise AND of a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -@encoding (t1) { - - @half 0 1 0 0 0 0 0 0 0 0 Rm(3) Rdn(3) - - @syntax "ands" <reg_DN> <reg_M> - - @conv { - - reg_DN = Register(Rdn) - reg_M = Register(Rm) - - } - -} - -@encoding (T2) { - - @word 1 1 1 0 1 0 1 0 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <?shift> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 0 0 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <?shift> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/and_A8815.d b/src/arch/arm/v7/opdefs/and_A8815.d deleted file mode 100644 index 5ace3fa..0000000 --- a/src/arch/arm/v7/opdefs/and_A8815.d +++ /dev/null @@ -1,52 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title AND (register-shifted register) - -@desc This instruction performs a bitwise AND of a register value and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. - -@encoding (A1) { - - @word cond(4) 0 0 0 0 0 0 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <reg_shift> - - @conv { - - reg_shift = RegisterShift(type, Rs) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/asr_A8816.d b/src/arch/arm/v7/opdefs/asr_A8816.d deleted file mode 100644 index 006a26c..0000000 --- a/src/arch/arm/v7/opdefs/asr_A8816.d +++ /dev/null @@ -1,91 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title ASR (immediate) - -@desc Arithmetic Shift Right (immediate) shifts a register value right by an immediate number of bits, shifting in copies of its sign bit, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -@encoding (t1) { - - @half 0 0 0 1 0 imm5(5) Rm(3) Rd(3) - - @syntax "asrs" <reg_D> <reg_M> <shift_imm> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - shift_imm = DecodeImmShift('10', imm5) - - } - -} - -@encoding (T2) { - - @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 1 0 Rm(4) - - @syntax <reg_D> <reg_M> <shift_imm> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift_imm = DecodeImmShift('10', imm3:imm2) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 1 0 0 Rm(4) - - @syntax <reg_D> <reg_M> <shift_imm> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift_imm = DecodeImmShift('10', imm5) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/asr_A8817.d b/src/arch/arm/v7/opdefs/asr_A8817.d deleted file mode 100644 index 1e1e9c1..0000000 --- a/src/arch/arm/v7/opdefs/asr_A8817.d +++ /dev/null @@ -1,90 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title ASR (register) - -@desc Arithmetic Shift Right (register) shifts a register value right by a variable number of bits, shifting in copies of its sign bit, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. - -@encoding (t1) { - - @half 0 1 0 0 0 0 0 1 0 0 Rm(3) Rdn(3) - - @syntax "asrs" <reg_DN> <reg_M> - - @conv { - - reg_DN = Register(Rdn) - reg_M = Register(Rm) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 1 0 0 1 0 S(1) Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) Rm(4) 0 1 0 1 Rn(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/b_A8818.d b/src/arch/arm/v7/opdefs/b_A8818.d deleted file mode 100644 index 9e27753..0000000 --- a/src/arch/arm/v7/opdefs/b_A8818.d +++ /dev/null @@ -1,157 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title B - -@desc Branch causes a branch to a target address. - -@encoding (t1) { - - @half 1 1 0 1 cond(4) imm8(8) - - @syntax <imm32> - - @conv { - - imm32 = SignExtend(imm8:'0', imm8 & 0x80, 32) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - - @hooks { - - fetch = help_fetching_with_instruction_b_from_thumb - link = handle_arm_conditional_branch_as_link - post = post_process_branch_instructions - - } - -} - -@encoding (t2) { - - @half 1 1 1 0 0 imm11(11) - - @syntax <imm32> - - @conv { - - imm32 = SignExtend(imm11:'0', imm11 & 0x400, 32) - - } - - @hooks { - - fetch = help_fetching_with_instruction_b_from_thumb - link = handle_arm_conditional_branch_as_link - post = post_process_branch_instructions - - } - -} - -@encoding (T3) { - - @word 1 1 1 1 0 S(1) cond(4) imm6(6) 1 0 J1(1) 0 J2(1) imm11(11) - - @syntax ".W" <imm32> - - @conv { - - imm32 = SignExtend(S:J2:J1:imm6:imm11:'0', S & 0x1, 32) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - - @hooks { - - fetch = help_fetching_with_instruction_b_from_thumb - link = handle_arm_conditional_branch_as_link - post = post_process_branch_instructions - - } - -} - -@encoding (T4) { - - @word 1 1 1 1 0 S(1) imm10(10) 1 0 J1(1) 1 J2(1) imm11(11) - - @syntax ".W" <imm32> - - @conv { - - I1 = NOT(J1 EOR S) - I2 = NOT(J2 EOR S) - imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', S & 0x1, 32) - - } - - @hooks { - - fetch = help_fetching_with_instruction_b_from_thumb - link = handle_arm_conditional_branch_as_link - post = post_process_branch_instructions - - } - -} - -@encoding (A1) { - - @word cond(4) 1 0 1 0 imm24(24) - - @syntax <imm32> - - @conv { - - imm32 = SignExtend(imm24:'00', imm24 & 0x800000, 32) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - - @hooks { - - fetch = help_fetching_with_instruction_b_from_arm - link = handle_arm_conditional_branch_as_link - post = post_process_branch_instructions - - } - -} - diff --git a/src/arch/arm/v7/opdefs/bfc_A8819.d b/src/arch/arm/v7/opdefs/bfc_A8819.d deleted file mode 100644 index 0ee99c8..0000000 --- a/src/arch/arm/v7/opdefs/bfc_A8819.d +++ /dev/null @@ -1,67 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title BFC - -@desc Bit Field Clear clears any number of adjacent bits at any position in a register, without affecting the other bits in the register. - -@encoding (T1) { - - @word 1 1 1 1 0 0 1 1 0 1 1 0 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 0 msb(5) - - @syntax <reg_D> <lsbit> <width> - - @conv { - - reg_D = Register(Rd) - msbit = UInt(msb) - lsbit = UInt(imm3:imm2) - width = BitDiff(msbit, lsbit) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 1 1 1 0 msb(5) Rd(4) lsb(5) 0 0 1 1 1 1 1 - - @syntax <reg_D> <lsbit> <width> - - @conv { - - reg_D = Register(Rd) - msbit = UInt(msb) - lsbit = UInt(lsb) - width = BitDiff(msbit, lsbit) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/bfi_A8820.d b/src/arch/arm/v7/opdefs/bfi_A8820.d deleted file mode 100644 index 1d2bb2f..0000000 --- a/src/arch/arm/v7/opdefs/bfi_A8820.d +++ /dev/null @@ -1,69 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title BFI - -@desc Bit Field Insert copies any number of low order bits from a register into the same number of adjacent bits at any position in the destination register. - -@encoding (T1) { - - @word 1 1 1 1 0 0 1 1 0 1 1 0 Rn(4) 0 imm3(3) Rd(4) imm2(2) 0 msb(5) - - @syntax <reg_D> <reg_N> <lsbit> <width> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - msbit = UInt(msb) - lsbit = UInt(imm3:imm2) - width = BitDiff(msbit, lsbit) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 1 1 1 0 msb(5) Rd(4) lsb(5) 0 0 1 Rn(4) - - @syntax <reg_D> <reg_N> <lsbit> <width> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - msbit = UInt(msb) - lsbit = UInt(lsb) - width = BitDiff(msbit, lsbit) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/bic_A8821.d b/src/arch/arm/v7/opdefs/bic_A8821.d deleted file mode 100644 index 9171b69..0000000 --- a/src/arch/arm/v7/opdefs/bic_A8821.d +++ /dev/null @@ -1,74 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title BIC (immediate) - -@desc Bitwise Bit Clear (immediate) performs a bitwise AND of a register value and the complement of an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -@encoding (T1) { - - @word 1 1 1 1 0 i(1) 0 0 0 0 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - - @syntax <reg_D> <reg_N> <imm32> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 1 1 1 0 S(1) Rn(4) Rd(4) imm12(12) - - @syntax <reg_D> <reg_N> <imm32> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ARMExpandImm_C(imm12, 0) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/bic_A8822.d b/src/arch/arm/v7/opdefs/bic_A8822.d deleted file mode 100644 index 8503460..0000000 --- a/src/arch/arm/v7/opdefs/bic_A8822.d +++ /dev/null @@ -1,92 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title BIC (register) - -@desc Bitwise Bit Clear (register) performs a bitwise AND of a register value and the complement of an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -@encoding (t1) { - - @half 0 1 0 0 0 0 1 1 1 0 Rm(3) Rdn(3) - - @syntax "bics" <reg_DN> <reg_M> - - @conv { - - reg_DN = Register(Rdn) - reg_M = Register(Rm) - - } - -} - -@encoding (T2) { - - @word 1 1 1 0 1 0 1 0 0 0 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <?shift> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 1 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <?shift> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/bic_A8823.d b/src/arch/arm/v7/opdefs/bic_A8823.d deleted file mode 100644 index e6903db..0000000 --- a/src/arch/arm/v7/opdefs/bic_A8823.d +++ /dev/null @@ -1,52 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title BIC (register-shifted register) - -@desc Bitwise Bit Clear (register-shifted register) performs a bitwise AND of a register value and the complement of a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 1 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <reg_shift> - - @conv { - - reg_shift = RegisterShift(type, Rs) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/bkpt_A8824.d b/src/arch/arm/v7/opdefs/bkpt_A8824.d deleted file mode 100644 index f0aa13a..0000000 --- a/src/arch/arm/v7/opdefs/bkpt_A8824.d +++ /dev/null @@ -1,55 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title BKPT - -@desc Breakpoint causes a software breakpoint to occur. Breakpoint is always unconditional, even when inside an IT block. - -@encoding (t1) { - - @half 1 0 1 1 1 1 1 0 imm8(8) - - @syntax <imm32> - - @conv { - - imm32 = ZeroExtend(imm8, 32) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 0 1 0 imm12(12) 0 1 1 1 imm4(4) - - @syntax <imm32> - - @conv { - - imm32 = ZeroExtend(imm12:imm4, 32) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/bl_A8825.d b/src/arch/arm/v7/opdefs/bl_A8825.d deleted file mode 100644 index da0def4..0000000 --- a/src/arch/arm/v7/opdefs/bl_A8825.d +++ /dev/null @@ -1,125 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title BL, BLX (immediate) - -@desc Branch with Link calls a subroutine at a PC-relative address. Branch with Link and Exchange Instruction Sets (immediate) calls a subroutine at a PC-relative address, and changes instruction set from ARM to Thumb, or from Thumb to ARM. - -@encoding (T1) { - - @word 1 1 1 1 0 S(1) imm10(10) 1 1 J1(1) 1 J2(1) imm11(11) - - @syntax <imm32> - - @conv { - - I1 = NOT(J1 EOR S) - I2 = NOT(J2 EOR S) - imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', S & 0x1, 32) - - } - - @hooks { - - fetch = help_fetching_with_instruction_bl_from_thumb - link = handle_call_as_link - post = post_process_branch_and_link_instructions - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 0 S(1) imm10H(10) 1 1 J1(1) 0 J2(1) imm10L(10) H(1) - - @syntax "blx" <imm32> - - @conv { - - I1 = NOT(J1 EOR S) - I2 = NOT(J2 EOR S) - imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', S & 0x1, 32) - - } - - @hooks { - - fetch = help_fetching_with_instruction_blx_from_thumb - link = handle_call_as_link - post = post_process_branch_and_link_instructions - - } - -} - -@encoding (A1) { - - @word cond(4) 1 0 1 1 imm24(24) - - @syntax <imm32> - - @conv { - - imm32 = SignExtend(imm24:'00', imm24 & 0x800000, 32) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - - @hooks { - - fetch = help_fetching_with_instruction_bl_from_arm - link = handle_call_as_link - post = post_process_branch_and_link_instructions - - } - -} - -@encoding (A2) { - - @word 1 1 1 1 1 0 1 H(1) imm24(24) - - @syntax "blx" <imm32> - - @conv { - - imm32 = SignExtend(imm24:H:'0', imm24 & 0x800000, 32) - - } - - @hooks { - - fetch = help_fetching_with_instruction_blx_from_arm - link = handle_call_as_link - post = post_process_branch_and_link_instructions - - } - -} - diff --git a/src/arch/arm/v7/opdefs/blx_A8826.d b/src/arch/arm/v7/opdefs/blx_A8826.d deleted file mode 100644 index 29719fa..0000000 --- a/src/arch/arm/v7/opdefs/blx_A8826.d +++ /dev/null @@ -1,61 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title BLX (register) - -@desc Branch with Link and Exchange (register) calls a subroutine at an address and instruction set specified by a register. - -@encoding (t1) { - - @half 0 1 0 0 0 1 1 1 1 Rm(4) 0 0 0 - - @syntax <reg_M> - - @conv { - - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 Rm(4) - - @syntax <reg_M> - - @conv { - - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/bx_A8827.d b/src/arch/arm/v7/opdefs/bx_A8827.d deleted file mode 100644 index f3681e7..0000000 --- a/src/arch/arm/v7/opdefs/bx_A8827.d +++ /dev/null @@ -1,75 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title BX - -@desc Branch and Exchange causes a branch to an address and instruction set specified by a register. - -@encoding (t1) { - - @half 0 1 0 0 0 1 1 1 0 Rm(4) 0 0 0 - - @syntax <reg_M> - - @conv { - - reg_M = Register(Rm) - - } - - @hooks { - - fetch = help_fetching_with_instruction_bx_from_thumb - link = handle_armv7_conditional_branch_from_register - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 Rm(4) - - @syntax <reg_M> - - @conv { - - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - - @hooks { - - fetch = help_fetching_with_instruction_bx_from_arm - link = handle_armv7_conditional_branch_from_register - - } - -} - diff --git a/src/arch/arm/v7/opdefs/bxj_A8828.d b/src/arch/arm/v7/opdefs/bxj_A8828.d deleted file mode 100644 index efa2de2..0000000 --- a/src/arch/arm/v7/opdefs/bxj_A8828.d +++ /dev/null @@ -1,61 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title BXJ - -@desc Branch and Exchange Jazelle attempts to change to Jazelle state. If the attempt fails, it branches to an address and instruction set specified by a register as though it were a BX instruction. In an implementation that includes the Virtualization Extensions, if HSTR.TJDBX is set to 1, execution of a BXJ instruction in a Non-secure mode other than Hyp mode generates a Hyp Trap exception. For more information see Trapping accesses to Jazelle functionality on page B1-1255. - -@encoding (T1) { - - @word 1 1 1 1 0 0 1 1 1 1 0 0 Rm(4) 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 - - @syntax <reg_M> - - @conv { - - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 Rm(4) - - @syntax <reg_M> - - @conv { - - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/cb_A8829.d b/src/arch/arm/v7/opdefs/cb_A8829.d deleted file mode 100644 index 134e0f4..0000000 --- a/src/arch/arm/v7/opdefs/cb_A8829.d +++ /dev/null @@ -1,58 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title CBNZ, CBZ - -@desc Compare and Branch on Nonzero and Compare and Branch on Zero compare the value in a register with zero, and conditionally branch forward a constant value. They do not affect the condition flags. - -@encoding (t1) { - - @half 1 0 1 1 op(1) 0 i(1) 1 imm5(5) Rn(3) - - @syntax <reg_N> <imm32> - - @conv { - - reg_N = Register(Rn) - imm32 = ZeroExtend(i:imm5:'0', 32) - nonzero = (op == '1') - - } - - @rules { - - if (nonzero); chk_call ExtendKeyword("n") - chk_call ExtendKeyword("z") - - } - - @hooks { - - fetch = help_fetching_with_instruction_cb_n_z - link = handle_comp_and_branch_if_true_as_link - post = post_process_comp_and_branch_instructions - - } - -} - diff --git a/src/arch/arm/v7/opdefs/cdp_A8830.d b/src/arch/arm/v7/opdefs/cdp_A8830.d deleted file mode 100644 index 109b89b..0000000 --- a/src/arch/arm/v7/opdefs/cdp_A8830.d +++ /dev/null @@ -1,109 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title CDP, CDP2 - -@desc Coprocessor Data Processing tells a coprocessor to perform an operation that is independent of ARM core registers and memory. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1, opc2, CRd, CRn, and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid CDP and CDP2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. - -@encoding (T1) { - - @word 1 1 1 0 1 1 1 0 opc1(4) CRn(4) CRd(4) coproc(4) opc2(3) 0 CRm(4) - - @syntax <cp> <undef_opc1> <creg_D> <creg_N> <creg_M> <undef_opc2> - - @conv { - - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_D = CRegister(CRd) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) - - } - -} - -@encoding (A1) { - - @word cond(4) 1 1 1 0 opc1(4) CRn(4) CRd(4) coproc(4) opc2(3) 0 CRm(4) - - @syntax <cp> <undef_opc1> <creg_D> <creg_N> <creg_M> <undef_opc2> - - @conv { - - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_D = CRegister(CRd) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 1 1 0 opc1(4) CRn(4) CRd(4) coproc(4) opc2(3) 0 CRm(4) - - @syntax "cdp2" <cp> <undef_opc1> <creg_D> <creg_N> <creg_M> <undef_opc2> - - @conv { - - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_D = CRegister(CRd) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) - - } - -} - -@encoding (A2) { - - @word 1 1 1 1 1 1 1 0 opc1(4) CRn(4) CRd(4) coproc(4) opc2(3) 0 CRm(4) - - @syntax "cdp2" <cp> <undef_opc1> <creg_D> <creg_N> <creg_M> <undef_opc2> - - @conv { - - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_D = CRegister(CRd) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/clrex_A8832.d b/src/arch/arm/v7/opdefs/clrex_A8832.d deleted file mode 100644 index 4f313f2..0000000 --- a/src/arch/arm/v7/opdefs/clrex_A8832.d +++ /dev/null @@ -1,39 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title CLREX - -@desc Clear-Exclusive clears the local record of the executing processor that an address has had a request for an exclusive access. - -@encoding (T1) { - - @word 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 1 0 1 1 1 1 - -} - -@encoding (A1) { - - @word 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 - -} - diff --git a/src/arch/arm/v7/opdefs/clz_A8833.d b/src/arch/arm/v7/opdefs/clz_A8833.d deleted file mode 100644 index d4fdac6..0000000 --- a/src/arch/arm/v7/opdefs/clz_A8833.d +++ /dev/null @@ -1,63 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title CLZ - -@desc Count Leading Zeros returns the number of binary zero bits before the first binary one bit in a value. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 1 1 Rm(4) 1 1 1 1 Rd(4) 1 0 0 0 Rm(4) - - @syntax <reg_D> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 1 1 0 1 1 1 1 Rd(4) 1 1 1 1 0 0 0 1 Rm(4) - - @syntax <reg_D> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/cmn_A8834.d b/src/arch/arm/v7/opdefs/cmn_A8834.d deleted file mode 100644 index fc0b19f..0000000 --- a/src/arch/arm/v7/opdefs/cmn_A8834.d +++ /dev/null @@ -1,63 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title CMN (immediate) - -@desc Compare Negative (immediate) adds a register value and an immediate value. It updates the condition flags based on the result, and discards the result. - -@encoding (T1) { - - @word 1 1 1 1 0 i(1) 0 1 0 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm8(8) - - @syntax <reg_N> <imm32> - - @conv { - - reg_N = Register(Rn) - imm32 = ThumbExpandImm(i:imm3:imm8) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 1 0 1 1 1 Rn(4) 0 0 0 0 imm12(12) - - @syntax <reg_N> <imm32> - - @conv { - - reg_N = Register(Rn) - imm32 = ARMExpandImm(imm12) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/cmn_A8835.d b/src/arch/arm/v7/opdefs/cmn_A8835.d deleted file mode 100644 index cd228de..0000000 --- a/src/arch/arm/v7/opdefs/cmn_A8835.d +++ /dev/null @@ -1,80 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title CMN (register) - -@desc Compare Negative (register) adds a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result. - -@encoding (t1) { - - @half 0 1 0 0 0 0 1 0 1 1 Rm(3) Rn(3) - - @syntax <reg_N> <reg_M> - - @conv { - - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (T2) { - - @word 1 1 1 0 1 0 1 1 0 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm2(2) type(2) Rm(4) - - @syntax ".W" <reg_N> <reg_M> <?shift> - - @conv { - - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 1 1 1 Rn(4) 0 0 0 0 imm5(5) type(2) 0 Rm(4) - - @syntax <reg_N> <reg_M> <?shift> - - @conv { - - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/cmn_A8836.d b/src/arch/arm/v7/opdefs/cmn_A8836.d deleted file mode 100644 index ad58482..0000000 --- a/src/arch/arm/v7/opdefs/cmn_A8836.d +++ /dev/null @@ -1,49 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title CMN (register-shifted register) - -@desc Compare Negative (register-shifted register) adds a register value and a register-shifted register value. It updates the condition flags based on the result, and discards the result. - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 1 1 1 Rn(4) 0 0 0 0 Rs(4) 0 type(2) 1 Rm(4) - - @syntax <reg_N> <reg_M> <reg_shift> - - @conv { - - reg_shift = RegisterShift(type, Rs) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/cmp_A8837.d b/src/arch/arm/v7/opdefs/cmp_A8837.d deleted file mode 100644 index 76b7a76..0000000 --- a/src/arch/arm/v7/opdefs/cmp_A8837.d +++ /dev/null @@ -1,78 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title CMP (immediate) - -@desc Compare (immediate) subtracts an immediate value from a register value. It updates the condition flags based on the result, and discards the result. - -@encoding (t1) { - - @half 0 0 1 0 1 Rn(3) imm8(8) - - @syntax <reg_N> <imm32> - - @conv { - - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 0 i(1) 0 1 1 0 1 1 Rn(4) 0 imm3(3) 1 1 1 1 imm8(8) - - @syntax ".W" <reg_N> <imm32> - - @conv { - - reg_N = Register(Rn) - imm32 = ThumbExpandImm(i:imm3:imm8) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 1 0 1 0 1 Rn(4) 0 0 0 0 imm12(12) - - @syntax <reg_N> <imm32> - - @conv { - - reg_N = Register(Rn) - imm32 = ARMExpandImm(imm12) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/cmp_A8838.d b/src/arch/arm/v7/opdefs/cmp_A8838.d deleted file mode 100644 index cd02543..0000000 --- a/src/arch/arm/v7/opdefs/cmp_A8838.d +++ /dev/null @@ -1,95 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title CMP (register) - -@desc Compare (register) subtracts an optionally-shifted register value from a register value. It updates the condition flags based on the result, and discards the result. - -@encoding (t1) { - - @half 0 1 0 0 0 0 1 0 1 0 Rm(3) Rn(3) - - @syntax <reg_N> <reg_M> - - @conv { - - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (t2) { - - @half 0 1 0 0 0 1 0 1 N(1) Rm(4) Rn(3) - - @syntax <reg_N> <reg_M> - - @conv { - - reg_N = Register(N:Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (T3) { - - @word 1 1 1 0 1 0 1 1 1 0 1 1 Rn(4) 0 imm3(3) 1 1 1 1 imm2(2) type(2) Rm(4) - - @syntax ".W" <reg_N> <reg_M> <?shift> - - @conv { - - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 1 0 1 Rn(4) 0 0 0 0 imm5(5) type(2) 0 Rm(4) - - @syntax <reg_N> <reg_M> <?shift> - - @conv { - - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/cmp_A8839.d b/src/arch/arm/v7/opdefs/cmp_A8839.d deleted file mode 100644 index 45ed0f9..0000000 --- a/src/arch/arm/v7/opdefs/cmp_A8839.d +++ /dev/null @@ -1,49 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title CMP (register-shifted register) - -@desc Compare (register-shifted register) subtracts a register-shifted register value from a register value. It updates the condition flags based on the result, and discards the result. - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 1 0 1 Rn(4) 0 0 0 0 Rs(4) 0 type(2) 1 Rm(4) - - @syntax <reg_N> <reg_M> <reg_shift> - - @conv { - - reg_shift = RegisterShift(type, Rs) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/dbg_A8842.d b/src/arch/arm/v7/opdefs/dbg_A8842.d deleted file mode 100644 index 62142f5..0000000 --- a/src/arch/arm/v7/opdefs/dbg_A8842.d +++ /dev/null @@ -1,61 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title DBG - -@desc Debug Hint provides a hint to debug and related systems. See their documentation for what use (if any) they make of this instruction. - -@encoding (T1) { - - @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 option(4) - - @syntax <undef_option> - - @conv { - - undef_option = RawValue(option) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 option(4) - - @syntax <undef_option> - - @conv { - - undef_option = RawValue(option) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/dmb_A8843.d b/src/arch/arm/v7/opdefs/dmb_A8843.d deleted file mode 100644 index 34f053a..0000000 --- a/src/arch/arm/v7/opdefs/dmb_A8843.d +++ /dev/null @@ -1,55 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title DMB - -@desc Data Memory Barrier is a memory barrier that ensures the ordering of observations of memory accesses, see Data Memory Barrier (DMB) on page A3-151. - -@encoding (T1) { - - @word 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 0 1 option(4) - - @syntax <limitation> - - @conv { - - limitation = BarrierLimitation(option) - - } - -} - -@encoding (A1) { - - @word 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 1 option(4) - - @syntax <limitation> - - @conv { - - limitation = BarrierLimitation(option) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/dsb_A8844.d b/src/arch/arm/v7/opdefs/dsb_A8844.d deleted file mode 100644 index 512220c..0000000 --- a/src/arch/arm/v7/opdefs/dsb_A8844.d +++ /dev/null @@ -1,55 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title DSB - -@desc Data Synchronization Barrier is a memory barrier that ensures the completion of memory accesses, see Data Synchronization Barrier (DSB) on page A3-152. - -@encoding (T1) { - - @word 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 0 0 option(4) - - @syntax <limitation> - - @conv { - - limitation = BarrierLimitation(option) - - } - -} - -@encoding (A1) { - - @word 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 option(4) - - @syntax <limitation> - - @conv { - - limitation = BarrierLimitation(option) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/eor_A8846.d b/src/arch/arm/v7/opdefs/eor_A8846.d deleted file mode 100644 index 38dc858..0000000 --- a/src/arch/arm/v7/opdefs/eor_A8846.d +++ /dev/null @@ -1,74 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title EOR (immediate) - -@desc Bitwise Exclusive OR (immediate) performs a bitwise Exclusive OR of a register value and an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -@encoding (T1) { - - @word 1 1 1 1 0 i(1) 0 0 1 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - - @syntax <reg_D> <reg_N> <imm32> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 0 0 0 1 S(1) Rn(4) Rd(4) imm12(12) - - @syntax <reg_D> <reg_N> <imm32> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ARMExpandImm_C(imm12, 0) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/eor_A8847.d b/src/arch/arm/v7/opdefs/eor_A8847.d deleted file mode 100644 index 66643a1..0000000 --- a/src/arch/arm/v7/opdefs/eor_A8847.d +++ /dev/null @@ -1,92 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title EOR (register) - -@desc Bitwise Exclusive OR (register) performs a bitwise Exclusive OR of a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -@encoding (t1) { - - @half 0 1 0 0 0 0 0 0 0 1 Rm(3) Rdn(3) - - @syntax "eors" <reg_DN> <reg_M> - - @conv { - - reg_DN = Register(Rdn) - reg_M = Register(Rm) - - } - -} - -@encoding (T2) { - - @word 1 1 1 0 1 0 1 0 1 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <?shift> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 0 0 1 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <?shift> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/eor_A8848.d b/src/arch/arm/v7/opdefs/eor_A8848.d deleted file mode 100644 index f38fa74..0000000 --- a/src/arch/arm/v7/opdefs/eor_A8848.d +++ /dev/null @@ -1,52 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title EOR (register-shifted register) - -@desc Bitwise Exclusive OR (register-shifted register) performs a bitwise Exclusive OR of a register value and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. - -@encoding (A1) { - - @word cond(4) 0 0 0 0 0 0 1 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <reg_shift> - - @conv { - - reg_shift = RegisterShift(type, Rs) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ldr_A8862.d b/src/arch/arm/v7/opdefs/ldr_A8862.d deleted file mode 100644 index 03df506..0000000 --- a/src/arch/arm/v7/opdefs/ldr_A8862.d +++ /dev/null @@ -1,98 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LDR (immediate, Thumb) - -@desc Load Register (immediate) calculates an address from a base register value and an immediate offset, loads a word from memory, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (t1) { - - @half 0 1 1 0 1 imm5(5) Rn(3) Rt(3) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm5:'00', 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) - - } - -} - -@encoding (t2) { - - @half 1 0 0 1 1 Rt(3) imm8(8) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - imm32 = ZeroExtend(imm8:'00', 32) - SP = Register(13) - mem_access = MakeMemoryAccess(SP, imm32, NULL, true, true, false) - - } - -} - -@encoding (T3) { - - @word 1 1 1 1 1 0 0 0 1 1 0 1 Rn(4) Rt(4) imm12(12) - - @syntax ".W" <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) - - } - -} - -@encoding (T4) { - - @word 1 1 1 1 1 0 0 0 0 1 0 1 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - index = (P == '1') - add = (U == '1') - wback = (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ldr_A8863.d b/src/arch/arm/v7/opdefs/ldr_A8863.d deleted file mode 100644 index 0d0ce1f..0000000 --- a/src/arch/arm/v7/opdefs/ldr_A8863.d +++ /dev/null @@ -1,53 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LDR (immediate, ARM) - -@desc Load Register (immediate) calculates an address from a base register value and an immediate offset, loads a word from memory, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (A1) { - - @word cond(4) 0 1 0 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) imm12(12) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ldr_A8864.d b/src/arch/arm/v7/opdefs/ldr_A8864.d deleted file mode 100644 index 74afa2d..0000000 --- a/src/arch/arm/v7/opdefs/ldr_A8864.d +++ /dev/null @@ -1,99 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LDR (literal) - -@desc Load Register (literal) calculates an address from the PC value and an immediate offset, loads a word from memory, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (t1) { - - @half 0 1 0 0 1 Rt(3) imm8(8) - - @syntax <reg_T> <imm32> - - @conv { - - reg_T = Register(Rt) - imm32 = ZeroExtend(imm8:'00', 32) - - } - - @hooks { - - fetch = help_fetching_with_instruction_ldr_literal_from_thumb - post = post_process_ldr_instructions - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 0 0 U(1) 1 0 1 1 1 1 1 Rt(4) imm12(12) - - @syntax ".W" <reg_T> <imm32> - - @conv { - - reg_T = Register(Rt) - imm32 = ZeroExtend(imm12, 32) - - } - - @hooks { - - fetch = help_fetching_with_instruction_ldr_literal_from_thumb - post = post_process_ldr_instructions - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 0 1 U(1) 0 0 1 1 1 1 1 Rt(4) imm12(12) - - @syntax <reg_T> <imm32> - - @conv { - - reg_T = Register(Rt) - imm32 = ZeroExtend(imm12, 32) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - - @hooks { - - fetch = help_fetching_with_instruction_ldr_literal_from_arm - post = post_process_ldr_instructions - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ldr_A8865.d b/src/arch/arm/v7/opdefs/ldr_A8865.d deleted file mode 100644 index ebb4e09..0000000 --- a/src/arch/arm/v7/opdefs/ldr_A8865.d +++ /dev/null @@ -1,62 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LDR (register, Thumb) - -@desc Load Register (register) calculates an address from a base register value and an offset register value, loads a word from memory, and writes it to a register. The offset register value can optionally be shifted. For information about memory accesses, see Memory accesses on page A8-294. The Thumb form of LDR (register) does not support register writeback. - -@encoding (t1) { - - @half 0 1 0 1 1 0 0 Rm(3) Rn(3) Rt(3) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, false, false) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 0 0 0 1 0 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - - @syntax ".W" <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(0, imm2) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, false, false) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ldr_A8866.d b/src/arch/arm/v7/opdefs/ldr_A8866.d deleted file mode 100644 index b161043..0000000 --- a/src/arch/arm/v7/opdefs/ldr_A8866.d +++ /dev/null @@ -1,54 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LDR (register, ARM) - -@desc Load Register (register) calculates an address from a base register value and an offset register value, loads a word from memory, and writes it to a register. The offset register value can optionally be shifted. For information about memory accesses, see Memory accesses on page A8-294. - -@encoding (A1) { - - @word cond(4) 0 1 1 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - shift = DecodeImmShift(type, imm5) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, index, add, wback) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ldrb_A8867.d b/src/arch/arm/v7/opdefs/ldrb_A8867.d deleted file mode 100644 index 2dea64e..0000000 --- a/src/arch/arm/v7/opdefs/ldrb_A8867.d +++ /dev/null @@ -1,81 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LDRB (immediate, Thumb) - -@desc Load Register Byte (immediate) calculates an address from a base register value and an immediate offset, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (t1) { - - @half 0 1 1 1 1 imm5(5) Rn(3) Rt(3) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm5, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 0 0 1 0 0 1 Rn(4) Rt(4) imm12(12) - - @syntax ".W" <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) - - } - -} - -@encoding (T3) { - - @word 1 1 1 1 1 0 0 0 0 0 0 1 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - index = (P == '1') - add = (U == '1') - wback = (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ldrb_A8868.d b/src/arch/arm/v7/opdefs/ldrb_A8868.d deleted file mode 100644 index 519c309..0000000 --- a/src/arch/arm/v7/opdefs/ldrb_A8868.d +++ /dev/null @@ -1,53 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LDRB (immediate, ARM) - -@desc Load Register Byte (immediate) calculates an address from a base register value and an immediate offset, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (A1) { - - @word cond(4) 0 1 0 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) imm12(12) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ldrb_A8869.d b/src/arch/arm/v7/opdefs/ldrb_A8869.d deleted file mode 100644 index fb80049..0000000 --- a/src/arch/arm/v7/opdefs/ldrb_A8869.d +++ /dev/null @@ -1,63 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LDRB (literal) - -@desc Load Register Byte (literal) calculates an address from the PC value and an immediate offset, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (T1) { - - @word 1 1 1 1 1 0 0 0 U(1) 0 0 1 1 1 1 1 Rt(4) imm12(12) - - @syntax <reg_T> <imm32> - - @conv { - - reg_T = Register(Rt) - imm32 = ZeroExtend(imm12, 32) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 0 1 U(1) 1 0 1 1 1 1 1 Rt(4) imm12(12) - - @syntax <reg_T> <imm32> - - @conv { - - reg_T = Register(Rt) - imm32 = ZeroExtend(imm12, 32) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ldrb_A8870.d b/src/arch/arm/v7/opdefs/ldrb_A8870.d deleted file mode 100644 index 35f95ab..0000000 --- a/src/arch/arm/v7/opdefs/ldrb_A8870.d +++ /dev/null @@ -1,89 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LDRB (register) - -@desc Load Register Byte (register) calculates an address from a base register value and an offset register value, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. The offset register value can optionally be shifted. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (t1) { - - @half 0 1 0 1 1 1 0 Rm(3) Rn(3) Rt(3) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, true, false) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 0 0 0 0 0 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - - @syntax ".W" <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(0, imm2) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, true, false) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - shift = DecodeImmShift(type, imm5) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, index, add, wback) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ldrbt_A8871.d b/src/arch/arm/v7/opdefs/ldrbt_A8871.d deleted file mode 100644 index 0bf9c3c..0000000 --- a/src/arch/arm/v7/opdefs/ldrbt_A8871.d +++ /dev/null @@ -1,93 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LDRBT - -@desc Load Register Byte Unprivileged loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRBT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. - -@encoding (T1) { - - @word 1 1 1 1 1 0 0 0 0 0 0 1 Rn(4) Rt(4) 1 1 1 0 imm8(8) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 0 0 U(1) 1 1 1 Rn(4) Rt(4) imm12(12) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - add = (U == '1') - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - -@encoding (A2) { - - @word cond(4) 0 1 1 0 U(1) 1 1 1 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - add = (U == '1') - shift = DecodeImmShift(type, imm5) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, false, add, false) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ldrd_A8872.d b/src/arch/arm/v7/opdefs/ldrd_A8872.d deleted file mode 100644 index c73fdca..0000000 --- a/src/arch/arm/v7/opdefs/ldrd_A8872.d +++ /dev/null @@ -1,75 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LDRD (immediate) - -@desc Load Register Dual (immediate) calculates an address from a base register value and an immediate offset, loads two words from memory, and writes them to two registers. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (T1) { - - @word 1 1 1 0 1 0 0 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) Rt2(4) imm8(8) - - @syntax <reg_T> <reg_T2> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - index = (P == '1') - add = (U == '1') - wback = (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) imm4H(4) 1 1 0 1 imm4L(4) - - @syntax <reg_T> <reg_T2> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_T2 = NextRegister(reg_T) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ldrd_A8873.d b/src/arch/arm/v7/opdefs/ldrd_A8873.d deleted file mode 100644 index 828e4a3..0000000 --- a/src/arch/arm/v7/opdefs/ldrd_A8873.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LDRD (literal) - -@desc Load Register Dual (literal) calculates an address from the PC value and an immediate offset, loads two words from memory, and writes them to two registers. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (T1) { - - @word 1 1 1 0 1 0 0 P(1) U(1) 1 W(1) 1 1 1 1 1 Rt(4) Rt2(4) imm8(8) - - @syntax <reg_T> <reg_T2> <imm32> - - @conv { - - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - imm32 = ZeroExtend(imm8:'00', 32) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 U(1) 1 0 0 1 1 1 1 Rt(4) imm4H(4) 1 1 0 1 imm4L(4) - - @syntax <reg_T> <reg_T2> <imm32> - - @conv { - - reg_T = Register(Rt) - reg_T2 = NextRegister(reg_T) - imm32 = ZeroExtend(imm4H:imm4L, 32) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ldrd_A8874.d b/src/arch/arm/v7/opdefs/ldrd_A8874.d deleted file mode 100644 index ed055a6..0000000 --- a/src/arch/arm/v7/opdefs/ldrd_A8874.d +++ /dev/null @@ -1,54 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LDRD (register) - -@desc Load Register Dual (register) calculates an address from a base register value and a register offset, loads two words from memory, and writes them to two registers. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (A1) { - - @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) 0 0 0 0 1 1 0 1 Rm(4) - - @syntax <reg_T> <reg_T2> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_T2 = NextRegister(reg_T) - reg_N = Register(Rn) - reg_M = Register(Rm) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, index, add, wback) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ldrex_A8875.d b/src/arch/arm/v7/opdefs/ldrex_A8875.d deleted file mode 100644 index b915061..0000000 --- a/src/arch/arm/v7/opdefs/ldrex_A8875.d +++ /dev/null @@ -1,66 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LDREX - -@desc Load Register Exclusive calculates an address from a base register value and an immediate offset, loads a word from memory, writes it to a register and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (T1) { - - @word 1 1 1 0 1 0 0 0 0 1 0 1 Rn(4) Rt(4) 1 1 1 1 imm8(8) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, false, false) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 0 0 1 Rn(4) Rt(4) 1 1 1 1 1 0 0 1 1 1 1 1 - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ldrexb_A8876.d b/src/arch/arm/v7/opdefs/ldrexb_A8876.d deleted file mode 100644 index e398ef2..0000000 --- a/src/arch/arm/v7/opdefs/ldrexb_A8876.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LDREXB - -@desc Load Register Exclusive Byte derives an address from a base register value, loads a byte from memory, zero-extends it to form a 32-bit word, writes it to a register and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (T1) { - - @word 1 1 1 0 1 0 0 0 1 1 0 1 Rn(4) Rt(4) 1 1 1 1 0 1 0 0 1 1 1 1 - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 1 0 1 Rn(4) Rt(4) 1 1 1 1 1 0 0 1 1 1 1 1 - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ldrexd_A8877.d b/src/arch/arm/v7/opdefs/ldrexd_A8877.d deleted file mode 100644 index 0188cb7..0000000 --- a/src/arch/arm/v7/opdefs/ldrexd_A8877.d +++ /dev/null @@ -1,67 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LDREXD - -@desc Load Register Exclusive Doubleword derives an address from a base register value, loads a 64-bit doubleword from memory, writes it to two registers and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (T1) { - - @word 1 1 1 0 1 0 0 0 1 1 0 1 Rn(4) Rt(4) Rt2(4) 0 1 1 1 1 1 1 1 - - @syntax <reg_T> <reg_T2> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 0 1 1 Rn(4) Rt(4) 1 1 1 1 1 0 0 1 1 1 1 1 - - @syntax <reg_T> <reg_T2> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_T2 = NextRegister(reg_T) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ldrexh_A8878.d b/src/arch/arm/v7/opdefs/ldrexh_A8878.d deleted file mode 100644 index 8e9366f..0000000 --- a/src/arch/arm/v7/opdefs/ldrexh_A8878.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LDREXH - -@desc Load Register Exclusive Halfword derives an address from a base register value, loads a halfword from memory, zero-extends it to form a 32-bit word, writes it to a register and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (T1) { - - @word 1 1 1 0 1 0 0 0 1 1 0 1 Rn(4) Rt(4) 1 1 1 1 0 1 0 1 1 1 1 1 - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 1 1 1 Rn(4) Rt(4) 1 1 1 1 1 0 0 1 1 1 1 1 - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ldrh_A8879.d b/src/arch/arm/v7/opdefs/ldrh_A8879.d deleted file mode 100644 index 3b57bf8..0000000 --- a/src/arch/arm/v7/opdefs/ldrh_A8879.d +++ /dev/null @@ -1,81 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LDRH (immediate, Thumb) - -@desc Load Register Halfword (immediate) calculates an address from a base register value and an immediate offset, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (t1) { - - @half 1 0 0 0 1 imm5(5) Rn(3) Rt(3) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm5:'0', 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 0 0 1 0 1 1 Rn(4) Rt(4) imm12(12) - - @syntax ".W" <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) - - } - -} - -@encoding (T3) { - - @word 1 1 1 1 1 0 0 0 0 0 1 1 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - index = (P == '1') - add = (U == '1') - wback = (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ldrh_A8880.d b/src/arch/arm/v7/opdefs/ldrh_A8880.d deleted file mode 100644 index f5f7ab0..0000000 --- a/src/arch/arm/v7/opdefs/ldrh_A8880.d +++ /dev/null @@ -1,53 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LDRH (immediate, ARM) - -@desc Load Register Halfword (immediate) calculates an address from a base register value and an immediate offset, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (A1) { - - @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) imm4H(4) 1 0 1 1 imm4L(4) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ldrh_A8881.d b/src/arch/arm/v7/opdefs/ldrh_A8881.d deleted file mode 100644 index 59005e4..0000000 --- a/src/arch/arm/v7/opdefs/ldrh_A8881.d +++ /dev/null @@ -1,63 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LDRH (literal) - -@desc Load Register Halfword (literal) calculates an address from the PC value and an immediate offset, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (T1) { - - @word 1 1 1 1 1 0 0 0 U(1) 0 1 1 1 1 1 1 Rt(4) imm12(12) - - @syntax <reg_T> <imm32> - - @conv { - - reg_T = Register(Rt) - imm32 = ZeroExtend(imm12, 32) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 1 1 1 1 1 Rt(4) imm4H(4) 1 0 1 1 imm4L(4) - - @syntax <reg_T> <imm32> - - @conv { - - reg_T = Register(Rt) - imm32 = ZeroExtend(imm4H:imm4L, 32) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ldrh_A8882.d b/src/arch/arm/v7/opdefs/ldrh_A8882.d deleted file mode 100644 index 823bf24..0000000 --- a/src/arch/arm/v7/opdefs/ldrh_A8882.d +++ /dev/null @@ -1,88 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LDRH (register) - -@desc Load Register Halfword (register) calculates an address from a base register value and an offset register value, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (t1) { - - @half 0 1 0 1 1 0 1 Rm(3) Rn(3) Rt(3) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, true, false) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 0 0 0 0 1 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - - @syntax ".W" <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(0, imm2) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, true, false) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) 0 0 0 0 1 0 1 1 Rm(4) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, index, add, wback) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ldrht_A8883.d b/src/arch/arm/v7/opdefs/ldrht_A8883.d deleted file mode 100644 index 8f8f015..0000000 --- a/src/arch/arm/v7/opdefs/ldrht_A8883.d +++ /dev/null @@ -1,92 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LDRHT - -@desc Load Register Halfword Unprivileged loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRHT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value. - -@encoding (T1) { - - @word 1 1 1 1 1 0 0 0 0 0 1 1 Rn(4) Rt(4) 1 1 1 0 imm8(8) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 U(1) 1 1 1 Rn(4) Rt(4) imm4H(4) 1 0 1 1 imm4L(4) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - add = (U == '1') - imm32 = ZeroExtend(imm4H:imm4L, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - -@encoding (A2) { - - @word cond(4) 0 0 0 0 U(1) 0 1 1 Rn(4) Rt(4) 0 0 0 0 1 0 1 1 Rm(4) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - add = (U == '1') - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, false, add, false) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ldrsb_A8884.d b/src/arch/arm/v7/opdefs/ldrsb_A8884.d deleted file mode 100644 index fc41134..0000000 --- a/src/arch/arm/v7/opdefs/ldrsb_A8884.d +++ /dev/null @@ -1,90 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LDRSB (immediate) - -@desc Load Register Signed Byte (immediate) calculates an address from a base register value and an immediate offset, loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (T1) { - - @word 1 1 1 1 1 0 0 1 1 0 0 1 Rn(4) Rt(4) imm12(12) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 0 1 0 0 0 1 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - index = (P == '1') - add = (U == '1') - wback = (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) imm4H(4) 1 1 0 1 imm4L(4) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ldrsb_A8885.d b/src/arch/arm/v7/opdefs/ldrsb_A8885.d deleted file mode 100644 index 6cb1d34..0000000 --- a/src/arch/arm/v7/opdefs/ldrsb_A8885.d +++ /dev/null @@ -1,63 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LDRSB (literal) - -@desc Load Register Signed Byte (literal) calculates an address from the PC value and an immediate offset, loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (T1) { - - @word 1 1 1 1 1 0 0 1 U(1) 0 0 1 1 1 1 1 Rt(4) imm12(12) - - @syntax <reg_T> <imm32> - - @conv { - - reg_T = Register(Rt) - imm32 = ZeroExtend(imm12, 32) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 U(1) 1 0 1 1 1 1 1 Rt(4) imm4H(4) 1 1 0 1 imm4L(4) - - @syntax <reg_T> <imm32> - - @conv { - - reg_T = Register(Rt) - imm32 = ZeroExtend(imm4H:imm4L, 32) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ldrsb_A8886.d b/src/arch/arm/v7/opdefs/ldrsb_A8886.d deleted file mode 100644 index 4a66278..0000000 --- a/src/arch/arm/v7/opdefs/ldrsb_A8886.d +++ /dev/null @@ -1,88 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LDRSB (register) - -@desc Load Register Signed Byte (register) calculates an address from a base register value and an offset register value, loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (t1) { - - @half 0 1 0 1 0 1 1 Rm(3) Rn(3) Rt(3) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, true, false) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 0 1 0 0 0 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - - @syntax ".W" <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(0, imm2) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, true, false) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) 0 0 0 0 1 1 0 1 Rm(4) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, index, add, wback) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ldrsbt_A8887.d b/src/arch/arm/v7/opdefs/ldrsbt_A8887.d deleted file mode 100644 index b545f32..0000000 --- a/src/arch/arm/v7/opdefs/ldrsbt_A8887.d +++ /dev/null @@ -1,92 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LDRSBT - -@desc Load Register Signed Byte Unprivileged loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRSBT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value. - -@encoding (T1) { - - @word 1 1 1 1 1 0 0 1 0 0 0 1 Rn(4) Rt(4) 1 1 1 0 imm8(8) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 U(1) 1 1 1 Rn(4) Rt(4) imm4H(4) 1 1 0 1 imm4L(4) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - add = (U == '1') - imm32 = ZeroExtend(imm4H:imm4L, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - -@encoding (A2) { - - @word cond(4) 0 0 0 0 U(1) 0 1 1 Rn(4) Rt(4) 0 0 0 0 1 1 0 1 Rm(4) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - add = (U == '1') - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, false, add, false) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ldrsh_A8888.d b/src/arch/arm/v7/opdefs/ldrsh_A8888.d deleted file mode 100644 index f01024c..0000000 --- a/src/arch/arm/v7/opdefs/ldrsh_A8888.d +++ /dev/null @@ -1,90 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LDRSH (immediate) - -@desc Load Register Signed Halfword (immediate) calculates an address from a base register value and an immediate offset, loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (T1) { - - @word 1 1 1 1 1 0 0 1 1 0 1 1 Rn(4) Rt(4) imm12(12) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 0 1 0 0 1 1 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - index = (P == '1') - add = (U == '1') - wback = (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) imm4H(4) 1 1 1 1 imm4L(4) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ldrsh_A8889.d b/src/arch/arm/v7/opdefs/ldrsh_A8889.d deleted file mode 100644 index 074cd5c..0000000 --- a/src/arch/arm/v7/opdefs/ldrsh_A8889.d +++ /dev/null @@ -1,63 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LDRSH (literal) - -@desc Load Register Signed Halfword (literal) calculates an address from the PC value and an immediate offset, loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (T1) { - - @word 1 1 1 1 1 0 0 1 U(1) 0 1 1 1 1 1 1 Rt(4) imm12(12) - - @syntax <reg_T> <imm32> - - @conv { - - reg_T = Register(Rt) - imm32 = ZeroExtend(imm12, 32) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 U(1) 1 0 1 1 1 1 1 Rt(4) imm4H(4) 1 1 1 1 imm4L(4) - - @syntax <reg_T> <imm32> - - @conv { - - reg_T = Register(Rt) - imm32 = ZeroExtend(imm4H:imm4L, 32) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ldrsh_A8890.d b/src/arch/arm/v7/opdefs/ldrsh_A8890.d deleted file mode 100644 index eac6c09..0000000 --- a/src/arch/arm/v7/opdefs/ldrsh_A8890.d +++ /dev/null @@ -1,88 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LDRSH (register) - -@desc Load Register Signed Halfword (register) calculates an address from a base register value and an offset register value, loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (t1) { - - @half 0 1 0 1 1 1 1 Rm(3) Rn(3) Rt(3) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, true, false) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 0 1 0 0 1 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - - @syntax ".W" <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(0, imm2) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, true, false) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) 0 0 0 0 1 1 1 1 Rm(4) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, index, add, wback) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ldrsht_A8891.d b/src/arch/arm/v7/opdefs/ldrsht_A8891.d deleted file mode 100644 index 355178b..0000000 --- a/src/arch/arm/v7/opdefs/ldrsht_A8891.d +++ /dev/null @@ -1,92 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LDRSHT - -@desc Load Register Signed Halfword Unprivileged loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRSHT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value. - -@encoding (T1) { - - @word 1 1 1 1 1 0 0 1 0 0 1 1 Rn(4) Rt(4) 1 1 1 0 imm8(8) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 U(1) 1 1 1 Rn(4) Rt(4) imm4H(4) 1 1 1 1 imm4L(4) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - add = (U == '1') - imm32 = ZeroExtend(imm4H:imm4L, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - -@encoding (A2) { - - @word cond(4) 0 0 0 0 U(1) 0 1 1 Rn(4) Rt(4) 0 0 0 0 1 1 1 1 Rm(4) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - add = (U == '1') - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, false, add, false) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ldrt_A8892.d b/src/arch/arm/v7/opdefs/ldrt_A8892.d deleted file mode 100644 index e13f0e7..0000000 --- a/src/arch/arm/v7/opdefs/ldrt_A8892.d +++ /dev/null @@ -1,93 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LDRT - -@desc Load Register Unprivileged loads a word from memory, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. - -@encoding (T1) { - - @word 1 1 1 1 1 0 0 0 0 1 0 1 Rn(4) Rt(4) 1 1 1 0 imm8(8) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 0 0 U(1) 0 1 1 Rn(4) Rt(4) imm12(12) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - add = (U == '1') - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - -@encoding (A2) { - - @word cond(4) 0 1 1 0 U(1) 0 1 1 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - add = (U == '1') - shift = DecodeImmShift(type, imm5) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, false, add, false) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/lsl_A8894.d b/src/arch/arm/v7/opdefs/lsl_A8894.d deleted file mode 100644 index 89924c6..0000000 --- a/src/arch/arm/v7/opdefs/lsl_A8894.d +++ /dev/null @@ -1,91 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LSL (immediate) - -@desc Logical Shift Left (immediate) shifts a register value left by an immediate number of bits, shifting in zeros, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -@encoding (t1) { - - @half 0 0 0 0 0 imm5(5) Rm(3) Rd(3) - - @syntax "lsls" <reg_D> <reg_M> <shift_imm> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - shift_imm = DecodeImmShift('00', imm5) - - } - -} - -@encoding (T2) { - - @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 0 0 Rm(4) - - @syntax <reg_D> <reg_M> <shift_imm> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift_imm = DecodeImmShift('00', imm3:imm2) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 0 0 0 Rm(4) - - @syntax <reg_D> <reg_M> <shift_imm> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift_imm = DecodeImmShift('00', imm5) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/lsl_A8895.d b/src/arch/arm/v7/opdefs/lsl_A8895.d deleted file mode 100644 index 4ac5ab6..0000000 --- a/src/arch/arm/v7/opdefs/lsl_A8895.d +++ /dev/null @@ -1,90 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LSL (register) - -@desc Logical Shift Left (register) shifts a register value left by a variable number of bits, shifting in zeros, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. - -@encoding (t1) { - - @half 0 1 0 0 0 0 0 0 1 0 Rm(3) Rdn(3) - - @syntax "lsls" <reg_DN> <reg_M> - - @conv { - - reg_DN = Register(Rdn) - reg_M = Register(Rm) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 1 0 0 0 0 S(1) Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) Rm(4) 0 0 0 1 Rn(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/lsr_A8896.d b/src/arch/arm/v7/opdefs/lsr_A8896.d deleted file mode 100644 index acb9e25..0000000 --- a/src/arch/arm/v7/opdefs/lsr_A8896.d +++ /dev/null @@ -1,91 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LSR (immediate) - -@desc Logical Shift Right (immediate) shifts a register value right by an immediate number of bits, shifting in zeros, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -@encoding (t1) { - - @half 0 0 0 0 1 imm5(5) Rm(3) Rd(3) - - @syntax "lsrs" <reg_D> <reg_M> <shift_imm> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - shift_imm = DecodeImmShift('01', imm5) - - } - -} - -@encoding (T2) { - - @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 0 1 Rm(4) - - @syntax <reg_D> <reg_M> <shift_imm> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift_imm = DecodeImmShift('01', imm3:imm2) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 0 1 0 Rm(4) - - @syntax <reg_D> <reg_M> <shift_imm> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift_imm = DecodeImmShift('01', imm5) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/lsr_A8897.d b/src/arch/arm/v7/opdefs/lsr_A8897.d deleted file mode 100644 index 070a152..0000000 --- a/src/arch/arm/v7/opdefs/lsr_A8897.d +++ /dev/null @@ -1,90 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LSR (register) - -@desc Logical Shift Right (register) shifts a register value right by a variable number of bits, shifting in zeros, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. - -@encoding (t1) { - - @half 0 1 0 0 0 0 0 0 1 1 Rm(3) Rdn(3) - - @syntax "lsrs" <reg_DN> <reg_M> - - @conv { - - reg_DN = Register(Rdn) - reg_M = Register(Rm) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 1 0 0 0 1 S(1) Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) Rm(4) 0 0 1 1 Rn(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/mcr_A8898.d b/src/arch/arm/v7/opdefs/mcr_A8898.d deleted file mode 100644 index f710d5d..0000000 --- a/src/arch/arm/v7/opdefs/mcr_A8898.d +++ /dev/null @@ -1,109 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title MCR, MCR2 - -@desc Move to Coprocessor from ARM core register passes the value of an ARM core register to a coprocessor. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1, opc2, CRn, and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid MCR and MCR2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, MCR accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an MCR instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Traps to the hypervisor on page B1-1247. Note Because of the range of possible traps to Hyp mode, the MCR pseudocode does not show these possible traps. - -@encoding (T1) { - - @word 1 1 1 0 1 1 1 0 opc1(3) 0 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - - @syntax <cp> <undef_opc1> <reg_T> <creg_N> <creg_M> <?undef_opc2> - - @conv { - - reg_T = Register(Rt) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) - - } - -} - -@encoding (A1) { - - @word cond(4) 1 1 1 0 opc1(3) 0 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - - @syntax <cp> <undef_opc1> <reg_T> <creg_N> <creg_M> <?undef_opc2> - - @conv { - - reg_T = Register(Rt) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 1 1 0 opc1(3) 0 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - - @syntax "mcr2" <cp> <undef_opc1> <reg_T> <creg_N> <creg_M> <?undef_opc2> - - @conv { - - reg_T = Register(Rt) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) - - } - -} - -@encoding (A2) { - - @word 1 1 1 1 1 1 1 0 opc1(3) 0 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - - @syntax "mcr2" <cp> <undef_opc1> <reg_T> <creg_N> <creg_M> <?undef_opc2> - - @conv { - - reg_T = Register(Rt) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/mcrr_A8899.d b/src/arch/arm/v7/opdefs/mcrr_A8899.d deleted file mode 100644 index f643826..0000000 --- a/src/arch/arm/v7/opdefs/mcrr_A8899.d +++ /dev/null @@ -1,105 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title MCRR, MCRR2 - -@desc Move to Coprocessor from two ARM core registers passes the values of two ARM core registers to a coprocessor. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1 and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid MCRR and MCRR2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, MCRR accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an MCRR instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Traps to the hypervisor on page B1-1247. Note Because of the range of possible traps to Hyp mode, the MCRR pseudocode does not show these possible traps. - -@encoding (T1) { - - @word 1 1 1 0 1 1 0 0 0 1 0 0 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - - @syntax <cp> <undef_opc1> <reg_T> <reg_T2> <creg_M> - - @conv { - - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_M = CRegister(CRm) - - } - -} - -@encoding (A1) { - - @word cond(4) 1 1 0 0 0 1 0 0 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - - @syntax <cp> <undef_opc1> <reg_T> <reg_T2> <creg_M> - - @conv { - - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_M = CRegister(CRm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 1 0 0 0 1 0 0 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - - @syntax "mcrr2" <cp> <undef_opc1> <reg_T> <reg_T2> <creg_M> - - @conv { - - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_M = CRegister(CRm) - - } - -} - -@encoding (A2) { - - @word 1 1 1 1 1 1 0 0 0 1 0 0 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - - @syntax "mcrr2" <cp> <undef_opc1> <reg_T> <reg_T2> <creg_M> - - @conv { - - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_M = CRegister(CRm) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/mla_A88100.d b/src/arch/arm/v7/opdefs/mla_A88100.d deleted file mode 100644 index 5d4b4e4..0000000 --- a/src/arch/arm/v7/opdefs/mla_A88100.d +++ /dev/null @@ -1,69 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title MLA - -@desc Multiply Accumulate multiplies two register values, and adds a third register value. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values. In an ARM instruction, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 0 0 0 0 Rn(4) Ra(4) Rd(4) 0 0 0 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <reg_A> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 0 0 1 S(1) Rd(4) Ra(4) Rm(4) 1 0 0 1 Rn(4) - - @syntax <reg_D> <reg_N> <reg_M> <reg_A> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - setflags = (S == '1') - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/mls_A88101.d b/src/arch/arm/v7/opdefs/mls_A88101.d deleted file mode 100644 index 4d10be8..0000000 --- a/src/arch/arm/v7/opdefs/mls_A88101.d +++ /dev/null @@ -1,67 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title MLS - -@desc Multiply and Subtract multiplies two register values, and subtracts the product from a third register value. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 0 0 0 0 Rn(4) Ra(4) Rd(4) 0 0 0 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <reg_A> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 0 1 1 0 Rd(4) Ra(4) Rm(4) 1 0 0 1 Rn(4) - - @syntax <reg_D> <reg_N> <reg_M> <reg_A> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/mov_A88102.d b/src/arch/arm/v7/opdefs/mov_A88102.d deleted file mode 100644 index d96baab..0000000 --- a/src/arch/arm/v7/opdefs/mov_A88102.d +++ /dev/null @@ -1,124 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title MOV (immediate) - -@desc Move (immediate) writes an immediate value to the destination register. It can optionally update the condition flags based on the value. - -@encoding (t1) { - - @half 0 0 1 0 0 Rd(3) imm8(8) - - @syntax "movs" <reg_D> <imm32> - - @conv { - - reg_D = Register(Rd) - imm32 = ZeroExtend(imm8, 32) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 0 i(1) 0 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm8(8) - - @syntax <reg_D> <imm32> - - @conv { - - reg_D = Register(Rd) - setflags = (S == '1') - imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") - - } - -} - -@encoding (T3) { - - @word 1 1 1 1 0 i(1) 1 0 0 1 0 0 imm4(4) 0 imm3(3) Rd(4) imm8(8) - - @syntax "movw" <reg_D> <imm32> - - @conv { - - reg_D = Register(Rd) - imm32 = ZeroExtend(imm4:i:imm3:imm8, 32) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm12(12) - - @syntax <reg_D> <imm32> - - @conv { - - reg_D = Register(Rd) - setflags = (S == '1') - imm32 = ARMExpandImm_C(imm12, 0) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - -@encoding (A2) { - - @word cond(4) 0 0 1 1 0 0 0 0 imm4(4) Rd(4) imm12(12) - - @syntax "movw" <reg_D> <imm32> - - @conv { - - reg_D = Register(Rd) - imm32 = ZeroExtend(imm4:imm12, 32) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/mov_A88103.d b/src/arch/arm/v7/opdefs/mov_A88103.d deleted file mode 100644 index cd3d75a..0000000 --- a/src/arch/arm/v7/opdefs/mov_A88103.d +++ /dev/null @@ -1,80 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title MOV (register, Thumb) - -@desc Move (register) copies a value from a register to the destination register. It can optionally update the condition flags based on the value. - -@encoding (t1) { - - @half 0 1 0 0 0 1 1 0 D(1) Rm(4) Rd(3) - - @syntax <reg_D> <reg_M> - - @conv { - - reg_D = Register(D:Rd) - reg_M = Register(Rm) - - } - -} - -@encoding (t2) { - - @half 0 0 0 0 0 0 0 0 0 0 Rm(3) Rd(3) - - @syntax "movs" <reg_D> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - -} - -@encoding (T3) { - - @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 0 0 0 Rd(4) 0 0 0 0 Rm(4) - - @syntax <reg_D> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") - - } - -} - diff --git a/src/arch/arm/v7/opdefs/mov_A88104.d b/src/arch/arm/v7/opdefs/mov_A88104.d deleted file mode 100644 index d164983..0000000 --- a/src/arch/arm/v7/opdefs/mov_A88104.d +++ /dev/null @@ -1,50 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title MOV (register, ARM) - -@desc Move (register) copies a value from a register to the destination register. It can optionally update the condition flags based on the value. - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) 0 0 0 0 0 0 0 0 Rm(4) - - @syntax <reg_D> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/movt_A88106.d b/src/arch/arm/v7/opdefs/movt_A88106.d deleted file mode 100644 index 265d008..0000000 --- a/src/arch/arm/v7/opdefs/movt_A88106.d +++ /dev/null @@ -1,63 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title MOVT - -@desc Move Top writes an immediate value to the top halfword of the destination register. It does not affect the contents of the bottom halfword. - -@encoding (T1) { - - @word 1 1 1 1 0 i(1) 1 0 1 1 0 0 imm4(4) 0 imm3(3) Rd(4) imm8(8) - - @syntax <reg_D> <imm16> - - @conv { - - reg_D = Register(Rd) - imm16 = BuildImm16(imm4:i:imm3:imm8) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 1 0 1 0 0 imm4(4) Rd(4) imm12(12) - - @syntax <reg_D> <imm16> - - @conv { - - reg_D = Register(Rd) - imm16 = BuildImm16(imm4:imm12) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/mrc_A88107.d b/src/arch/arm/v7/opdefs/mrc_A88107.d deleted file mode 100644 index fb9714c..0000000 --- a/src/arch/arm/v7/opdefs/mrc_A88107.d +++ /dev/null @@ -1,109 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title MRC, MRC2 - -@desc Move to ARM core register from Coprocessor causes a coprocessor to transfer a value to an ARM core register or to the condition flags. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1, opc2, CRn, and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid MRC and MRC2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, MRC accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an MRC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Traps to the hypervisor on page B1-1247. Note Because of the range of possible traps to Hyp mode, the MRC pseudocode does not show these possible traps. - -@encoding (T1) { - - @word 1 1 1 0 1 1 1 0 opc1(3) 1 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - - @syntax <cp> <undef_opc1> <reg_T> <creg_N> <creg_M> <?undef_opc2> - - @conv { - - reg_T = Register(Rt) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) - - } - -} - -@encoding (A1) { - - @word cond(4) 1 1 1 0 opc1(3) 1 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - - @syntax <cp> <undef_opc1> <reg_T> <creg_N> <creg_M> <?undef_opc2> - - @conv { - - reg_T = Register(Rt) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 1 1 0 opc1(3) 1 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - - @syntax "mrc2" <cp> <undef_opc1> <reg_T> <creg_N> <creg_M> <?undef_opc2> - - @conv { - - reg_T = Register(Rt) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) - - } - -} - -@encoding (A2) { - - @word 1 1 1 1 1 1 1 0 opc1(3) 1 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - - @syntax "mrc2" <cp> <undef_opc1> <reg_T> <creg_N> <creg_M> <?undef_opc2> - - @conv { - - reg_T = Register(Rt) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/mrrc_A88108.d b/src/arch/arm/v7/opdefs/mrrc_A88108.d deleted file mode 100644 index 026c0ef..0000000 --- a/src/arch/arm/v7/opdefs/mrrc_A88108.d +++ /dev/null @@ -1,105 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title MRRC, MRRC2 - -@desc Move to two ARM core registers from Coprocessor causes a coprocessor to transfer values to two ARM core registers. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1 and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid MRRC and MRRC2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, MRRC accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an MRRC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Traps to the hypervisor on page B1-1247. Note Because of the range of possible traps to Hyp mode, the MRRC pseudocode does not show these possible traps. - -@encoding (T1) { - - @word 1 1 1 0 1 1 0 0 0 1 0 1 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - - @syntax <cp> <opc> <reg_T> <reg_T2> <creg_M> - - @conv { - - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - cp = CoProcessor(coproc) - opc = RawValue(opc1) - creg_M = CRegister(CRm) - - } - -} - -@encoding (A1) { - - @word cond(4) 1 1 0 0 0 1 0 1 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - - @syntax <cp> <opc> <reg_T> <reg_T2> <creg_M> - - @conv { - - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - cp = CoProcessor(coproc) - opc = RawValue(opc1) - creg_M = CRegister(CRm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 1 0 0 0 1 0 1 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - - @syntax "mrrc2" <cp> <opc> <reg_T> <reg_T2> <creg_M> - - @conv { - - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - cp = CoProcessor(coproc) - opc = RawValue(opc1) - creg_M = CRegister(CRm) - - } - -} - -@encoding (A2) { - - @word 1 1 1 1 1 1 0 0 0 1 0 1 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - - @syntax "mrrc2" <cp> <opc> <reg_T> <reg_T2> <creg_M> - - @conv { - - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - cp = CoProcessor(coproc) - opc = RawValue(opc1) - creg_M = CRegister(CRm) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/mul_A88114.d b/src/arch/arm/v7/opdefs/mul_A88114.d deleted file mode 100644 index fa250b7..0000000 --- a/src/arch/arm/v7/opdefs/mul_A88114.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title MUL - -@desc Multiply multiplies two register values. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values. Optionally, it can update the condition flags based on the result. In the Thumb instruction set, this option is limited to only a few forms of the instruction. Use of this option adversely affects performance on many processor implementations. - -@encoding (t1) { - - @half 0 1 0 0 0 0 1 1 0 1 Rn(3) Rdm(3) - - @syntax "muls" <reg_DM_1> <reg_N> <reg_DM_2> - - @conv { - - reg_N = Register(Rn) - reg_DM_1 = Register(Rdm) - reg_DM_2 = Register(Rdm) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 1 1 0 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 0 0 0 S(1) Rd(4) 0 0 0 0 Rm(4) 1 0 0 1 Rn(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/mvn_A88115.d b/src/arch/arm/v7/opdefs/mvn_A88115.d deleted file mode 100644 index 2955439..0000000 --- a/src/arch/arm/v7/opdefs/mvn_A88115.d +++ /dev/null @@ -1,72 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title MVN (immediate) - -@desc Bitwise NOT (immediate) writes the bitwise inverse of an immediate value to the destination register. It can optionally update the condition flags based on the value. - -@encoding (T1) { - - @word 1 1 1 1 0 i(1) 0 0 0 1 1 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm8(8) - - @syntax <reg_D> <imm32> - - @conv { - - reg_D = Register(Rd) - setflags = (S == '1') - imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 1 1 1 1 S(1) 0 0 0 0 Rd(4) imm12(12) - - @syntax <reg_D> <imm32> - - @conv { - - reg_D = Register(Rd) - setflags = (S == '1') - imm32 = ARMExpandImm_C(imm12, 0) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/mvn_A88116.d b/src/arch/arm/v7/opdefs/mvn_A88116.d deleted file mode 100644 index 1f3f390..0000000 --- a/src/arch/arm/v7/opdefs/mvn_A88116.d +++ /dev/null @@ -1,90 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title MVN (register) - -@desc Bitwise NOT (register) writes the bitwise inverse of a register value to the destination register. It can optionally update the condition flags based on the result. - -@encoding (t1) { - - @half 0 1 0 0 0 0 1 1 1 1 Rm(3) Rd(3) - - @syntax "mvns" <reg_D> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - -} - -@encoding (T2) { - - @word 1 1 1 0 1 0 1 0 0 1 1 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - - @syntax <reg_D> <reg_M> <?shift> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 1 1 S(1) 0 0 0 0 Rd(4) imm5(5) type(2) 0 Rm(4) - - @syntax <reg_D> <reg_M> <?shift> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/mvn_A88117.d b/src/arch/arm/v7/opdefs/mvn_A88117.d deleted file mode 100644 index cc6ef16..0000000 --- a/src/arch/arm/v7/opdefs/mvn_A88117.d +++ /dev/null @@ -1,51 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title MVN (register-shifted register) - -@desc Bitwise NOT (register-shifted register) writes the bitwise inverse of a register-shifted register value to the destination register. It can optionally update the condition flags based on the result. - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 1 1 S(1) 0 0 0 0 Rd(4) Rs(4) 0 type(2) 1 Rm(4) - - @syntax <reg_D> <reg_M> <reg_shift> - - @conv { - - reg_shift = RegisterShift(type, Rs) - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/nop_A88119.d b/src/arch/arm/v7/opdefs/nop_A88119.d deleted file mode 100644 index 84c495a..0000000 --- a/src/arch/arm/v7/opdefs/nop_A88119.d +++ /dev/null @@ -1,53 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title NOP - -@desc No Operation does nothing. This instruction can be used for instruction alignment purposes. See Pre-UAL pseudo-instruction NOP on page AppxH-2472 for details of NOP before the introduction of UAL and the ARMv6K and ARMv6T2 architecture variants. Note The timing effects of including a NOP instruction in a program are not guaranteed. It can increase execution time, leave it unchanged, or even reduce it. Therefore, NOP instructions are not suitable for timing loops. - -@encoding (t1) { - - @half 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 - -} - -@encoding (T2) { - - @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - - @syntax ".W" - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/orn_A88120.d b/src/arch/arm/v7/opdefs/orn_A88120.d deleted file mode 100644 index b823b6c..0000000 --- a/src/arch/arm/v7/opdefs/orn_A88120.d +++ /dev/null @@ -1,50 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title ORN (immediate) - -@desc Bitwise OR NOT (immediate) performs a bitwise (inclusive) OR of a register value and the complement of an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -@encoding (T1) { - - @word 1 1 1 1 0 i(1) 0 0 0 1 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - - @syntax <reg_D> <reg_N> <imm32> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - - } - -} - diff --git a/src/arch/arm/v7/opdefs/orn_A88121.d b/src/arch/arm/v7/opdefs/orn_A88121.d deleted file mode 100644 index f1523ec..0000000 --- a/src/arch/arm/v7/opdefs/orn_A88121.d +++ /dev/null @@ -1,51 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title ORN (register) - -@desc Bitwise OR NOT (register) performs a bitwise (inclusive) OR of a register value and the complement of an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -@encoding (T1) { - - @word 1 1 1 0 1 0 1 0 0 1 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <?shift> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - - } - -} - diff --git a/src/arch/arm/v7/opdefs/orr_A88122.d b/src/arch/arm/v7/opdefs/orr_A88122.d deleted file mode 100644 index 766b5ee..0000000 --- a/src/arch/arm/v7/opdefs/orr_A88122.d +++ /dev/null @@ -1,74 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title ORR (immediate) - -@desc Bitwise OR (immediate) performs a bitwise (inclusive) OR of a register value and an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -@encoding (T1) { - - @word 1 1 1 1 0 i(1) 0 0 0 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - - @syntax <reg_D> <reg_N> <imm32> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 1 1 0 0 S(1) Rn(4) Rd(4) imm12(12) - - @syntax <reg_D> <reg_N> <imm32> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ARMExpandImm_C(imm12, 0) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/orr_A88123.d b/src/arch/arm/v7/opdefs/orr_A88123.d deleted file mode 100644 index 2395c89..0000000 --- a/src/arch/arm/v7/opdefs/orr_A88123.d +++ /dev/null @@ -1,92 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title ORR (register) - -@desc Bitwise OR (register) performs a bitwise (inclusive) OR of a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -@encoding (t1) { - - @half 0 1 0 0 0 0 1 1 0 0 Rm(3) Rdn(3) - - @syntax "orrs" <reg_DN> <reg_M> - - @conv { - - reg_DN = Register(Rdn) - reg_M = Register(Rm) - - } - -} - -@encoding (T2) { - - @word 1 1 1 0 1 0 1 0 0 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <?shift> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 0 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <?shift> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/orr_A88124.d b/src/arch/arm/v7/opdefs/orr_A88124.d deleted file mode 100644 index f4d78b9..0000000 --- a/src/arch/arm/v7/opdefs/orr_A88124.d +++ /dev/null @@ -1,52 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title ORR (register-shifted register) - -@desc Bitwise OR (register-shifted register) performs a bitwise (inclusive) OR of a register value and a register-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 0 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <reg_shift> - - @conv { - - reg_shift = RegisterShift(type, Rs) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/pop_A88131.d b/src/arch/arm/v7/opdefs/pop_A88131.d deleted file mode 100644 index 2dee09a..0000000 --- a/src/arch/arm/v7/opdefs/pop_A88131.d +++ /dev/null @@ -1,87 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title POP (Thumb) - -@desc Pop Multiple Registers loads multiple registers from the stack, loading from consecutive memory locations starting at the address in SP, and updates SP to point just above the loaded data. - -@encoding (t1) { - - @half 1 0 1 1 1 1 0 P(1) register_list(8) - - @syntax <registers> - - @conv { - - registers = RegistersList(P:'0000000':register_list) - - } - - @hooks { - - link = handle_armv7_return_from_pop - - } - -} - -@encoding (T2) { - - @word 1 1 1 0 1 0 0 0 1 0 1 1 1 1 0 1 P(1) M(1) 0 register_list(13) - - @syntax ".W" <registers> - - @conv { - - registers = RegistersList(P:M:'0':register_list) - - } - - @hooks { - - link = handle_armv7_return_from_pop - - } - -} - -@encoding (T3) { - - @word 1 1 1 1 1 0 0 0 0 1 0 1 1 1 0 1 Rt(4) 1 0 1 1 0 0 0 0 0 1 0 0 - - @syntax ".W" <registers> - - @conv { - - registers = RegistersList(1 << Rt) - - } - - @hooks { - - link = handle_armv7_return_from_pop - - } - -} - diff --git a/src/arch/arm/v7/opdefs/pop_A88132.d b/src/arch/arm/v7/opdefs/pop_A88132.d deleted file mode 100644 index 27bbf3b..0000000 --- a/src/arch/arm/v7/opdefs/pop_A88132.d +++ /dev/null @@ -1,79 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title POP (ARM) - -@desc Pop Multiple Registers loads multiple registers from the stack, loading from consecutive memory locations starting at the address in SP, and updates SP to point just above the loaded data. - -@encoding (A1) { - - @word cond(4) 1 0 0 0 1 0 1 1 1 1 0 1 register_list(16) - - @syntax <registers> - - @conv { - - registers = RegistersList(register_list) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - - @hooks { - - link = handle_armv7_return_from_pop - - } - -} - -@encoding (A2) { - - @word cond(4) 0 1 0 0 1 0 0 1 1 1 0 1 Rt(4) 0 0 0 0 0 0 0 0 0 1 0 0 - - @syntax <registers> - - @conv { - - registers = RegistersList(1 << Rt) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - - @hooks { - - link = handle_armv7_return_from_pop - - } - -} - diff --git a/src/arch/arm/v7/opdefs/push_A88133.d b/src/arch/arm/v7/opdefs/push_A88133.d deleted file mode 100644 index 14fc3e9..0000000 --- a/src/arch/arm/v7/opdefs/push_A88133.d +++ /dev/null @@ -1,109 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title PUSH - -@desc Push Multiple Registers stores multiple registers to the stack, storing to consecutive memory locations ending just below the address in SP, and updates SP to point to the start of the stored data. - -@encoding (t1) { - - @half 1 0 1 1 0 1 0 M(1) register_list(8) - - @syntax <registers> - - @conv { - - registers = RegistersList('0':M:'000000':register_list) - - } - -} - -@encoding (T2) { - - @word 1 1 1 0 1 0 0 1 0 0 1 0 1 1 0 1 0 M(1) 0 register_list(13) - - @syntax ".W" <registers> - - @conv { - - registers = RegistersList('0':M:'0':register_list) - - } - -} - -@encoding (T3) { - - @word 1 1 1 1 1 0 0 0 0 1 0 0 1 1 0 1 Rt(4) 1 1 0 1 0 0 0 0 0 1 0 0 - - @syntax ".W" <registers> - - @conv { - - registers = Zeros(16) - - } - -} - -@encoding (A1) { - - @word cond(4) 1 0 0 1 0 0 1 0 1 1 0 1 register_list(16) - - @syntax <registers> - - @conv { - - registers = RegistersList(register_list) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - -@encoding (A2) { - - @word cond(4) 0 1 0 1 0 0 1 0 1 1 0 1 Rt(4) 0 0 0 0 0 0 0 0 0 1 0 0 - - @syntax <registers> - - @conv { - - registers = Zeros(16) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/qadd16_A88135.d b/src/arch/arm/v7/opdefs/qadd16_A88135.d deleted file mode 100644 index 15af29d..0000000 --- a/src/arch/arm/v7/opdefs/qadd16_A88135.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title QADD16 - -@desc Saturating Add 16 performs two 16-bit integer additions, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/qadd8_A88136.d b/src/arch/arm/v7/opdefs/qadd8_A88136.d deleted file mode 100644 index a71b251..0000000 --- a/src/arch/arm/v7/opdefs/qadd8_A88136.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title QADD8 - -@desc Saturating Add 8 performs four 8-bit integer additions, saturates the results to the 8-bit signed integer range –27 ≤ x ≤ 27 – 1, and writes the results to the destination register. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/qadd_A88134.d b/src/arch/arm/v7/opdefs/qadd_A88134.d deleted file mode 100644 index f932983..0000000 --- a/src/arch/arm/v7/opdefs/qadd_A88134.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title QADD - -@desc Saturating Add adds two register values, saturates the result to the 32-bit signed integer range –231 to (231 – 1), and writes the result to the destination register. If saturation occurs, it sets the Q flag in the APSR. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 1 0 0 0 Rm(4) - - @syntax <reg_D> <reg_M> <reg_N> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 0 0 0 Rn(4) Rd(4) 0 0 0 0 0 1 0 1 Rm(4) - - @syntax <reg_D> <reg_M> <reg_N> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/qasx_A88137.d b/src/arch/arm/v7/opdefs/qasx_A88137.d deleted file mode 100644 index 68251ca..0000000 --- a/src/arch/arm/v7/opdefs/qasx_A88137.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title QASX - -@desc Saturating Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one 16-bit integer addition and one 16-bit subtraction, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/qdadd_A88138.d b/src/arch/arm/v7/opdefs/qdadd_A88138.d deleted file mode 100644 index c40cdcd..0000000 --- a/src/arch/arm/v7/opdefs/qdadd_A88138.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title QDADD - -@desc Saturating Double and Add adds a doubled register value to another register value, and writes the result to the destination register. Both the doubling and the addition have their results saturated to the 32-bit signed integer range –231 ≤ x ≤ 231 – 1. If saturation occurs in either operation, it sets the Q flag in the APSR. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 1 0 0 1 Rm(4) - - @syntax <reg_D> <reg_M> <reg_N> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 1 0 0 Rn(4) Rd(4) 0 0 0 0 0 1 0 1 Rm(4) - - @syntax <reg_D> <reg_M> <reg_N> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/qdsub_A88139.d b/src/arch/arm/v7/opdefs/qdsub_A88139.d deleted file mode 100644 index 87bd083..0000000 --- a/src/arch/arm/v7/opdefs/qdsub_A88139.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title QDSUB - -@desc Saturating Double and Subtract subtracts a doubled register value from another register value, and writes the result to the destination register. Both the doubling and the subtraction have their results saturated to the 32-bit signed integer range –231 ≤ x ≤ 231 – 1. If saturation occurs in either operation, it sets the Q flag in the APSR. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 1 0 1 1 Rm(4) - - @syntax <reg_D> <reg_M> <reg_N> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 1 1 0 Rn(4) Rd(4) 0 0 0 0 0 1 0 1 Rm(4) - - @syntax <reg_D> <reg_M> <reg_N> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/qsax_A88140.d b/src/arch/arm/v7/opdefs/qsax_A88140.d deleted file mode 100644 index df24cf8..0000000 --- a/src/arch/arm/v7/opdefs/qsax_A88140.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title QSAX - -@desc Saturating Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one 16-bit integer subtraction and one 16-bit addition, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/qsub16_A88142.d b/src/arch/arm/v7/opdefs/qsub16_A88142.d deleted file mode 100644 index 5b2c96b..0000000 --- a/src/arch/arm/v7/opdefs/qsub16_A88142.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title QSUB16 - -@desc Saturating Subtract 16 performs two 16-bit integer subtractions, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 0 1 1 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/qsub8_A88143.d b/src/arch/arm/v7/opdefs/qsub8_A88143.d deleted file mode 100644 index 270a99d..0000000 --- a/src/arch/arm/v7/opdefs/qsub8_A88143.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title QSUB8 - -@desc Saturating Subtract 8 performs four 8-bit integer subtractions, saturates the results to the 8-bit signed integer range –27 ≤ x ≤ 27 – 1, and writes the results to the destination register. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 1 1 1 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/qsub_A88141.d b/src/arch/arm/v7/opdefs/qsub_A88141.d deleted file mode 100644 index c60ec57..0000000 --- a/src/arch/arm/v7/opdefs/qsub_A88141.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title QSUB - -@desc Saturating Subtract subtracts one register value from another register value, saturates the result to the 32-bit signed integer range –231 ≤ x ≤ 231 – 1, and writes the result to the destination register. If saturation occurs, it sets the Q flag in the APSR. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 1 0 1 0 Rm(4) - - @syntax <reg_D> <reg_M> <reg_N> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 0 1 0 Rn(4) Rd(4) 0 0 0 0 0 1 0 1 Rm(4) - - @syntax <reg_D> <reg_M> <reg_N> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/rbit_A88144.d b/src/arch/arm/v7/opdefs/rbit_A88144.d deleted file mode 100644 index 7f2bdb6..0000000 --- a/src/arch/arm/v7/opdefs/rbit_A88144.d +++ /dev/null @@ -1,63 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title RBIT - -@desc Reverse Bits reverses the bit order in a 32-bit register. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 1 Rm(4) 1 1 1 1 Rd(4) 1 0 1 0 Rm(4) - - @syntax <reg_D> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 1 1 1 1 1 1 1 Rd(4) 1 1 1 1 0 0 1 1 Rm(4) - - @syntax <reg_D> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/rev16_A88146.d b/src/arch/arm/v7/opdefs/rev16_A88146.d deleted file mode 100644 index 53b9a82..0000000 --- a/src/arch/arm/v7/opdefs/rev16_A88146.d +++ /dev/null @@ -1,78 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title REV16 - -@desc Byte-Reverse Packed Halfword reverses the byte order in each16-bit halfword of a 32-bit register. - -@encoding (t1) { - - @half 1 0 1 1 1 0 1 0 0 1 Rm(3) Rd(3) - - @syntax <reg_D> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 1 0 1 0 0 1 Rm(4) 1 1 1 1 Rd(4) 1 0 0 1 Rm(4) - - @syntax ".W" <reg_D> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 0 1 1 1 1 1 1 Rd(4) 1 1 1 1 1 0 1 1 Rm(4) - - @syntax <reg_D> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/rev_A88145.d b/src/arch/arm/v7/opdefs/rev_A88145.d deleted file mode 100644 index 2fe305d..0000000 --- a/src/arch/arm/v7/opdefs/rev_A88145.d +++ /dev/null @@ -1,78 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title REV - -@desc Byte-Reverse Word reverses the byte order in a 32-bit register. - -@encoding (t1) { - - @half 1 0 1 1 1 0 1 0 0 0 Rm(3) Rd(3) - - @syntax <reg_D> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 1 0 1 0 0 1 Rm(4) 1 1 1 1 Rd(4) 1 0 0 0 Rm(4) - - @syntax ".W" <reg_D> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 0 1 1 1 1 1 1 Rd(4) 1 1 1 1 0 0 1 1 Rm(4) - - @syntax <reg_D> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/revsh_A88147.d b/src/arch/arm/v7/opdefs/revsh_A88147.d deleted file mode 100644 index 551582c..0000000 --- a/src/arch/arm/v7/opdefs/revsh_A88147.d +++ /dev/null @@ -1,78 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title REVSH - -@desc Byte-Reverse Signed Halfword reverses the byte order in the lower 16-bit halfword of a 32-bit register, and sign-extends the result to 32 bits. - -@encoding (t1) { - - @half 1 0 1 1 1 0 1 0 1 1 Rm(3) Rd(3) - - @syntax <reg_D> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 1 0 1 0 0 1 Rm(4) 1 1 1 1 Rd(4) 1 0 1 1 Rm(4) - - @syntax ".W" <reg_D> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 1 1 1 1 1 1 1 Rd(4) 1 1 1 1 1 0 1 1 Rm(4) - - @syntax <reg_D> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ror_A88149.d b/src/arch/arm/v7/opdefs/ror_A88149.d deleted file mode 100644 index 7e061c6..0000000 --- a/src/arch/arm/v7/opdefs/ror_A88149.d +++ /dev/null @@ -1,74 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title ROR (immediate) - -@desc Rotate Right (immediate) provides the value of the contents of a register rotated by a constant value. The bits that are rotated off the right end are inserted into the vacated bit positions on the left. It can optionally update the condition flags based on the result. - -@encoding (T1) { - - @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 1 1 Rm(4) - - @syntax <reg_D> <reg_M> <shift_imm> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift_imm = DecodeImmShift('11', imm3:imm2) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 1 1 0 Rm(4) - - @syntax <reg_D> <reg_M> <shift_imm> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift_imm = DecodeImmShift('11', imm5) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ror_A88150.d b/src/arch/arm/v7/opdefs/ror_A88150.d deleted file mode 100644 index c046bf7..0000000 --- a/src/arch/arm/v7/opdefs/ror_A88150.d +++ /dev/null @@ -1,90 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title ROR (register) - -@desc Rotate Right (register) provides the value of the contents of a register rotated by a variable number of bits. The bits that are rotated off the right end are inserted into the vacated bit positions on the left. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. - -@encoding (t1) { - - @half 0 1 0 0 0 0 0 1 1 1 Rm(3) Rdn(3) - - @syntax "rors" <reg_DN> <reg_M> - - @conv { - - reg_DN = Register(Rdn) - reg_M = Register(Rm) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 1 0 0 1 1 S(1) Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) Rm(4) 0 1 1 1 Rn(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/rrx_A88151.d b/src/arch/arm/v7/opdefs/rrx_A88151.d deleted file mode 100644 index 4debd42..0000000 --- a/src/arch/arm/v7/opdefs/rrx_A88151.d +++ /dev/null @@ -1,72 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title RRX - -@desc Rotate Right with Extend provides the value of the contents of a register shifted right by one place, with the Carry flag shifted into bit[31]. RRX can optionally update the condition flags based on the result. In that case, bit[0] is shifted into the Carry flag. - -@encoding (T1) { - - @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 0 0 0 Rd(4) 0 0 1 1 Rm(4) - - @syntax <reg_D> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) 0 0 0 0 0 1 1 0 Rm(4) - - @syntax <reg_D> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/rsb_A88152.d b/src/arch/arm/v7/opdefs/rsb_A88152.d deleted file mode 100644 index ea53373..0000000 --- a/src/arch/arm/v7/opdefs/rsb_A88152.d +++ /dev/null @@ -1,91 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title RSB (immediate) - -@desc Reverse Subtract (immediate) subtracts a register value from an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -@encoding (t1) { - - @half 0 1 0 0 0 0 1 0 0 1 Rn(3) Rd(3) - - @syntax "rsbs" <reg_D> <reg_N> <imm32> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = Zeros(32) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 0 i(1) 0 1 1 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - - @syntax <reg_D> <reg_N> <imm32> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ThumbExpandImm(i:imm3:imm8) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 0 0 1 1 S(1) Rn(4) Rd(4) imm12(12) - - @syntax <reg_D> <reg_N> <imm32> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ARMExpandImm(imm12) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/rsb_A88153.d b/src/arch/arm/v7/opdefs/rsb_A88153.d deleted file mode 100644 index f4a6d61..0000000 --- a/src/arch/arm/v7/opdefs/rsb_A88153.d +++ /dev/null @@ -1,76 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title RSB (register) - -@desc Reverse Subtract (register) subtracts a register value from an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -@encoding (T1) { - - @word 1 1 1 0 1 0 1 1 1 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <?shift> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 0 1 1 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <?shift> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/rsb_A88154.d b/src/arch/arm/v7/opdefs/rsb_A88154.d deleted file mode 100644 index 9ccf559..0000000 --- a/src/arch/arm/v7/opdefs/rsb_A88154.d +++ /dev/null @@ -1,52 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title RSB (register-shifted register) - -@desc Reverse Subtract (register-shifted register) subtracts a register value from a register-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -@encoding (A1) { - - @word cond(4) 0 0 0 0 0 1 1 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <reg_shift> - - @conv { - - reg_shift = RegisterShift(type, Rs) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/rsc_A88155.d b/src/arch/arm/v7/opdefs/rsc_A88155.d deleted file mode 100644 index fc5f8b6..0000000 --- a/src/arch/arm/v7/opdefs/rsc_A88155.d +++ /dev/null @@ -1,51 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title RSC (immediate) - -@desc Reverse Subtract with Carry (immediate) subtracts a register value and the value of NOT (Carry flag) from an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -@encoding (A1) { - - @word cond(4) 0 0 1 0 1 1 1 S(1) Rn(4) Rd(4) imm12(12) - - @syntax <reg_D> <reg_N> <imm32> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ARMExpandImm(imm12) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/rsc_A88156.d b/src/arch/arm/v7/opdefs/rsc_A88156.d deleted file mode 100644 index 70829cd..0000000 --- a/src/arch/arm/v7/opdefs/rsc_A88156.d +++ /dev/null @@ -1,52 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title RSC (register) - -@desc Reverse Subtract with Carry (register) subtracts a register value and the value of NOT (Carry flag) from an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -@encoding (A1) { - - @word cond(4) 0 0 0 0 1 1 1 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <?shift> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/rsc_A88157.d b/src/arch/arm/v7/opdefs/rsc_A88157.d deleted file mode 100644 index 4fa276d..0000000 --- a/src/arch/arm/v7/opdefs/rsc_A88157.d +++ /dev/null @@ -1,52 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title RSC (register-shifted register) - -@desc Reverse Subtract (register-shifted register) subtracts a register value and the value of NOT (Carry flag) from a register-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -@encoding (A1) { - - @word cond(4) 0 0 0 0 1 1 1 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <reg_shift> - - @conv { - - reg_shift = RegisterShift(type, Rs) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/sadd16_A88158.d b/src/arch/arm/v7/opdefs/sadd16_A88158.d deleted file mode 100644 index 51ad948..0000000 --- a/src/arch/arm/v7/opdefs/sadd16_A88158.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SADD16 - -@desc Signed Add 16 performs two 16-bit signed integer additions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the additions. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 0 0 1 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/sadd8_A88159.d b/src/arch/arm/v7/opdefs/sadd8_A88159.d deleted file mode 100644 index 463c968..0000000 --- a/src/arch/arm/v7/opdefs/sadd8_A88159.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SADD8 - -@desc Signed Add 8 performs four 8-bit signed integer additions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the additions. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 0 0 1 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/sasx_A88160.d b/src/arch/arm/v7/opdefs/sasx_A88160.d deleted file mode 100644 index a0529cb..0000000 --- a/src/arch/arm/v7/opdefs/sasx_A88160.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SASX - -@desc Signed Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one 16-bit integer addition and one 16-bit subtraction, and writes the results to the destination register. It sets the APSR.GE bits according to the results. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 0 0 1 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/sbc_A88161.d b/src/arch/arm/v7/opdefs/sbc_A88161.d deleted file mode 100644 index 4ea776a..0000000 --- a/src/arch/arm/v7/opdefs/sbc_A88161.d +++ /dev/null @@ -1,74 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SBC (immediate) - -@desc Subtract with Carry (immediate) subtracts an immediate value and the value of NOT (Carry flag) from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -@encoding (T1) { - - @word 1 1 1 1 0 i(1) 0 1 0 1 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - - @syntax <reg_D> <reg_N> <imm32> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ThumbExpandImm(i:imm3:imm8) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 0 1 1 0 S(1) Rn(4) Rd(4) imm12(12) - - @syntax <reg_D> <reg_N> <imm32> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ARMExpandImm(imm12) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/sbc_A88162.d b/src/arch/arm/v7/opdefs/sbc_A88162.d deleted file mode 100644 index b6e660a..0000000 --- a/src/arch/arm/v7/opdefs/sbc_A88162.d +++ /dev/null @@ -1,92 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SBC (register) - -@desc Subtract with Carry (register) subtracts an optionally-shifted register value and the value of NOT (Carry flag) from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -@encoding (t1) { - - @half 0 1 0 0 0 0 0 1 1 0 Rm(3) Rdn(3) - - @syntax "sbcs" <reg_DN> <reg_M> - - @conv { - - reg_DN = Register(Rdn) - reg_M = Register(Rm) - - } - -} - -@encoding (T2) { - - @word 1 1 1 0 1 0 1 1 0 1 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <?shift> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 1 1 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <?shift> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/sbc_A88163.d b/src/arch/arm/v7/opdefs/sbc_A88163.d deleted file mode 100644 index 0500edc..0000000 --- a/src/arch/arm/v7/opdefs/sbc_A88163.d +++ /dev/null @@ -1,52 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SBC (register-shifted register) - -@desc Subtract with Carry (register-shifted register) subtracts a register-shifted register value and the value of NOT (Carry flag) from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -@encoding (A1) { - - @word cond(4) 0 0 0 0 1 1 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <reg_shift> - - @conv { - - reg_shift = RegisterShift(type, Rs) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/sbfx_A88164.d b/src/arch/arm/v7/opdefs/sbfx_A88164.d deleted file mode 100644 index 486db3c..0000000 --- a/src/arch/arm/v7/opdefs/sbfx_A88164.d +++ /dev/null @@ -1,67 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SBFX - -@desc Signed Bit Field Extract extracts any number of adjacent bits at any position from a register, sign-extends them to 32 bits, and writes the result to the destination register. - -@encoding (T1) { - - @word 1 1 1 1 0 0 1 1 0 1 0 0 Rn(4) 0 imm3(3) Rd(4) imm2(2) 0 widthm1(5) - - @syntax <reg_D> <reg_N> <lsbit> <width> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - lsbit = UInt(imm3:imm2) - width = IncWidth(widthm1) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 1 1 0 1 widthm1(5) Rd(4) lsb(5) 1 0 1 Rn(4) - - @syntax <reg_D> <reg_N> <lsbit> <width> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - lsbit = UInt(lsb) - width = IncWidth(widthm1) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/sdiv_A88165.d b/src/arch/arm/v7/opdefs/sdiv_A88165.d deleted file mode 100644 index 19ebfa9..0000000 --- a/src/arch/arm/v7/opdefs/sdiv_A88165.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SDIV - -@desc Signed Divide divides a 32-bit signed integer register value by a 32-bit signed integer register value, and writes the result to the destination register. The condition flags are not affected. See ARMv7 implementation requirements and options for the divide instructions on page A4-172 for more information about this instruction. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 1 1 1 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 1 0 0 0 1 Rd(4) 1 1 1 1 Rm(4) 0 0 0 1 Rn(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/sel_A88166.d b/src/arch/arm/v7/opdefs/sel_A88166.d deleted file mode 100644 index cb32ed6..0000000 --- a/src/arch/arm/v7/opdefs/sel_A88166.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SEL - -@desc Select Bytes selects each byte of its result from either its first operand or its second operand, according to the values of the GE flags. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 1 0 0 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 0 0 0 Rn(4) Rd(4) 1 1 1 1 1 0 1 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/setend_A88167.d b/src/arch/arm/v7/opdefs/setend_A88167.d deleted file mode 100644 index e549c50..0000000 --- a/src/arch/arm/v7/opdefs/setend_A88167.d +++ /dev/null @@ -1,55 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SETEND - -@desc Set Endianness writes a new value to ENDIANSTATE. - -@encoding (t1) { - - @half 1 0 1 1 0 1 1 0 0 1 0 1 E(1) 0 0 0 - - @syntax <set_bigend> - - @conv { - - set_bigend = EndianState(E == '1') - - } - -} - -@encoding (A1) { - - @word 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 E(1) 0 0 0 0 0 0 0 0 0 - - @syntax <set_bigend> - - @conv { - - set_bigend = EndianState(E == '1') - - } - -} - diff --git a/src/arch/arm/v7/opdefs/sev_A88168.d b/src/arch/arm/v7/opdefs/sev_A88168.d deleted file mode 100644 index 2bd9af4..0000000 --- a/src/arch/arm/v7/opdefs/sev_A88168.d +++ /dev/null @@ -1,53 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SEV - -@desc Send Event is a hint instruction. It causes an event to be signaled to all processors in the multiprocessor system. For more information, see Wait For Event and Send Event on page B1-1199. - -@encoding (t1) { - - @half 1 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 - -} - -@encoding (T2) { - - @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 - - @syntax ".W" - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/shadd16_A88169.d b/src/arch/arm/v7/opdefs/shadd16_A88169.d deleted file mode 100644 index 22baa05..0000000 --- a/src/arch/arm/v7/opdefs/shadd16_A88169.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SHADD16 - -@desc Signed Halving Add 16 performs two signed 16-bit integer additions, halves the results, and writes the results to the destination register. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/shadd8_A88170.d b/src/arch/arm/v7/opdefs/shadd8_A88170.d deleted file mode 100644 index bfc3031..0000000 --- a/src/arch/arm/v7/opdefs/shadd8_A88170.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SHADD8 - -@desc Signed Halving Add 8 performs four signed 8-bit integer additions, halves the results, and writes the results to the destination register. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/shasx_A88171.d b/src/arch/arm/v7/opdefs/shasx_A88171.d deleted file mode 100644 index 71d241b..0000000 --- a/src/arch/arm/v7/opdefs/shasx_A88171.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SHASX - -@desc Signed Halving Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one signed 16-bit integer addition and one signed 16-bit subtraction, halves the results, and writes the results to the destination register. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/shsax_A88172.d b/src/arch/arm/v7/opdefs/shsax_A88172.d deleted file mode 100644 index 8794738..0000000 --- a/src/arch/arm/v7/opdefs/shsax_A88172.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SHSAX - -@desc Signed Halving Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one signed 16-bit integer subtraction and one signed 16-bit addition, halves the results, and writes the results to the destination register. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/shsub16_A88173.d b/src/arch/arm/v7/opdefs/shsub16_A88173.d deleted file mode 100644 index f7099f2..0000000 --- a/src/arch/arm/v7/opdefs/shsub16_A88173.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SHSUB16 - -@desc Signed Halving Subtract 16 performs two signed 16-bit integer subtractions, halves the results, and writes the results to the destination register. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 0 1 1 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/shsub8_A88174.d b/src/arch/arm/v7/opdefs/shsub8_A88174.d deleted file mode 100644 index 99af65d..0000000 --- a/src/arch/arm/v7/opdefs/shsub8_A88174.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SHSUB8 - -@desc Signed Halving Subtract 8 performs four signed 8-bit integer subtractions, halves the results, and writes the results to the destination register. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 1 1 1 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/smlad_A88177.d b/src/arch/arm/v7/opdefs/smlad_A88177.d deleted file mode 100644 index 3eabaa9..0000000 --- a/src/arch/arm/v7/opdefs/smlad_A88177.d +++ /dev/null @@ -1,76 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SMLAD - -@desc Signed Multiply Accumulate Dual performs two signed 16 × 16-bit multiplications. It adds the products to a 32-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. This instruction sets the Q flag if the accumulate operation overflows. Overflow cannot occur during the multiplications. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 0 0 1 0 Rn(4) Ra(4) Rd(4) 0 0 0 M(1) Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <reg_A> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - m_swap = (M == '1') - - } - - @rules { - - if (m_swap); chk_call ExtendKeyword("x") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 1 0 0 0 0 Rd(4) Ra(4) Rm(4) 0 0 M(1) 1 Rn(4) - - @syntax <reg_D> <reg_N> <reg_M> <reg_A> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - m_swap = (M == '1') - - } - - @rules { - - if (m_swap); chk_call ExtendKeyword("x") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/smlal_A88178.d b/src/arch/arm/v7/opdefs/smlal_A88178.d deleted file mode 100644 index 03da53c..0000000 --- a/src/arch/arm/v7/opdefs/smlal_A88178.d +++ /dev/null @@ -1,69 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SMLAL - -@desc Signed Multiply Accumulate Long multiplies two signed 32-bit values to produce a 64-bit value, and accumulates this with a 64-bit value. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 1 1 0 0 Rn(4) RdLo(4) RdHi(4) 0 0 0 0 Rm(4) - - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 1 1 1 S(1) RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4) - - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/smlald_A88180.d b/src/arch/arm/v7/opdefs/smlald_A88180.d deleted file mode 100644 index fa6a473..0000000 --- a/src/arch/arm/v7/opdefs/smlald_A88180.d +++ /dev/null @@ -1,76 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SMLALD - -@desc Signed Multiply Accumulate Long Dual performs two signed 16 × 16-bit multiplications. It adds the products to a 64-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. Overflow is possible during this instruction, but only as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo 264. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 1 1 0 0 Rn(4) RdLo(4) RdHi(4) 1 1 0 M(1) Rm(4) - - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - m_swap = (M == '1') - - } - - @rules { - - if (m_swap); chk_call ExtendKeyword("x") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 1 0 1 0 0 RdHi(4) RdLo(4) Rm(4) 0 0 M(1) 1 Rn(4) - - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - m_swap = (M == '1') - - } - - @rules { - - if (m_swap); chk_call ExtendKeyword("x") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/smlsd_A88182.d b/src/arch/arm/v7/opdefs/smlsd_A88182.d deleted file mode 100644 index d458fa8..0000000 --- a/src/arch/arm/v7/opdefs/smlsd_A88182.d +++ /dev/null @@ -1,76 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SMLSD - -@desc Signed Multiply Subtract Dual performs two signed 16 × 16-bit multiplications. It adds the difference of the products to a 32-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. This instruction sets the Q flag if the accumulate operation overflows. Overflow cannot occur during the multiplications or subtraction. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 0 1 0 0 Rn(4) Ra(4) Rd(4) 0 0 0 M(1) Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <reg_A> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - m_swap = (M == '1') - - } - - @rules { - - if (m_swap); chk_call ExtendKeyword("x") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 1 0 0 0 0 Rd(4) Ra(4) Rm(4) 0 1 M(1) 1 Rn(4) - - @syntax <reg_D> <reg_N> <reg_M> <reg_A> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - m_swap = (M == '1') - - } - - @rules { - - if (m_swap); chk_call ExtendKeyword("x") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/smlsld_A88183.d b/src/arch/arm/v7/opdefs/smlsld_A88183.d deleted file mode 100644 index 9f64eed..0000000 --- a/src/arch/arm/v7/opdefs/smlsld_A88183.d +++ /dev/null @@ -1,76 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SMLSLD - -@desc Signed Multiply Subtract Long Dual performs two signed 16 × 16-bit multiplications. It adds the difference of the products to a 64-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. Overflow is possible during this instruction, but only as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo 264. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 1 1 0 1 Rn(4) RdLo(4) RdHi(4) 1 1 0 M(1) Rm(4) - - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - m_swap = (M == '1') - - } - - @rules { - - if (m_swap); chk_call ExtendKeyword("x") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 1 0 1 0 0 RdHi(4) RdLo(4) Rm(4) 0 1 M(1) 1 Rn(4) - - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - m_swap = (M == '1') - - } - - @rules { - - if (m_swap); chk_call ExtendKeyword("x") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/smmla_A88184.d b/src/arch/arm/v7/opdefs/smmla_A88184.d deleted file mode 100644 index a4d29b8..0000000 --- a/src/arch/arm/v7/opdefs/smmla_A88184.d +++ /dev/null @@ -1,76 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SMMLA - -@desc Signed Most Significant Word Multiply Accumulate multiplies two signed 32-bit values, extracts the most significant 32 bits of the result, and adds an accumulate value. Optionally, the instruction can specify that the result is rounded instead of being truncated. In this case, the constant 0x80000000 is added to the product before the high word is extracted. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 0 1 0 1 Rn(4) Ra(4) Rd(4) 0 0 0 R(1) Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <reg_A> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - round = (R == '1') - - } - - @rules { - - if (round); chk_call ExtendKeyword("r") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 1 0 1 0 1 Rd(4) Ra(4) Rm(4) 0 0 R(1) 1 Rn(4) - - @syntax <reg_D> <reg_N> <reg_M> <reg_A> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - round = (R == '1') - - } - - @rules { - - if (round); chk_call ExtendKeyword("r") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/smmls_A88185.d b/src/arch/arm/v7/opdefs/smmls_A88185.d deleted file mode 100644 index d59617b..0000000 --- a/src/arch/arm/v7/opdefs/smmls_A88185.d +++ /dev/null @@ -1,76 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SMMLS - -@desc Signed Most Significant Word Multiply Subtract multiplies two signed 32-bit values, subtracts the result from a 32-bit accumulate value that is shifted left by 32 bits, and extracts the most significant 32 bits of the result of that subtraction. Optionally, the instruction can specify that the result of the instruction is rounded instead of being truncated. In this case, the constant 0x80000000 is added to the result of the subtraction before the high word is extracted. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 0 1 1 0 Rn(4) Ra(4) Rd(4) 0 0 0 R(1) Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <reg_A> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - round = (R == '1') - - } - - @rules { - - if (round); chk_call ExtendKeyword("r") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 1 0 1 0 1 Rd(4) Ra(4) Rm(4) 1 1 R(1) 1 Rn(4) - - @syntax <reg_D> <reg_N> <reg_M> <reg_A> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - round = (R == '1') - - } - - @rules { - - if (round); chk_call ExtendKeyword("r") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/smmul_A88186.d b/src/arch/arm/v7/opdefs/smmul_A88186.d deleted file mode 100644 index e02ca52..0000000 --- a/src/arch/arm/v7/opdefs/smmul_A88186.d +++ /dev/null @@ -1,74 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SMMUL - -@desc Signed Most Significant Word Multiply multiplies two signed 32-bit values, extracts the most significant 32 bits of the result, and writes those bits to the destination register. Optionally, the instruction can specify that the result is rounded instead of being truncated. In this case, the constant 0x80000000 is added to the product before the high word is extracted. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 0 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 R(1) Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - round = (R == '1') - - } - - @rules { - - if (round); chk_call ExtendKeyword("r") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 1 0 1 0 1 Rd(4) 1 1 1 1 Rm(4) 0 0 R(1) 1 Rn(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - round = (R == '1') - - } - - @rules { - - if (round); chk_call ExtendKeyword("r") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/smuad_A88187.d b/src/arch/arm/v7/opdefs/smuad_A88187.d deleted file mode 100644 index 324e257..0000000 --- a/src/arch/arm/v7/opdefs/smuad_A88187.d +++ /dev/null @@ -1,74 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SMUAD - -@desc Signed Dual Multiply Add performs two signed 16 × 16-bit multiplications. It adds the products together, and writes the result to the destination register. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. This instruction sets the Q flag if the addition overflows. The multiplications cannot overflow. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 0 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 M(1) Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - m_swap = (M == '1') - - } - - @rules { - - if (m_swap); chk_call ExtendKeyword("x") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 1 0 0 0 0 Rd(4) 1 1 1 1 Rm(4) 0 0 M(1) 1 Rn(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - m_swap = (M == '1') - - } - - @rules { - - if (m_swap); chk_call ExtendKeyword("x") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/smull_A88189.d b/src/arch/arm/v7/opdefs/smull_A88189.d deleted file mode 100644 index 5ab1c54..0000000 --- a/src/arch/arm/v7/opdefs/smull_A88189.d +++ /dev/null @@ -1,69 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SMULL - -@desc Signed Multiply Long multiplies two 32-bit signed values to produce a 64-bit result. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 1 0 0 0 Rn(4) RdLo(4) RdHi(4) 0 0 0 0 Rm(4) - - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 1 1 0 S(1) RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4) - - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/str_A88203.d b/src/arch/arm/v7/opdefs/str_A88203.d deleted file mode 100644 index e3feaf7..0000000 --- a/src/arch/arm/v7/opdefs/str_A88203.d +++ /dev/null @@ -1,98 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title STR (immediate, Thumb) - -@desc Store Register (immediate) calculates an address from a base register value and an immediate offset, and stores a word from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (t1) { - - @half 0 1 1 0 0 imm5(5) Rn(3) Rt(3) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm5:'00', 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) - - } - -} - -@encoding (t2) { - - @half 1 0 0 1 0 Rt(3) imm8(8) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - imm32 = ZeroExtend(imm8:'00', 32) - SP = Register(13) - mem_access = MakeMemoryAccess(SP, imm32, NULL, true, true, false) - - } - -} - -@encoding (T3) { - - @word 1 1 1 1 1 0 0 0 1 1 0 0 Rn(4) Rt(4) imm12(12) - - @syntax ".W" <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) - - } - -} - -@encoding (T4) { - - @word 1 1 1 1 1 0 0 0 0 1 0 0 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - index = (P == '1') - add = (U == '1') - wback = (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/str_A88204.d b/src/arch/arm/v7/opdefs/str_A88204.d deleted file mode 100644 index d780ae3..0000000 --- a/src/arch/arm/v7/opdefs/str_A88204.d +++ /dev/null @@ -1,53 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title STR (immediate, ARM) - -@desc Store Register (immediate) calculates an address from a base register value and an immediate offset, and stores a word from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (A1) { - - @word cond(4) 0 1 0 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) imm12(12) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/str_A88205.d b/src/arch/arm/v7/opdefs/str_A88205.d deleted file mode 100644 index 55f154c..0000000 --- a/src/arch/arm/v7/opdefs/str_A88205.d +++ /dev/null @@ -1,89 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title STR (register) - -@desc Store Register (register) calculates an address from a base register value and an offset register value, stores a word from a register to memory. The offset register value can optionally be shifted. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (t1) { - - @half 0 1 0 1 0 0 0 Rm(3) Rn(3) Rt(3) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, true, false) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 0 0 0 1 0 0 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - - @syntax ".W" <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(0, imm2) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, true, false) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - shift = DecodeImmShift(type, imm5) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, index, add, wback) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/strb_A88206.d b/src/arch/arm/v7/opdefs/strb_A88206.d deleted file mode 100644 index 2caf94c..0000000 --- a/src/arch/arm/v7/opdefs/strb_A88206.d +++ /dev/null @@ -1,81 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title STRB (immediate, Thumb) - -@desc Store Register Byte (immediate) calculates an address from a base register value and an immediate offset, and stores a byte from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (t1) { - - @half 0 1 1 1 0 imm5(5) Rn(3) Rt(3) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm5, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 0 0 1 0 0 0 Rn(4) Rt(4) imm12(12) - - @syntax ".W" <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) - - } - -} - -@encoding (T3) { - - @word 1 1 1 1 1 0 0 0 0 0 0 0 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - index = (P == '1') - add = (U == '1') - wback = (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/strb_A88207.d b/src/arch/arm/v7/opdefs/strb_A88207.d deleted file mode 100644 index 4e893fb..0000000 --- a/src/arch/arm/v7/opdefs/strb_A88207.d +++ /dev/null @@ -1,53 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title STRB (immediate, ARM) - -@desc Store Register Byte (immediate) calculates an address from a base register value and an immediate offset, and stores a byte from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (A1) { - - @word cond(4) 0 1 0 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) imm12(12) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/strb_A88208.d b/src/arch/arm/v7/opdefs/strb_A88208.d deleted file mode 100644 index 36f6134..0000000 --- a/src/arch/arm/v7/opdefs/strb_A88208.d +++ /dev/null @@ -1,89 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title STRB (register) - -@desc Store Register Byte (register) calculates an address from a base register value and an offset register value, and stores a byte from a register to memory. The offset register value can optionally be shifted. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (t1) { - - @half 0 1 0 1 0 1 0 Rm(3) Rn(3) Rt(3) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, true, false) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 0 0 0 0 0 0 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - - @syntax ".W" <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(0, imm2) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, true, false) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - shift = DecodeImmShift(type, imm5) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, index, add, wback) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/strbt_A88209.d b/src/arch/arm/v7/opdefs/strbt_A88209.d deleted file mode 100644 index 2bcb260..0000000 --- a/src/arch/arm/v7/opdefs/strbt_A88209.d +++ /dev/null @@ -1,93 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title STRBT - -@desc Store Register Byte Unprivileged stores a byte from a register to memory. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. STRBT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. - -@encoding (T1) { - - @word 1 1 1 1 1 0 0 0 0 0 0 0 Rn(4) Rt(4) 1 1 1 0 imm8(8) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 0 0 U(1) 1 1 0 Rn(4) Rt(4) imm12(12) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - add = (U == '1') - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - -@encoding (A2) { - - @word cond(4) 0 1 1 0 U(1) 1 1 0 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - add = (U == '1') - shift = DecodeImmShift(type, imm5) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, false, add, false) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/strd_A88210.d b/src/arch/arm/v7/opdefs/strd_A88210.d deleted file mode 100644 index 437bcb3..0000000 --- a/src/arch/arm/v7/opdefs/strd_A88210.d +++ /dev/null @@ -1,75 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title STRD (immediate) - -@desc Store Register Dual (immediate) calculates an address from a base register value and an immediate offset, and stores two words from two registers to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (T1) { - - @word 1 1 1 0 1 0 0 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) Rt2(4) imm8(8) - - @syntax <reg_T> <reg_T2> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - index = (P == '1') - add = (U == '1') - wback = (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) imm4H(4) 1 1 1 1 imm4L(4) - - @syntax <reg_T> <reg_T2> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_T2 = NextRegister(reg_T) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/strd_A88211.d b/src/arch/arm/v7/opdefs/strd_A88211.d deleted file mode 100644 index b30d4a5..0000000 --- a/src/arch/arm/v7/opdefs/strd_A88211.d +++ /dev/null @@ -1,54 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title STRD (register) - -@desc Store Register Dual (register) calculates an address from a base register value and a register offset, and stores two words from two registers to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (A1) { - - @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) 0 0 0 0 1 1 1 1 Rm(4) - - @syntax <reg_T> <reg_T2> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_T2 = NextRegister(reg_T) - reg_N = Register(Rn) - reg_M = Register(Rm) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, index, add, wback) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/strex_A88212.d b/src/arch/arm/v7/opdefs/strex_A88212.d deleted file mode 100644 index 65a7dfe..0000000 --- a/src/arch/arm/v7/opdefs/strex_A88212.d +++ /dev/null @@ -1,68 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title STREX - -@desc Store Register Exclusive calculates an address from a base register value and an immediate offset, and stores a word from a register to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (T1) { - - @word 1 1 1 0 1 0 0 0 0 1 0 0 Rn(4) Rt(4) Rd(4) imm8(8) - - @syntax <reg_D> <reg_T> <mem_access> - - @conv { - - reg_D = Register(Rd) - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, false, false) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 0 0 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rt(4) - - @syntax <reg_D> <reg_T> <mem_access> - - @conv { - - reg_D = Register(Rd) - reg_T = Register(Rt) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/strexb_A88213.d b/src/arch/arm/v7/opdefs/strexb_A88213.d deleted file mode 100644 index 0197d6c..0000000 --- a/src/arch/arm/v7/opdefs/strexb_A88213.d +++ /dev/null @@ -1,67 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title STREXB - -@desc Store Register Exclusive Byte derives an address from a base register value, and stores a byte from a register to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (T1) { - - @word 1 1 1 0 1 0 0 0 1 1 0 0 Rn(4) Rt(4) 1 1 1 1 0 1 0 0 Rd(4) - - @syntax <reg_D> <reg_T> <mem_access> - - @conv { - - reg_D = Register(Rd) - reg_T = Register(Rt) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 1 0 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rt(4) - - @syntax <reg_D> <reg_T> <mem_access> - - @conv { - - reg_D = Register(Rd) - reg_T = Register(Rt) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/strexd_A88214.d b/src/arch/arm/v7/opdefs/strexd_A88214.d deleted file mode 100644 index 2867cea..0000000 --- a/src/arch/arm/v7/opdefs/strexd_A88214.d +++ /dev/null @@ -1,69 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title STREXD - -@desc Store Register Exclusive Doubleword derives an address from a base register value, and stores a 64-bit doubleword from two registers to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (T1) { - - @word 1 1 1 0 1 0 0 0 1 1 0 0 Rn(4) Rt(4) Rt2(4) 0 1 1 1 Rd(4) - - @syntax <reg_D> <reg_T> <reg_T2> <mem_access> - - @conv { - - reg_D = Register(Rd) - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 0 1 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rt(4) - - @syntax <reg_D> <reg_T> <reg_T2> <mem_access> - - @conv { - - reg_D = Register(Rd) - reg_T = Register(Rt) - reg_T2 = NextRegister(reg_T) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/strexh_A88215.d b/src/arch/arm/v7/opdefs/strexh_A88215.d deleted file mode 100644 index 4ca0b6f..0000000 --- a/src/arch/arm/v7/opdefs/strexh_A88215.d +++ /dev/null @@ -1,67 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title STREXH - -@desc Store Register Exclusive Halfword derives an address from a base register value, and stores a halfword from a register to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (T1) { - - @word 1 1 1 0 1 0 0 0 1 1 0 0 Rn(4) Rt(4) 1 1 1 1 0 1 0 1 Rd(4) - - @syntax <reg_D> <reg_T> <mem_access> - - @conv { - - reg_D = Register(Rd) - reg_T = Register(Rt) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 1 1 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rt(4) - - @syntax <reg_D> <reg_T> <mem_access> - - @conv { - - reg_D = Register(Rd) - reg_T = Register(Rt) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/strh_A88216.d b/src/arch/arm/v7/opdefs/strh_A88216.d deleted file mode 100644 index 624b483..0000000 --- a/src/arch/arm/v7/opdefs/strh_A88216.d +++ /dev/null @@ -1,81 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title STRH (immediate, Thumb) - -@desc Store Register Halfword (immediate) calculates an address from a base register value and an immediate offset, and stores a halfword from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (t1) { - - @half 1 0 0 0 0 imm5(5) Rn(3) Rt(3) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm5:'0', 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 0 0 1 0 1 0 Rn(4) Rt(4) imm12(12) - - @syntax ".W" <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) - - } - -} - -@encoding (T3) { - - @word 1 1 1 1 1 0 0 0 0 0 1 0 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - index = (P == '1') - add = (U == '1') - wback = (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/strh_A88217.d b/src/arch/arm/v7/opdefs/strh_A88217.d deleted file mode 100644 index 3b5f97c..0000000 --- a/src/arch/arm/v7/opdefs/strh_A88217.d +++ /dev/null @@ -1,53 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title STRH (immediate, ARM) - -@desc Store Register Halfword (immediate) calculates an address from a base register value and an immediate offset, and stores a halfword from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (A1) { - - @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) imm4H(4) 1 0 1 1 imm4L(4) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/strh_A88218.d b/src/arch/arm/v7/opdefs/strh_A88218.d deleted file mode 100644 index 1e9dc1f..0000000 --- a/src/arch/arm/v7/opdefs/strh_A88218.d +++ /dev/null @@ -1,88 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title STRH (register) - -@desc Store Register Halfword (register) calculates an address from a base register value and an offset register value, and stores a halfword from a register to memory. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294. - -@encoding (t1) { - - @half 0 1 0 1 0 0 1 Rm(3) Rn(3) Rt(3) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, true, false) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 0 0 0 0 1 0 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - - @syntax ".W" <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(0, imm2) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, true, false) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) 0 0 0 0 1 0 1 1 Rm(4) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, index, add, wback) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/strht_A88219.d b/src/arch/arm/v7/opdefs/strht_A88219.d deleted file mode 100644 index 3811572..0000000 --- a/src/arch/arm/v7/opdefs/strht_A88219.d +++ /dev/null @@ -1,92 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title STRHT - -@desc Store Register Halfword Unprivileged stores a halfword from a register to memory. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. STRHT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value. - -@encoding (T1) { - - @word 1 1 1 1 1 0 0 0 0 0 1 0 Rn(4) Rt(4) 1 1 1 0 imm8(8) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 U(1) 1 1 0 Rn(4) Rt(4) imm4H(4) 1 0 1 1 imm4L(4) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - add = (U == '1') - imm32 = ZeroExtend(imm4H:imm4L, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - -@encoding (A2) { - - @word cond(4) 0 0 0 0 U(1) 0 1 0 Rn(4) Rt(4) 0 0 0 0 1 0 1 1 Rm(4) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - add = (U == '1') - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, false, add, false) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/strt_A88220.d b/src/arch/arm/v7/opdefs/strt_A88220.d deleted file mode 100644 index 794a0fa..0000000 --- a/src/arch/arm/v7/opdefs/strt_A88220.d +++ /dev/null @@ -1,93 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title STRT - -@desc Store Register Unprivileged stores a word from a register to memory. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. STRT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. - -@encoding (T1) { - - @word 1 1 1 1 1 0 0 0 0 1 0 0 Rn(4) Rt(4) 1 1 1 0 imm8(8) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 0 0 U(1) 0 1 0 Rn(4) Rt(4) imm12(12) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - add = (U == '1') - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - -@encoding (A2) { - - @word cond(4) 0 1 1 0 U(1) 0 1 0 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - - @syntax <reg_T> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - add = (U == '1') - shift = DecodeImmShift(type, imm5) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, false, add, false) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/sub_A88221.d b/src/arch/arm/v7/opdefs/sub_A88221.d deleted file mode 100644 index 41ce6b3..0000000 --- a/src/arch/arm/v7/opdefs/sub_A88221.d +++ /dev/null @@ -1,98 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SUB (immediate, Thumb) - -@desc This instruction subtracts an immediate value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -@encoding (t1) { - - @half 0 0 0 1 1 1 1 imm3(3) Rn(3) Rd(3) - - @syntax "subs" <reg_D> <reg_N> <imm32> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm3, 32) - - } - -} - -@encoding (t2) { - - @half 0 0 1 1 1 Rdn(3) imm8(8) - - @syntax "subs" <reg_DN> <imm32> - - @conv { - - reg_DN = Register(Rdn) - imm32 = ZeroExtend(imm8, 32) - - } - -} - -@encoding (T3) { - - @word 1 1 1 1 0 i(1) 0 1 1 0 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - - @syntax <reg_D> <reg_N> <imm32> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ThumbExpandImm(i:imm3:imm8) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") - - } - -} - -@encoding (T4) { - - @word 1 1 1 1 0 i(1) 1 0 1 0 1 0 Rn(4) 0 imm3(3) Rd(4) imm8(8) - - @syntax "subw" <reg_D> <reg_N> <imm32> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ZeroExtend(i:imm3:imm8, 32) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/sub_A88222.d b/src/arch/arm/v7/opdefs/sub_A88222.d deleted file mode 100644 index ef326b8..0000000 --- a/src/arch/arm/v7/opdefs/sub_A88222.d +++ /dev/null @@ -1,51 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SUB (immediate, ARM) - -@desc This instruction subtracts an immediate value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -@encoding (A1) { - - @word cond(4) 0 0 1 0 0 1 0 S(1) Rn(4) Rd(4) imm12(12) - - @syntax <reg_D> <reg_N> <imm32> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ARMExpandImm(imm12) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/sub_A88223.d b/src/arch/arm/v7/opdefs/sub_A88223.d deleted file mode 100644 index a629250..0000000 --- a/src/arch/arm/v7/opdefs/sub_A88223.d +++ /dev/null @@ -1,93 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SUB (register) - -@desc This instruction subtracts an optionally-shifted register value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -@encoding (t1) { - - @half 0 0 0 1 1 0 1 Rm(3) Rn(3) Rd(3) - - @syntax "subs" <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (T2) { - - @word 1 1 1 0 1 0 1 1 1 0 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <?shift> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 0 1 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <?shift> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/sub_A88224.d b/src/arch/arm/v7/opdefs/sub_A88224.d deleted file mode 100644 index 5ef4e4d..0000000 --- a/src/arch/arm/v7/opdefs/sub_A88224.d +++ /dev/null @@ -1,52 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SUB (register-shifted register) - -@desc This instruction subtracts a register-shifted register value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -@encoding (A1) { - - @word cond(4) 0 0 0 0 0 1 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <reg_shift> - - @conv { - - reg_shift = RegisterShift(type, Rs) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/sub_A88225.d b/src/arch/arm/v7/opdefs/sub_A88225.d deleted file mode 100644 index dc54c6b..0000000 --- a/src/arch/arm/v7/opdefs/sub_A88225.d +++ /dev/null @@ -1,107 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SUB (SP minus immediate) - -@desc This instruction subtracts an immediate value from the SP value, and writes the result to the destination register. - -@encoding (t1) { - - @half 1 0 1 1 0 0 0 0 1 imm7(7) - - @syntax <SP_0> <SP_1> <imm32> - - @conv { - - imm32 = ZeroExtend(imm7:'00', 32) - SP_0 = Register(13) - SP_1 = Register(13) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 0 i(1) 0 1 1 0 1 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm8(8) - - @syntax <reg_D> <SP> <imm32> - - @conv { - - reg_D = Register(Rd) - setflags = (S == '1') - imm32 = ThumbExpandImm(i:imm3:imm8) - SP = Register(13) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") - - } - -} - -@encoding (T3) { - - @word 1 1 1 1 0 i(1) 1 0 1 0 1 0 1 1 0 1 0 imm3(3) Rd(4) imm8(8) - - @syntax "subw" <reg_D> <SP> <imm32> - - @conv { - - reg_D = Register(Rd) - imm32 = ZeroExtend(i:imm3:imm8, 32) - SP = Register(13) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 0 0 1 0 S(1) 1 1 0 1 Rd(4) imm12(12) - - @syntax <reg_D> <SP> <imm32> - - @conv { - - reg_D = Register(Rd) - setflags = (S == '1') - imm32 = ARMExpandImm(imm12) - SP = Register(13) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/sub_A88226.d b/src/arch/arm/v7/opdefs/sub_A88226.d deleted file mode 100644 index 02ecada..0000000 --- a/src/arch/arm/v7/opdefs/sub_A88226.d +++ /dev/null @@ -1,76 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SUB (SP minus register) - -@desc This instruction subtracts an optionally-shifted register value from the SP value, and writes the result to the destination register. - -@encoding (T1) { - - @word 1 1 1 0 1 0 1 1 1 0 1 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - - @syntax <reg_D> <SP> <reg_M> <?shift> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) - SP = Register(13) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 0 1 0 S(1) 1 1 0 1 Rd(4) imm5(5) type(2) 0 Rm(4) - - @syntax <reg_D> <SP> <reg_M> <?shift> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) - SP = Register(13) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/subs_B9320.d b/src/arch/arm/v7/opdefs/subs_B9320.d deleted file mode 100644 index 335e614..0000000 --- a/src/arch/arm/v7/opdefs/subs_B9320.d +++ /dev/null @@ -1,44 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2014 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SUBS PC, LR and related instructions (ARM) - -@encoding(A1) { - - @word cond(4) 0 0 1 opcode(4) 1 Rn(4) 1 1 1 1 imm12(12) - - @syntax {c} <Rn> <#const> - - @conv { - - c = Condition(cond) - Rn = Register(Rn) - const = ExpandImmC32(imm12) - - } - - @rules { - - } - -} diff --git a/src/arch/arm/v7/opdefs/svc_A88228.d b/src/arch/arm/v7/opdefs/svc_A88228.d deleted file mode 100644 index be48545..0000000 --- a/src/arch/arm/v7/opdefs/svc_A88228.d +++ /dev/null @@ -1,61 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SVC (previously SWI) - -@desc Supervisor Call, previously called Software Interrupt, causes a Supervisor Call exception. For more information, see Supervisor Call (SVC) exception on page B1-1209. Software can use this instruction as a call to an operating system to provide a service. In the following cases, the Supervisor Call exception generated by the SVC instruction is taken to Hyp mode: • If the SVC is executed in Hyp mode. • If HCR.TGE is set to 1, and the SVC is executed in Non-secure User mode. For more information, see Supervisor Call exception, when HCR.TGE is set to 1 on page B1-1191 In these cases, the HSR identifies that the exception entry was caused by a Supervisor Call exception, EC value 0x11, see Use of the HSR on page B3-1424. The immediate field in the HSR: • if the SVC is unconditional: — for the Thumb instruction, is the zero-extended value of the imm8 field — for the ARM instruction, is the least-significant 16 bits the imm24 field • if the SVC is conditional, is UNKNOWN. - -@encoding (t1) { - - @half 1 1 0 1 1 1 1 1 imm8(8) - - @syntax <imm32> - - @conv { - - imm32 = ZeroExtend(imm8, 32) - - } - -} - -@encoding (A1) { - - @word cond(4) 1 1 1 1 imm24(24) - - @syntax <imm32> - - @conv { - - imm32 = ZeroExtend(imm24, 32) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/swp_A88229.d b/src/arch/arm/v7/opdefs/swp_A88229.d deleted file mode 100644 index 2e39015..0000000 --- a/src/arch/arm/v7/opdefs/swp_A88229.d +++ /dev/null @@ -1,52 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SWP, SWPB - -@desc SWP (Swap) swaps a word between registers and memory. SWP loads a word from the memory address given by the value of register <Rn>. The value of register <Rt2> is then stored to the memory address given by the value of <Rn>, and the original loaded value is written to register <Rt>. If the same register is specified for <Rt> and <Rt2>, this instruction swaps the value of the register and the value at the memory address. SWPB (Swap Byte) swaps a byte between registers and memory. SWPB loads a byte from the memory address given by the value of register <Rn>. The value of the least significant byte of register <Rt2> is stored to the memory address given by <Rn>, the original loaded value is zero-extended to a 32-bit word, and the word is written to register <Rt>. If the same register is specified for <Rt> and <Rt2>, this instruction swaps the value of the least significant byte of the register and the byte value at the memory address, and clears the most significant three bytes of the register. For both instructions, the memory system ensures that no other memory access can occur to the memory location between the load access and the store access. Note • The SWP and SWPB instructions rely on the properties of the system beyond the processor to ensure that no stores from other observers can occur between the load access and the store access, and this might not be implemented for all regions of memory on some system implementations. In all cases, SWP and SWPB do ensure that no stores from the processor that executed the SWP or SWPB instruction can occur between the load access and the store access of the SWP or SWPB. • ARM deprecates the use of SWP and SWPB, and strongly recommends that new software uses: LDREX/STREX in preference to SWP — LDREXB/STREXB in preference to SWPB. — • If the translation table entries that relate to a memory location accessed by the SWP or SWPB instruction change, or are seen to change by the executing processor as a result of TLB eviction, this might mean that the translation table attributes, permissions or addresses for the load are different to those for the store. In this case, the architecture makes no guarantee that no memory access occur to these memory locations between the load and store. The Virtualization Extensions make the SWP and SWPB instructions OPTIONAL and deprecated: • If an implementation does not include the SWP and SWPB instructions, the ID_ISAR0.Swap_instrs and ID_ISAR4.SWP_frac fields are zero, see About the Instruction Set Attribute registers on page B7-1950. • In an implementation that includes SWP and SWPB, both instructions are UNDEFINED in Hyp mode. - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 B(1) 0 0 Rn(4) Rt(4) 0 0 0 0 1 0 0 1 Rt2(4) - - @syntax <reg_T> <reg_T2> <mem_access> - - @conv { - - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - reg_N = Register(Rn) - size = (B != 4) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) - - } - - @rules { - - if (size); chk_call ExtendKeyword("b") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/teq_A88237.d b/src/arch/arm/v7/opdefs/teq_A88237.d deleted file mode 100644 index 89073f6..0000000 --- a/src/arch/arm/v7/opdefs/teq_A88237.d +++ /dev/null @@ -1,63 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title TEQ (immediate) - -@desc Test Equivalence (immediate) performs a bitwise exclusive OR operation on a register value and an immediate value. It updates the condition flags based on the result, and discards the result. - -@encoding (T1) { - - @word 1 1 1 1 0 i(1) 0 0 1 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm8(8) - - @syntax <reg_N> <imm32> - - @conv { - - reg_N = Register(Rn) - imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 1 0 0 1 1 Rn(4) 0 0 0 0 imm12(12) - - @syntax <reg_N> <imm32> - - @conv { - - reg_N = Register(Rn) - imm32 = ARMExpandImm_C(imm12, 0) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/teq_A88238.d b/src/arch/arm/v7/opdefs/teq_A88238.d deleted file mode 100644 index 8187d81..0000000 --- a/src/arch/arm/v7/opdefs/teq_A88238.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title TEQ (register) - -@desc Test Equivalence (register) performs a bitwise exclusive OR operation on a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result. - -@encoding (T1) { - - @word 1 1 1 0 1 0 1 0 1 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm2(2) type(2) Rm(4) - - @syntax <reg_N> <reg_M> <?shift> - - @conv { - - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 0 1 1 Rn(4) 0 0 0 0 imm5(5) type(2) 0 Rm(4) - - @syntax <reg_N> <reg_M> <?shift> - - @conv { - - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/teq_A88239.d b/src/arch/arm/v7/opdefs/teq_A88239.d deleted file mode 100644 index 986a7f0..0000000 --- a/src/arch/arm/v7/opdefs/teq_A88239.d +++ /dev/null @@ -1,49 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title TEQ (register-shifted register) - -@desc Test Equivalence (register-shifted register) performs a bitwise exclusive OR operation on a register value and a register-shifted register value. It updates the condition flags based on the result, and discards the result. - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 0 1 1 Rn(4) 0 0 0 0 Rs(4) 0 type(2) 1 Rm(4) - - @syntax <reg_N> <reg_M> <reg_shift> - - @conv { - - reg_shift = RegisterShift(type, Rs) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/tst_A88240.d b/src/arch/arm/v7/opdefs/tst_A88240.d deleted file mode 100644 index 0ff5121..0000000 --- a/src/arch/arm/v7/opdefs/tst_A88240.d +++ /dev/null @@ -1,63 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title TST (immediate) - -@desc Test (immediate) performs a bitwise AND operation on a register value and an immediate value. It updates the condition flags based on the result, and discards the result. - -@encoding (T1) { - - @word 1 1 1 1 0 i(1) 0 0 0 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm8(8) - - @syntax <reg_N> <imm32> - - @conv { - - reg_N = Register(Rn) - imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 1 0 0 0 1 Rn(4) 0 0 0 0 imm12(12) - - @syntax <reg_N> <imm32> - - @conv { - - reg_N = Register(Rn) - imm32 = ARMExpandImm_C(imm12, 0) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/tst_A88241.d b/src/arch/arm/v7/opdefs/tst_A88241.d deleted file mode 100644 index 8777d06..0000000 --- a/src/arch/arm/v7/opdefs/tst_A88241.d +++ /dev/null @@ -1,80 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title TST (register) - -@desc Test (register) performs a bitwise AND operation on a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result. - -@encoding (t1) { - - @half 0 1 0 0 0 0 1 0 0 0 Rm(3) Rn(3) - - @syntax <reg_N> <reg_M> - - @conv { - - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (T2) { - - @word 1 1 1 0 1 0 1 0 0 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm2(2) type(2) Rm(4) - - @syntax ".W" <reg_N> <reg_M> <?shift> - - @conv { - - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 0 0 1 Rn(4) 0 0 0 0 imm5(5) type(2) 0 Rm(4) - - @syntax <reg_N> <reg_M> <?shift> - - @conv { - - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/tst_A88242.d b/src/arch/arm/v7/opdefs/tst_A88242.d deleted file mode 100644 index d3fdd9c..0000000 --- a/src/arch/arm/v7/opdefs/tst_A88242.d +++ /dev/null @@ -1,49 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title TST (register-shifted register) - -@desc Test (register-shifted register) performs a bitwise AND operation on a register value and a register-shifted register value. It updates the condition flags based on the result, and discards the result. - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 0 0 1 Rn(4) 0 0 0 0 Rs(4) 0 type(2) 1 Rm(4) - - @syntax <reg_N> <reg_M> <reg_shift> - - @conv { - - reg_shift = RegisterShift(type, Rs) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/uadd16_A88243.d b/src/arch/arm/v7/opdefs/uadd16_A88243.d deleted file mode 100644 index fcaadee..0000000 --- a/src/arch/arm/v7/opdefs/uadd16_A88243.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title UADD16 - -@desc Unsigned Add 16 performs two 16-bit unsigned integer additions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the additions. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/uadd8_A88244.d b/src/arch/arm/v7/opdefs/uadd8_A88244.d deleted file mode 100644 index 451ca79..0000000 --- a/src/arch/arm/v7/opdefs/uadd8_A88244.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title UADD8 - -@desc Unsigned Add 8 performs four unsigned 8-bit integer additions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the additions. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/uasx_A88245.d b/src/arch/arm/v7/opdefs/uasx_A88245.d deleted file mode 100644 index f968527..0000000 --- a/src/arch/arm/v7/opdefs/uasx_A88245.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title UASX - -@desc Unsigned Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, and writes the results to the destination register. It sets the APSR.GE bits according to the results. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/ubfx_A88246.d b/src/arch/arm/v7/opdefs/ubfx_A88246.d deleted file mode 100644 index 1f9488e..0000000 --- a/src/arch/arm/v7/opdefs/ubfx_A88246.d +++ /dev/null @@ -1,67 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title UBFX - -@desc Unsigned Bit Field Extract extracts any number of adjacent bits at any position from a register, zero-extends them to 32 bits, and writes the result to the destination register. - -@encoding (T1) { - - @word 1 1 1 1 0 0 1 1 1 1 0 0 Rn(4) 0 imm3(3) Rd(4) imm2(2) 0 widthm1(5) - - @syntax <reg_D> <reg_N> <lsbit> <width> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - lsbit = UInt(imm3:imm2) - width = IncWidth(widthm1) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 1 1 1 1 widthm1(5) Rd(4) lsb(5) 1 0 1 Rn(4) - - @syntax <reg_D> <reg_N> <lsbit> <width> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - lsbit = UInt(lsb) - width = IncWidth(widthm1) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/udf_A88247.d b/src/arch/arm/v7/opdefs/udf_A88247.d deleted file mode 100644 index 38f818c..0000000 --- a/src/arch/arm/v7/opdefs/udf_A88247.d +++ /dev/null @@ -1,69 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title UDF - -@desc Permanently Undefined generates an Undefined Instruction exception. The encodings for UDF used in this section are defined as permanently UNDEFINED in the versions of the architecture specified in this section. Issue C.a of this manual first defines an assembler mnemonic for these encodings. However: • with the Thumb instruction set, ARM deprecates using the UDF instruction in an IT block • in the ARM instruction set, UDF is not conditional. - -@encoding (t1) { - - @half 1 1 0 1 1 1 1 0 imm8(8) - - @syntax <imm32> - - @conv { - - imm32 = ZeroExtend(imm8, 32) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 0 1 1 1 1 1 1 1 imm4(4) 1 0 1 0 imm12(12) - - @syntax ".W" <imm32> - - @conv { - - imm32 = ZeroExtend(imm4:imm12, 32) - - } - -} - -@encoding (A1) { - - @word 1 1 1 0 0 1 1 1 1 1 1 1 imm12(12) 1 1 1 1 imm4(4) - - @syntax <imm32> - - @conv { - - imm32 = ZeroExtend(imm12:imm4, 32) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/udiv_A88248.d b/src/arch/arm/v7/opdefs/udiv_A88248.d deleted file mode 100644 index eea7947..0000000 --- a/src/arch/arm/v7/opdefs/udiv_A88248.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title UDIV - -@desc Unsigned Divide divides a 32-bit unsigned integer register value by a 32-bit unsigned integer register value, and writes the result to the destination register. The condition flags are not affected. See ARMv7 implementation requirements and options for the divide instructions on page A4-172 for more information about this instruction. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 1 0 1 1 Rn(4) 1 1 1 1 Rd(4) 1 1 1 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 1 0 0 1 1 Rd(4) 1 1 1 1 Rm(4) 0 0 0 1 Rn(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/uhadd16_A88249.d b/src/arch/arm/v7/opdefs/uhadd16_A88249.d deleted file mode 100644 index 54da5b0..0000000 --- a/src/arch/arm/v7/opdefs/uhadd16_A88249.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title UHADD16 - -@desc Unsigned Halving Add 16 performs two unsigned 16-bit integer additions, halves the results, and writes the results to the destination register. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/uhadd8_A88250.d b/src/arch/arm/v7/opdefs/uhadd8_A88250.d deleted file mode 100644 index 759a0a7..0000000 --- a/src/arch/arm/v7/opdefs/uhadd8_A88250.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title UHADD8 - -@desc Unsigned Halving Add 8 performs four unsigned 8-bit integer additions, halves the results, and writes the results to the destination register. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/uhasx_A88251.d b/src/arch/arm/v7/opdefs/uhasx_A88251.d deleted file mode 100644 index 3751394..0000000 --- a/src/arch/arm/v7/opdefs/uhasx_A88251.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title UHASX - -@desc Unsigned Halving Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, halves the results, and writes the results to the destination register. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/uhsax_A88252.d b/src/arch/arm/v7/opdefs/uhsax_A88252.d deleted file mode 100644 index f06b2ba..0000000 --- a/src/arch/arm/v7/opdefs/uhsax_A88252.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title UHSAX - -@desc Unsigned Halving Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, halves the results, and writes the results to the destination register. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/uhsub16_A88253.d b/src/arch/arm/v7/opdefs/uhsub16_A88253.d deleted file mode 100644 index 93f92f7..0000000 --- a/src/arch/arm/v7/opdefs/uhsub16_A88253.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title UHSUB16 - -@desc Unsigned Halving Subtract 16 performs two unsigned 16-bit integer subtractions, halves the results, and writes the results to the destination register. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 0 1 1 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/uhsub8_A88254.d b/src/arch/arm/v7/opdefs/uhsub8_A88254.d deleted file mode 100644 index 198a095..0000000 --- a/src/arch/arm/v7/opdefs/uhsub8_A88254.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title UHSUB8 - -@desc Unsigned Halving Subtract 8 performs four unsigned 8-bit integer subtractions, halves the results, and writes the results to the destination register. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 1 1 1 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/umaal_A88255.d b/src/arch/arm/v7/opdefs/umaal_A88255.d deleted file mode 100644 index 34cb707..0000000 --- a/src/arch/arm/v7/opdefs/umaal_A88255.d +++ /dev/null @@ -1,67 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title UMAAL - -@desc Unsigned Multiply Accumulate Accumulate Long multiplies two unsigned 32-bit values to produce a 64-bit value, adds two unsigned 32-bit values, and writes the 64-bit result to two registers. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 1 1 1 0 Rn(4) RdLo(4) RdHi(4) 0 1 1 0 Rm(4) - - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 0 1 0 0 RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4) - - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/umlal_A88256.d b/src/arch/arm/v7/opdefs/umlal_A88256.d deleted file mode 100644 index 00d1903..0000000 --- a/src/arch/arm/v7/opdefs/umlal_A88256.d +++ /dev/null @@ -1,69 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title UMLAL - -@desc Unsigned Multiply Accumulate Long multiplies two unsigned 32-bit values to produce a 64-bit value, and accumulates this with a 64-bit value. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 1 1 1 0 Rn(4) RdLo(4) RdHi(4) 0 0 0 0 Rm(4) - - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 1 0 1 S(1) RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4) - - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/umull_A88257.d b/src/arch/arm/v7/opdefs/umull_A88257.d deleted file mode 100644 index d2cc321..0000000 --- a/src/arch/arm/v7/opdefs/umull_A88257.d +++ /dev/null @@ -1,69 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title UMULL - -@desc Unsigned Multiply Long multiplies two 32-bit unsigned values to produce a 64-bit result. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 1 0 1 0 Rn(4) RdLo(4) RdHi(4) 0 0 0 0 Rm(4) - - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 1 0 0 S(1) RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4) - - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/uqadd16_A88258.d b/src/arch/arm/v7/opdefs/uqadd16_A88258.d deleted file mode 100644 index 14528c8..0000000 --- a/src/arch/arm/v7/opdefs/uqadd16_A88258.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title UQADD16 - -@desc Unsigned Saturating Add 16 performs two unsigned 16-bit integer additions, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/uqadd8_A88259.d b/src/arch/arm/v7/opdefs/uqadd8_A88259.d deleted file mode 100644 index 94b8e39..0000000 --- a/src/arch/arm/v7/opdefs/uqadd8_A88259.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title UQADD8 - -@desc Unsigned Saturating Add 8 performs four unsigned 8-bit integer additions, saturates the results to the 8-bit unsigned integer range 0 ≤ x ≤ 28 – 1, and writes the results to the destination register. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/uqasx_A88260.d b/src/arch/arm/v7/opdefs/uqasx_A88260.d deleted file mode 100644 index 174b08c..0000000 --- a/src/arch/arm/v7/opdefs/uqasx_A88260.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title UQASX - -@desc Unsigned Saturating Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/uqsax_A88261.d b/src/arch/arm/v7/opdefs/uqsax_A88261.d deleted file mode 100644 index 6092e51..0000000 --- a/src/arch/arm/v7/opdefs/uqsax_A88261.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title UQSAX - -@desc Unsigned Saturating Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/uqsub16_A88262.d b/src/arch/arm/v7/opdefs/uqsub16_A88262.d deleted file mode 100644 index 1f458ff..0000000 --- a/src/arch/arm/v7/opdefs/uqsub16_A88262.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title UQSUB16 - -@desc Unsigned Saturating Subtract 16 performs two unsigned 16-bit integer subtractions, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 0 1 1 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/uqsub8_A88263.d b/src/arch/arm/v7/opdefs/uqsub8_A88263.d deleted file mode 100644 index 37d96e7..0000000 --- a/src/arch/arm/v7/opdefs/uqsub8_A88263.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title UQSUB8 - -@desc Unsigned Saturating Subtract 8 performs four unsigned 8-bit integer subtractions, saturates the results to the 8-bit unsigned integer range 0 ≤ x ≤ 28 – 1, and writes the results to the destination register. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 1 1 1 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/usad8_A88264.d b/src/arch/arm/v7/opdefs/usad8_A88264.d deleted file mode 100644 index 09d7ece..0000000 --- a/src/arch/arm/v7/opdefs/usad8_A88264.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title USAD8 - -@desc Unsigned Sum of Absolute Differences performs four unsigned 8-bit subtractions, and adds the absolute values of the differences together. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 0 1 1 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 1 1 0 0 0 Rd(4) 1 1 1 1 Rm(4) 0 0 0 1 Rn(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/usada8_A88265.d b/src/arch/arm/v7/opdefs/usada8_A88265.d deleted file mode 100644 index dd1efdb..0000000 --- a/src/arch/arm/v7/opdefs/usada8_A88265.d +++ /dev/null @@ -1,67 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title USADA8 - -@desc Unsigned Sum of Absolute Differences and Accumulate performs four unsigned 8-bit subtractions, and adds the absolute values of the differences to a 32-bit accumulate operand. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 0 1 1 1 Rn(4) Ra(4) Rd(4) 0 0 0 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <reg_A> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 1 1 0 0 0 Rd(4) Ra(4) Rm(4) 0 0 0 1 Rn(4) - - @syntax <reg_D> <reg_N> <reg_M> <reg_A> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/usat16_A88267.d b/src/arch/arm/v7/opdefs/usat16_A88267.d deleted file mode 100644 index c091dc6..0000000 --- a/src/arch/arm/v7/opdefs/usat16_A88267.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title USAT16 - -@desc Unsigned Saturate 16 saturates two signed 16-bit values to a selected unsigned range. The Q flag is set if the operation saturates. - -@encoding (T1) { - - @word 1 1 1 1 0 0 1 1 1 0 1 0 Rn(4) 0 0 0 0 Rd(4) 0 0 0 0 sat_imm(4) - - @syntax <reg_D> <saturate_to> <reg_N> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - saturate_to = UInt(sat_imm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 1 1 0 sat_imm(4) Rd(4) 1 1 1 1 0 0 1 1 Rn(4) - - @syntax <reg_D> <saturate_to> <reg_N> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - saturate_to = UInt(sat_imm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/usat_A88266.d b/src/arch/arm/v7/opdefs/usat_A88266.d deleted file mode 100644 index 55de21a..0000000 --- a/src/arch/arm/v7/opdefs/usat_A88266.d +++ /dev/null @@ -1,67 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title USAT - -@desc Unsigned Saturate saturates an optionally-shifted signed value to a selected unsigned range. The Q flag is set if the operation saturates. - -@encoding (T1) { - - @word 1 1 1 1 0 0 1 1 1 0 sh(1) 0 Rn(4) 0 imm3(3) Rd(4) imm2(2) 0 sat_imm(5) - - @syntax <reg_D> <saturate_to> <reg_N> <?shift> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - saturate_to = UInt(sat_imm) - shift = DecodeImmShift(sh:'0', imm3:imm2) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 1 1 sat_imm(5) Rd(4) imm5(5) sh(1) 0 1 Rn(4) - - @syntax <reg_D> <saturate_to> <reg_N> <?shift> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - saturate_to = UInt(sat_imm) - shift = DecodeImmShift(sh:'0', imm5) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/usax_A88268.d b/src/arch/arm/v7/opdefs/usax_A88268.d deleted file mode 100644 index 040eedc..0000000 --- a/src/arch/arm/v7/opdefs/usax_A88268.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title USAX - -@desc Unsigned Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, and writes the results to the destination register. It sets the APSR.GE bits according to the results. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/usub16_A88269.d b/src/arch/arm/v7/opdefs/usub16_A88269.d deleted file mode 100644 index 31796d9..0000000 --- a/src/arch/arm/v7/opdefs/usub16_A88269.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title USUB16 - -@desc Unsigned Subtract 16 performs two 16-bit unsigned integer subtractions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the subtractions. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 0 1 1 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/usub8_A88270.d b/src/arch/arm/v7/opdefs/usub8_A88270.d deleted file mode 100644 index 576894c..0000000 --- a/src/arch/arm/v7/opdefs/usub8_A88270.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title USUB8 - -@desc Unsigned Subtract 8 performs four 8-bit unsigned integer subtractions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the subtractions. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 1 1 1 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/uxtab16_A88272.d b/src/arch/arm/v7/opdefs/uxtab16_A88272.d deleted file mode 100644 index 4fc61d2..0000000 --- a/src/arch/arm/v7/opdefs/uxtab16_A88272.d +++ /dev/null @@ -1,67 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title UXTAB16 - -@desc Unsigned Extend and Add Byte 16 extracts two 8-bit values from a register, zero-extends them to 16 bits each, adds the results to two 16-bit values from another register, and writes the final results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 0 0 1 1 Rn(4) 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <?rotation> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 1 0 0 Rn(4) Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <?rotation> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/uxtab_A88271.d b/src/arch/arm/v7/opdefs/uxtab_A88271.d deleted file mode 100644 index fe27d4b..0000000 --- a/src/arch/arm/v7/opdefs/uxtab_A88271.d +++ /dev/null @@ -1,67 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title UXTAB - -@desc Unsigned Extend and Add Byte extracts an 8-bit value from a register, zero-extends it to 32 bits, adds the result to the value in another register, and writes the final result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 0 1 0 1 Rn(4) 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <?rotation> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 1 1 0 Rn(4) Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <?rotation> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/uxtah_A88273.d b/src/arch/arm/v7/opdefs/uxtah_A88273.d deleted file mode 100644 index 3c587d9..0000000 --- a/src/arch/arm/v7/opdefs/uxtah_A88273.d +++ /dev/null @@ -1,67 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title UXTAH - -@desc Unsigned Extend and Add Halfword extracts a 16-bit value from a register, zero-extends it to 32 bits, adds the result to a value from another register, and writes the final result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 0 0 0 1 Rn(4) 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <?rotation> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 1 1 1 Rn(4) Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <?rotation> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/uxtb16_A88275.d b/src/arch/arm/v7/opdefs/uxtb16_A88275.d deleted file mode 100644 index a30d133..0000000 --- a/src/arch/arm/v7/opdefs/uxtb16_A88275.d +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title UXTB16 - -@desc Unsigned Extend Byte 16 extracts two 8-bit values from a register, zero-extends them to 16 bits each, and writes the results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) - - @syntax <reg_D> <reg_M> <?rotation> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 1 0 0 1 1 1 1 Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) - - @syntax <reg_D> <reg_M> <?rotation> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/uxtb_A88274.d b/src/arch/arm/v7/opdefs/uxtb_A88274.d deleted file mode 100644 index f49ba83..0000000 --- a/src/arch/arm/v7/opdefs/uxtb_A88274.d +++ /dev/null @@ -1,80 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title UXTB - -@desc Unsigned Extend Byte extracts an 8-bit value from a register, zero-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value. - -@encoding (t1) { - - @half 1 0 1 1 0 0 1 0 1 1 Rm(3) Rd(3) - - @syntax <reg_D> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) - - @syntax ".W" <reg_D> <reg_M> <?rotation> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 1 1 0 1 1 1 1 Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) - - @syntax <reg_D> <reg_M> <?rotation> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/uxth_A88276.d b/src/arch/arm/v7/opdefs/uxth_A88276.d deleted file mode 100644 index 5ae4f4f..0000000 --- a/src/arch/arm/v7/opdefs/uxth_A88276.d +++ /dev/null @@ -1,80 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title UXTH - -@desc Unsigned Extend Halfword extracts a 16-bit value from a register, zero-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value. - -@encoding (t1) { - - @half 1 0 1 1 0 0 1 0 1 0 Rm(3) Rd(3) - - @syntax <reg_D> <reg_M> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) - - @syntax ".W" <reg_D> <reg_M> <?rotation> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 1 1 1 1 1 1 1 Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) - - @syntax <reg_D> <reg_M> <?rotation> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/wfi_A88425.d b/src/arch/arm/v7/opdefs/wfi_A88425.d deleted file mode 100644 index f11d033..0000000 --- a/src/arch/arm/v7/opdefs/wfi_A88425.d +++ /dev/null @@ -1,53 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title WFI - -@desc Wait For Interrupt is a hint instruction that permits the processor to enter a low-power state until one of a number of asynchronous events occurs. For more information, see Wait For Interrupt on page B1-1202. In an implementation that includes the Virtualization Extensions, if HCR.TWI is set to 1, execution of a WFI instruction in a Non-secure mode other than Hyp mode generates a Hyp Trap exception if, ignoring the value of the HCR.TWI bit, conditions permit the processor to suspend execution. For more information see Trapping use of the WFI and WFE instructions on page B1-1255. - -@encoding (t1) { - - @half 1 0 1 1 1 1 1 1 0 0 1 1 0 0 0 0 - -} - -@encoding (T2) { - - @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 - - @syntax ".W" - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/opdefs/yield_A88426.d b/src/arch/arm/v7/opdefs/yield_A88426.d deleted file mode 100644 index 252c018..0000000 --- a/src/arch/arm/v7/opdefs/yield_A88426.d +++ /dev/null @@ -1,53 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title YIELD - -@desc YIELD is a hint instruction. Software with a multithreading capability can use a YIELD instruction to indicate to the hardware that it is performing a task, for example a spin-lock, that could be swapped out to improve overall system performance. Hardware can use this hint to suspend and resume multiple software threads if it supports the capability. For more information about the recommended use of this instruction see The Yield instruction on page A4-178. - -@encoding (t1) { - - @half 1 0 1 1 1 1 1 1 0 0 0 1 0 0 0 0 - -} - -@encoding (T2) { - - @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - @syntax ".W" - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 - - @rules { - - chk_call StoreCondition(cond) - - } - -} - diff --git a/src/arch/arm/v7/operands/Makefile.am b/src/arch/arm/v7/operands/Makefile.am deleted file mode 100644 index 8cf73b8..0000000 --- a/src/arch/arm/v7/operands/Makefile.am +++ /dev/null @@ -1,21 +0,0 @@ - -noinst_LTLIBRARIES = libarcharmv7operands.la - -libarcharmv7operands_la_SOURCES = \ - coproc.h coproc.c \ - estate.h estate.c \ - limitation.h limitation.c \ - maccess.h maccess.c \ - offset.h offset.c \ - reglist.h reglist.c \ - rotation.h rotation.c \ - shift.h shift.c - -libarcharmv7operands_la_LIBADD = - -libarcharmv7operands_la_CFLAGS = $(AM_CFLAGS) - - -AM_CPPFLAGS = $(LIBGTK_CFLAGS) $(LIBXML_CFLAGS) - -AM_CFLAGS = $(DEBUG_CFLAGS) $(WARNING_FLAGS) $(COMPLIANCE_FLAGS) diff --git a/src/arch/arm/v7/operands/coproc.c b/src/arch/arm/v7/operands/coproc.c deleted file mode 100644 index a0c0254..0000000 --- a/src/arch/arm/v7/operands/coproc.c +++ /dev/null @@ -1,250 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * coproc.c - décallages de valeurs - * - * Copyright (C) 2016-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#include "coproc.h" - - -#include "../../../operand-int.h" -#include "../../../../common/sort.h" - - - -/* Définition d'un opérande représentant un co-processeur (instance) */ -struct _GArmV7CoprocOperand -{ - GArchOperand parent; /* Instance parente */ - - uint8_t index; /* Indice du co-processeur */ - -}; - - -/* Définition d'un opérande représentant un co-processeur (classe) */ -struct _GArmV7CoprocOperandClass -{ - GArchOperandClass parent; /* Classe parente */ - -}; - - -/* Initialise la classe des coprocs de domaine et d'accès. */ -static void g_armv7_coproc_operand_class_init(GArmV7CoprocOperandClass *); - -/* Initialise une instance de coproc de domaine et d'accès. */ -static void g_armv7_coproc_operand_init(GArmV7CoprocOperand *); - -/* Supprime toutes les références externes. */ -static void g_armv7_coproc_operand_dispose(GArmV7CoprocOperand *); - -/* Procède à la libération totale de la mémoire. */ -static void g_armv7_coproc_operand_finalize(GArmV7CoprocOperand *); - -/* Compare un opérande avec un autre. */ -static int g_armv7_coproc_operand_compare(const GArmV7CoprocOperand *, const GArmV7CoprocOperand *); - -/* Traduit un opérande en version humainement lisible. */ -static void g_armv7_coproc_operand_print(const GArmV7CoprocOperand *, GBufferLine *, AsmSyntax); - - - -/* Indique le type défini par la GLib pour un co-processeur ARM. */ -G_DEFINE_TYPE(GArmV7CoprocOperand, g_armv7_coproc_operand, G_TYPE_ARCH_OPERAND); - - -/****************************************************************************** -* * -* Paramètres : klass = classe à initialiser. * -* * -* Description : Initialise la classe des co-processeurs ARM. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_coproc_operand_class_init(GArmV7CoprocOperandClass *klass) -{ - GObjectClass *object; /* Autre version de la classe */ - GArchOperandClass *operand; /* Version de classe parente */ - - object = G_OBJECT_CLASS(klass); - operand = G_ARCH_OPERAND_CLASS(klass); - - object->dispose = (GObjectFinalizeFunc/* ! */)g_armv7_coproc_operand_dispose; - object->finalize = (GObjectFinalizeFunc)g_armv7_coproc_operand_finalize; - - operand->compare = (operand_compare_fc)g_armv7_coproc_operand_compare; - operand->print = (operand_print_fc)g_armv7_coproc_operand_print; - -} - - -/****************************************************************************** -* * -* Paramètres : operand = instance à initialiser. * -* * -* Description : Initialise une instance de co-processeur ARM. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_coproc_operand_init(GArmV7CoprocOperand *operand) -{ - -} - - -/****************************************************************************** -* * -* Paramètres : operand = instance d'objet GLib à traiter. * -* * -* Description : Supprime toutes les références externes. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_coproc_operand_dispose(GArmV7CoprocOperand *operand) -{ - G_OBJECT_CLASS(g_armv7_coproc_operand_parent_class)->dispose(G_OBJECT(operand)); - -} - - -/****************************************************************************** -* * -* Paramètres : operand = instance d'objet GLib à traiter. * -* * -* Description : Procède à la libération totale de la mémoire. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_coproc_operand_finalize(GArmV7CoprocOperand *operand) -{ - G_OBJECT_CLASS(g_armv7_coproc_operand_parent_class)->finalize(G_OBJECT(operand)); - -} - - -/****************************************************************************** -* * -* Paramètres : a = premier opérande à consulter. * -* b = second opérande à consulter. * -* * -* Description : Compare un opérande avec un autre. * -* * -* Retour : Bilan de la comparaison. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static int g_armv7_coproc_operand_compare(const GArmV7CoprocOperand *a, const GArmV7CoprocOperand *b) -{ - int result; /* Bilan à faire remonter */ - - result = sort_unsigned_long(a->index, b->index); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : operand = opérande à traiter. * -* line = ligne tampon où imprimer l'opérande donné. * -* syntax = type de représentation demandée. * -* * -* Description : Traduit un opérande en version humainement lisible. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_coproc_operand_print(const GArmV7CoprocOperand *operand, GBufferLine *line, AsmSyntax syntax) -{ - char name[5]; /* Mot clef principal */ - size_t nlen; /* Taille de ce mot clef */ - - nlen = snprintf(name, sizeof(name), "p%hhu", operand->index); - - g_buffer_line_append_text(line, BLC_ASSEMBLY, name, nlen, RTT_REGISTER, NULL); - -} - - -/****************************************************************************** -* * -* Paramètres : raw = valeur brute du co-processeur à considérer. * -* * -* Description : Crée une représentation d'un co-processeur ARM. * -* * -* Retour : Opérande mis en place. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArchOperand *g_armv7_coproc_operand_new(uint8_t raw) -{ - GArmV7CoprocOperand *result; /* Structure à retourner */ - - result = g_object_new(G_TYPE_ARMV7_COPROC_OPERAND, NULL); - - result->index = raw; - - return G_ARCH_OPERAND(result); - -} - - -/****************************************************************************** -* * -* Paramètres : operand = opérande à consulter. * -* * -* Description : Fournit l'indice d'un co-processeur ARM. * -* * -* Retour : Inditifiant représentant le co-processeur. * -* * -* Remarques : - * -* * -******************************************************************************/ - -uint8_t g_armv7_coproc_operand_get_index(const GArmV7CoprocOperand *operand) -{ - return operand->index; - -} diff --git a/src/arch/arm/v7/operands/coproc.h b/src/arch/arm/v7/operands/coproc.h deleted file mode 100644 index 07224d3..0000000 --- a/src/arch/arm/v7/operands/coproc.h +++ /dev/null @@ -1,61 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * coproc.h - prototypes pour les décallages de valeurs - * - * Copyright (C) 2016-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_ARM_V7_OPERANDS_COPROC_H -#define _ARCH_ARM_V7_OPERANDS_COPROC_H - - -#include <glib-object.h> - - -#include "../../../operand.h" - - - -#define G_TYPE_ARMV7_COPROC_OPERAND g_armv7_coproc_operand_get_type() -#define G_ARMV7_COPROC_OPERAND(obj) (G_TYPE_CHECK_INSTANCE_CAST((obj), g_armv7_coproc_operand_get_type(), GArmV7CoprocOperand)) -#define G_IS_ARMV7_COPROC_OPERAND(obj) (G_TYPE_CHECK_INSTANCE_TYPE((obj), g_armv7_coproc_operand_get_type())) -#define G_ARMV7_COPROC_OPERAND_CLASS(klass) (G_TYPE_CHECK_CLASS_CAST((klass), G_TYPE_ARMV7_COPROC_OPERAND, GArmV7CoprocOperandClass)) -#define G_IS_ARMV7_COPROC_OPERAND_CLASS(klass) (G_TYPE_CHECK_CLASS_TYPE((klass), G_TYPE_ARMV7_COPROC_OPERAND)) -#define G_ARMV7_COPROC_OPERAND_GET_CLASS(obj) (G_TYPE_INSTANCE_GET_CLASS((obj), G_TYPE_ARMV7_COPROC_OPERAND, GArmV7CoprocOperandClass)) - - -/* Définition d'un opérande représentant un co-processeur (instance) */ -typedef struct _GArmV7CoprocOperand GArmV7CoprocOperand; - -/* Définition d'un opérande représentant un co-processeur (classe) */ -typedef struct _GArmV7CoprocOperandClass GArmV7CoprocOperandClass; - - -/* Indique le type défini par la GLib pour un co-processeur ARM. */ -GType g_armv7_coproc_operand_get_type(void); - -/* Crée une représentation d'un co-processeur ARM. */ -GArchOperand *g_armv7_coproc_operand_new(uint8_t); - -/* Fournit l'indice d'un co-processeur ARM. */ -uint8_t g_armv7_coproc_operand_get_index(const GArmV7CoprocOperand *); - - - -#endif /* _ARCH_ARM_V7_OPERANDS_COPROC_H */ diff --git a/src/arch/arm/v7/operands/estate.c b/src/arch/arm/v7/operands/estate.c deleted file mode 100644 index 0756110..0000000 --- a/src/arch/arm/v7/operands/estate.c +++ /dev/null @@ -1,248 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * endian.c - décallages de valeurs - * - * Copyright (C) 2016-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#include "estate.h" - - -#include "../../../operand-int.h" -#include "../../../../common/sort.h" - - - -/* Définition d'un opérande affichant le choix d'un boutisme (instance) */ -struct _GArmV7EndianOperand -{ - GArchOperand parent; /* Instance parente */ - - bool big; /* Grand boutisme à afficher ? */ - -}; - - -/* Définition d'un opérande affichant le choix d'un boutisme (classe) */ -struct _GArmV7EndianOperandClass -{ - GArchOperandClass parent; /* Classe parente */ - -}; - - -/* Initialise la classe des affichages de boutisme. */ -static void g_armv7_endian_operand_class_init(GArmV7EndianOperandClass *); - -/* Initialise une instance d'affichage de boutisme. */ -static void g_armv7_endian_operand_init(GArmV7EndianOperand *); - -/* Supprime toutes les références externes. */ -static void g_armv7_endian_operand_dispose(GArmV7EndianOperand *); - -/* Procède à la libération totale de la mémoire. */ -static void g_armv7_endian_operand_finalize(GArmV7EndianOperand *); - -/* Compare un opérande avec un autre. */ -static int g_armv7_endian_operand_compare(const GArmV7EndianOperand *, const GArmV7EndianOperand *); - -/* Traduit un opérande en version humainement lisible. */ -static void g_armv7_endian_operand_print(const GArmV7EndianOperand *, GBufferLine *, AsmSyntax); - - - -/* Indique le type défini par la GLib pour une endian de domaine et d'accès. */ -G_DEFINE_TYPE(GArmV7EndianOperand, g_armv7_endian_operand, G_TYPE_ARCH_OPERAND); - - -/****************************************************************************** -* * -* Paramètres : klass = classe à initialiser. * -* * -* Description : Initialise la classe des affichages de boutisme. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_endian_operand_class_init(GArmV7EndianOperandClass *klass) -{ - GObjectClass *object; /* Autre version de la classe */ - GArchOperandClass *operand; /* Version de classe parente */ - - object = G_OBJECT_CLASS(klass); - operand = G_ARCH_OPERAND_CLASS(klass); - - object->dispose = (GObjectFinalizeFunc/* ! */)g_armv7_endian_operand_dispose; - object->finalize = (GObjectFinalizeFunc)g_armv7_endian_operand_finalize; - - operand->compare = (operand_compare_fc)g_armv7_endian_operand_compare; - operand->print = (operand_print_fc)g_armv7_endian_operand_print; - -} - - -/****************************************************************************** -* * -* Paramètres : operand = instance à initialiser. * -* * -* Description : Initialise une instance d'affichage de boutisme. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_endian_operand_init(GArmV7EndianOperand *operand) -{ - -} - - -/****************************************************************************** -* * -* Paramètres : operand = instance d'objet GLib à traiter. * -* * -* Description : Supprime toutes les références externes. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_endian_operand_dispose(GArmV7EndianOperand *operand) -{ - G_OBJECT_CLASS(g_armv7_endian_operand_parent_class)->dispose(G_OBJECT(operand)); - -} - - -/****************************************************************************** -* * -* Paramètres : operand = instance d'objet GLib à traiter. * -* * -* Description : Procède à la libération totale de la mémoire. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_endian_operand_finalize(GArmV7EndianOperand *operand) -{ - G_OBJECT_CLASS(g_armv7_endian_operand_parent_class)->finalize(G_OBJECT(operand)); - -} - - -/****************************************************************************** -* * -* Paramètres : a = premier opérande à consulter. * -* b = second opérande à consulter. * -* * -* Description : Compare un opérande avec un autre. * -* * -* Retour : Bilan de la comparaison. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static int g_armv7_endian_operand_compare(const GArmV7EndianOperand *a, const GArmV7EndianOperand *b) -{ - int result; /* Bilan à faire remonter */ - - result = sort_boolean(a->big, b->big); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : operand = opérande à traiter. * -* line = ligne tampon où imprimer l'opérande donné. * -* syntax = type de représentation demandée. * -* * -* Description : Traduit un opérande en version humainement lisible. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_endian_operand_print(const GArmV7EndianOperand *operand, GBufferLine *line, AsmSyntax syntax) -{ - if (operand->big) - g_buffer_line_append_text(line, BLC_ASSEMBLY, "BE", 2, RTT_KEY_WORD, NULL); - else - g_buffer_line_append_text(line, BLC_ASSEMBLY, "LE", 2, RTT_KEY_WORD, NULL); - -} - - -/****************************************************************************** -* * -* Paramètres : big = indication sur le boutisme à représenter. * -* * -* Description : Crée une représentation de boutisme ARMv7. * -* * -* Retour : Opérande mis en place. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArchOperand *g_armv7_endian_operand_new(bool big) -{ - GArmV7EndianOperand *result; /* Structure à retourner */ - - result = g_object_new(G_TYPE_ARMV7_ENDIAN_OPERAND, NULL); - - result->big = big; - - return G_ARCH_OPERAND(result); - -} - - -/****************************************************************************** -* * -* Paramètres : operand = opérande à consulter. * -* * -* Description : Indique le type de boutisme représenté. * -* * -* Retour : Type de boutisme. * -* * -* Remarques : - * -* * -******************************************************************************/ - -bool g_armv7_endian_operand_is_big_endian(const GArmV7EndianOperand *operand) -{ - return operand->big; - -} diff --git a/src/arch/arm/v7/operands/estate.h b/src/arch/arm/v7/operands/estate.h deleted file mode 100644 index a1726cf..0000000 --- a/src/arch/arm/v7/operands/estate.h +++ /dev/null @@ -1,61 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * estate.h - prototypes pour le basculement de boutisme - * - * Copyright (C) 2016-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_ARM_V7_OPERANDS_ESTATE_H -#define _ARCH_ARM_V7_OPERANDS_ESTATE_H - - -#include <glib-object.h> - - -#include "../../../operand.h" - - - -#define G_TYPE_ARMV7_ENDIAN_OPERAND g_armv7_endian_operand_get_type() -#define G_ARMV7_ENDIAN_OPERAND(obj) (G_TYPE_CHECK_INSTANCE_CAST((obj), g_armv7_endian_operand_get_type(), GArmV7EndianOperand)) -#define G_IS_ARMV7_ENDIAN_OPERAND(obj) (G_TYPE_CHECK_INSTANCE_TYPE((obj), g_armv7_endian_operand_get_type())) -#define G_ARMV7_ENDIAN_OPERAND_CLASS(klass) (G_TYPE_CHECK_CLASS_CAST((klass), G_TYPE_ARMV7_ENDIAN_OPERAND, GArmV7EndianOperandClass)) -#define G_IS_ARMV7_ENDIAN_OPERAND_CLASS(klass) (G_TYPE_CHECK_CLASS_TYPE((klass), G_TYPE_ARMV7_ENDIAN_OPERAND)) -#define G_ARMV7_ENDIAN_OPERAND_GET_CLASS(obj) (G_TYPE_INSTANCE_GET_CLASS((obj), G_TYPE_ARMV7_ENDIAN_OPERAND, GArmV7EndianOperandClass)) - - -/* Définition d'un opérande affichant le choix d'un boutisme (instance) */ -typedef struct _GArmV7EndianOperand GArmV7EndianOperand; - -/* Définition d'un opérande affichant le choix d'un boutisme (classe) */ -typedef struct _GArmV7EndianOperandClass GArmV7EndianOperandClass; - - -/* Indique le type défini par la GLib pour une endian de domaine et d'accès. */ -GType g_armv7_endian_operand_get_type(void); - -/* Crée une représentation de boutisme ARMv7. */ -GArchOperand *g_armv7_endian_operand_new(bool); - -/* Indique le type de boutisme représenté. */ -bool g_armv7_endian_operand_is_big_endian(const GArmV7EndianOperand *); - - - -#endif /* _ARCH_ARM_V7_OPERANDS_ESTATE_H */ diff --git a/src/arch/arm/v7/operands/limitation.c b/src/arch/arm/v7/operands/limitation.c deleted file mode 100644 index 75e958f..0000000 --- a/src/arch/arm/v7/operands/limitation.c +++ /dev/null @@ -1,287 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * limitation.c - décallages de valeurs - * - * Copyright (C) 2016-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#include "limitation.h" - - -#include "../../../operand-int.h" -#include "../../../../common/sort.h" - - - -/* Définition d'un opérande déterminant une limitation de domaine et d'accès (instance) */ -struct _GArmV7LimitationOperand -{ - GArchOperand parent; /* Instance parente */ - - BarrierLimitationType type; /* Type de limitation */ - -}; - - -/* Définition d'un opérande déterminant une limitation de domaine et d'accès (classe) */ -struct _GArmV7LimitationOperandClass -{ - GArchOperandClass parent; /* Classe parente */ - -}; - - -/* Initialise la classe des co-processeurs ARM. */ -static void g_armv7_limitation_operand_class_init(GArmV7LimitationOperandClass *); - -/* Initialise une instance de co-processeur ARM. */ -static void g_armv7_limitation_operand_init(GArmV7LimitationOperand *); - -/* Supprime toutes les références externes. */ -static void g_armv7_limitation_operand_dispose(GArmV7LimitationOperand *); - -/* Procède à la libération totale de la mémoire. */ -static void g_armv7_limitation_operand_finalize(GArmV7LimitationOperand *); - -/* Compare un opérande avec un autre. */ -static int g_armv7_limitation_operand_compare(const GArmV7LimitationOperand *, const GArmV7LimitationOperand *); - -/* Traduit un opérande en version humainement lisible. */ -static void g_armv7_limitation_operand_print(const GArmV7LimitationOperand *, GBufferLine *, AsmSyntax); - - - -/* Indique le type défini par la GLib pour une limitation de domaine et d'accès. */ -G_DEFINE_TYPE(GArmV7LimitationOperand, g_armv7_limitation_operand, G_TYPE_ARCH_OPERAND); - - -/****************************************************************************** -* * -* Paramètres : klass = classe à initialiser. * -* * -* Description : Initialise la classe des limitations de domaine et d'accès. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_limitation_operand_class_init(GArmV7LimitationOperandClass *klass) -{ - GObjectClass *object; /* Autre version de la classe */ - GArchOperandClass *operand; /* Version de classe parente */ - - object = G_OBJECT_CLASS(klass); - operand = G_ARCH_OPERAND_CLASS(klass); - - object->dispose = (GObjectFinalizeFunc/* ! */)g_armv7_limitation_operand_dispose; - object->finalize = (GObjectFinalizeFunc)g_armv7_limitation_operand_finalize; - - operand->compare = (operand_compare_fc)g_armv7_limitation_operand_compare; - operand->print = (operand_print_fc)g_armv7_limitation_operand_print; - -} - - -/****************************************************************************** -* * -* Paramètres : operand = instance à initialiser. * -* * -* Description : Initialise une instance de limitation de domaine et d'accès. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_limitation_operand_init(GArmV7LimitationOperand *operand) -{ - -} - - -/****************************************************************************** -* * -* Paramètres : operand = instance d'objet GLib à traiter. * -* * -* Description : Supprime toutes les références externes. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_limitation_operand_dispose(GArmV7LimitationOperand *operand) -{ - G_OBJECT_CLASS(g_armv7_limitation_operand_parent_class)->dispose(G_OBJECT(operand)); - -} - - -/****************************************************************************** -* * -* Paramètres : operand = instance d'objet GLib à traiter. * -* * -* Description : Procède à la libération totale de la mémoire. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_limitation_operand_finalize(GArmV7LimitationOperand *operand) -{ - G_OBJECT_CLASS(g_armv7_limitation_operand_parent_class)->finalize(G_OBJECT(operand)); - -} - - -/****************************************************************************** -* * -* Paramètres : a = premier opérande à consulter. * -* b = second opérande à consulter. * -* * -* Description : Compare un opérande avec un autre. * -* * -* Retour : Bilan de la comparaison. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static int g_armv7_limitation_operand_compare(const GArmV7LimitationOperand *a, const GArmV7LimitationOperand *b) -{ - int result; /* Bilan à faire remonter */ - - result = sort_unsigned_long(a->type, b->type); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : operand = opérande à traiter. * -* line = ligne tampon où imprimer l'opérande donné. * -* syntax = type de représentation demandée. * -* * -* Description : Traduit un opérande en version humainement lisible. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_limitation_operand_print(const GArmV7LimitationOperand *operand, GBufferLine *line, AsmSyntax syntax) -{ - switch (operand->type) - { - case BLT_SY: - g_buffer_line_append_text(line, BLC_ASSEMBLY, "SY", 2, RTT_KEY_WORD, NULL); - break; - - case BLT_ST: - g_buffer_line_append_text(line, BLC_ASSEMBLY, "ST", 2, RTT_KEY_WORD, NULL); - break; - - case BLT_ISH: - g_buffer_line_append_text(line, BLC_ASSEMBLY, "ISH", 3, RTT_KEY_WORD, NULL); - break; - - case BLT_ISHST: - g_buffer_line_append_text(line, BLC_ASSEMBLY, "ISHST", 5, RTT_KEY_WORD, NULL); - break; - - case BLT_NSH: - g_buffer_line_append_text(line, BLC_ASSEMBLY, "NSH", 3, RTT_KEY_WORD, NULL); - break; - - case BLT_NSHST: - g_buffer_line_append_text(line, BLC_ASSEMBLY, "NSHST", 5, RTT_KEY_WORD, NULL); - break; - - case BLT_OSH: - g_buffer_line_append_text(line, BLC_ASSEMBLY, "OSH", 3, RTT_KEY_WORD, NULL); - break; - - case BLT_OSHST: - g_buffer_line_append_text(line, BLC_ASSEMBLY, "OSHST", 5, RTT_KEY_WORD, NULL); - break; - - default: - g_buffer_line_append_text(line, BLC_ASSEMBLY, "(reserved)", 10, RTT_KEY_WORD, NULL); - break; - - } - -} - - -/****************************************************************************** -* * -* Paramètres : raw = valeur brute de la limitation à considérer. * -* * -* Description : Crée une représentation d'une limitation pour barrière. * -* * -* Retour : Opérande mis en place. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArchOperand *g_armv7_limitation_operand_new(uint8_t raw) -{ - GArmV7LimitationOperand *result; /* Structure à retourner */ - - result = g_object_new(G_TYPE_ARMV7_LIMITATION_OPERAND, NULL); - - if (raw < 0b0010 || raw > 0b1111) - result->type = BLT_RESERVED; - - else - result->type = raw; - - return G_ARCH_OPERAND(result); - -} - - -/****************************************************************************** -* * -* Paramètres : operand = opérande à consulter. * -* * -* Description : Indique le type de limitation représentée. * -* * -* Retour : Type de limitation d'accès et de domaine. * -* * -* Remarques : - * -* * -******************************************************************************/ - -BarrierLimitationType g_armv7_limitation_operand_get_value(const GArmV7LimitationOperand *operand) -{ - return operand->type; - -} diff --git a/src/arch/arm/v7/operands/limitation.h b/src/arch/arm/v7/operands/limitation.h deleted file mode 100644 index 4f7db88..0000000 --- a/src/arch/arm/v7/operands/limitation.h +++ /dev/null @@ -1,77 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * limitation.h - prototypes pour les décallages de valeurs - * - * Copyright (C) 2016-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_ARM_V7_OPERANDS_LIMITATION_H -#define _ARCH_ARM_V7_OPERANDS_LIMITATION_H - - -#include <glib-object.h> - - -#include "../../../operand.h" - - - -#define G_TYPE_ARMV7_LIMITATION_OPERAND g_armv7_limitation_operand_get_type() -#define G_ARMV7_LIMITATION_OPERAND(obj) (G_TYPE_CHECK_INSTANCE_CAST((obj), g_armv7_limitation_operand_get_type(), GArmV7LimitationOperand)) -#define G_IS_ARMV7_LIMITATION_OPERAND(obj) (G_TYPE_CHECK_INSTANCE_TYPE((obj), g_armv7_limitation_operand_get_type())) -#define G_ARMV7_LIMITATION_OPERAND_CLASS(klass) (G_TYPE_CHECK_CLASS_CAST((klass), G_TYPE_ARMV7_LIMITATION_OPERAND, GArmV7LimitationOperandClass)) -#define G_IS_ARMV7_LIMITATION_OPERAND_CLASS(klass) (G_TYPE_CHECK_CLASS_TYPE((klass), G_TYPE_ARMV7_LIMITATION_OPERAND)) -#define G_ARMV7_LIMITATION_OPERAND_GET_CLASS(obj) (G_TYPE_INSTANCE_GET_CLASS((obj), G_TYPE_ARMV7_LIMITATION_OPERAND, GArmV7LimitationOperandClass)) - - -/* Définition d'un opérande déterminant une limitation de domaine et d'accès (instance) */ -typedef struct _GArmV7LimitationOperand GArmV7LimitationOperand; - -/* Définition d'un opérande déterminant une limitation de domaine et d'accès (classe) */ -typedef struct _GArmV7LimitationOperandClass GArmV7LimitationOperandClass; - - -/* Types de limitation domaine & accès */ -typedef enum _BarrierLimitationType -{ - BLT_RESERVED = 0, - BLT_SY = 0b1111, - BLT_ST = 0b1110, - BLT_ISH = 0b1011, - BLT_ISHST = 0b1010, - BLT_NSH = 0b0111, - BLT_NSHST = 0b0110, - BLT_OSH = 0b0011, - BLT_OSHST = 0b0010 - -} BarrierLimitationType; - - -/* Indique le type défini par la GLib pour une limitation de domaine et d'accès. */ -GType g_armv7_limitation_operand_get_type(void); - -/* Crée une représentation d'une limitation pour barrière. */ -GArchOperand *g_armv7_limitation_operand_new(uint8_t); - -/* Indique le type de limitation représentée. */ -BarrierLimitationType g_armv7_limitation_operand_get_value(const GArmV7LimitationOperand *); - - - -#endif /* _ARCH_ARM_V7_OPERANDS_LIMITATION_H */ diff --git a/src/arch/arm/v7/operands/maccess.c b/src/arch/arm/v7/operands/maccess.c deleted file mode 100644 index 6daf821..0000000 --- a/src/arch/arm/v7/operands/maccess.c +++ /dev/null @@ -1,385 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * maccess.c - accès à la mémorie à partir d'un registre et d'un décallage - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#include "maccess.h" - - -#include "../../../operand-int.h" -#include "../../../../common/sort.h" - - - -/* Définition d'un opérande offrant un accès à la mémoire depuis une base (instance) */ -struct _GArmV7MAccessOperand -{ - GArchOperand parent; /* Instance parente */ - - GArchOperand *base; /* Base de l'accès en mémoire */ - GArchOperand *offset; /* Décallage pour l'adresse */ - GArchOperand *shift; /* Décallage pour le décallage */ - bool not_post_indexed; /* Positio du décallage */ - bool write_back; /* Mise à jour de la base */ - -}; - - -/* Définition d'un opérande offrant un accès à la mémoire depuis une base (classe) */ -struct _GArmV7MAccessOperandClass -{ - GArchOperandClass parent; /* Classe parente */ - -}; - - -/* Initialise la classe des accès à la mémoire chez ARM. */ -static void g_armv7_maccess_operand_class_init(GArmV7MAccessOperandClass *); - -/* Initialise une instance d'accès à la mémoire chez ARM. */ -static void g_armv7_maccess_operand_init(GArmV7MAccessOperand *); - -/* Supprime toutes les références externes. */ -static void g_armv7_maccess_operand_dispose(GArmV7MAccessOperand *); - -/* Procède à la libération totale de la mémoire. */ -static void g_armv7_maccess_operand_finalize(GArmV7MAccessOperand *); - -/* Compare un opérande avec un autre. */ -static int g_armv7_maccess_operand_compare(const GArmV7MAccessOperand *, const GArmV7MAccessOperand *); - -/* Traduit un opérande en version humainement lisible. */ -static void g_armv7_maccess_operand_print(const GArmV7MAccessOperand *, GBufferLine *, AsmSyntax); - - - -/* Indique le type défini par la GLib pour un accès à la mémoire depuis une base. */ -G_DEFINE_TYPE(GArmV7MAccessOperand, g_armv7_maccess_operand, G_TYPE_ARCH_OPERAND); - - -/****************************************************************************** -* * -* Paramètres : klass = classe à initialiser. * -* * -* Description : Initialise la classe des accès à la mémoire chez ARM. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_maccess_operand_class_init(GArmV7MAccessOperandClass *klass) -{ - GObjectClass *object; /* Autre version de la classe */ - GArchOperandClass *operand; /* Version de classe parente */ - - object = G_OBJECT_CLASS(klass); - operand = G_ARCH_OPERAND_CLASS(klass); - - object->dispose = (GObjectFinalizeFunc/* ! */)g_armv7_maccess_operand_dispose; - object->finalize = (GObjectFinalizeFunc)g_armv7_maccess_operand_finalize; - - operand->compare = (operand_compare_fc)g_armv7_maccess_operand_compare; - operand->print = (operand_print_fc)g_armv7_maccess_operand_print; - -} - - -/****************************************************************************** -* * -* Paramètres : operand = instance à initialiser. * -* * -* Description : Initialise une instance d'accès à la mémoire chez ARM. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_maccess_operand_init(GArmV7MAccessOperand *operand) -{ - -} - - -/****************************************************************************** -* * -* Paramètres : operand = instance d'objet GLib à traiter. * -* * -* Description : Supprime toutes les références externes. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_maccess_operand_dispose(GArmV7MAccessOperand *operand) -{ - g_object_unref(G_OBJECT(operand->base)); - - if (operand->offset != NULL) - g_object_unref(G_OBJECT(operand->offset)); - - if (operand->shift != NULL) - g_object_unref(G_OBJECT(operand->shift)); - - G_OBJECT_CLASS(g_armv7_maccess_operand_parent_class)->dispose(G_OBJECT(operand)); - -} - - -/****************************************************************************** -* * -* Paramètres : operand = instance d'objet GLib à traiter. * -* * -* Description : Procède à la libération totale de la mémoire. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_maccess_operand_finalize(GArmV7MAccessOperand *operand) -{ - G_OBJECT_CLASS(g_armv7_maccess_operand_parent_class)->finalize(G_OBJECT(operand)); - -} - - -/****************************************************************************** -* * -* Paramètres : a = premier opérande à consulter. * -* b = second opérande à consulter. * -* * -* Description : Compare un opérande avec un autre. * -* * -* Retour : Bilan de la comparaison. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static int g_armv7_maccess_operand_compare(const GArmV7MAccessOperand *a, const GArmV7MAccessOperand *b) -{ - int result; /* Bilan à faire remonter */ - - result = g_arch_operand_compare(a->base, b->base); - if (result != 0) goto gamoc_done; - - result = sort_pointer(a->offset, b->offset, (__compar_fn_t)g_arch_operand_compare); - if (result != 0) goto gamoc_done; - - result = sort_pointer(a->shift, b->shift, (__compar_fn_t)g_arch_operand_compare); - if (result != 0) goto gamoc_done; - - result = sort_boolean(a->not_post_indexed, b->not_post_indexed); - if (result != 0) goto gamoc_done; - - result = sort_boolean(a->write_back, b->write_back); - - gamoc_done: - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : operand = opérande à traiter. * -* line = ligne tampon où imprimer l'opérande donné. * -* syntax = type de représentation demandée. * -* * -* Description : Traduit un opérande en version humainement lisible. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_maccess_operand_print(const GArmV7MAccessOperand *operand, GBufferLine *line, AsmSyntax syntax) -{ - g_buffer_line_append_text(line, BLC_ASSEMBLY, "[", 1, RTT_HOOK, NULL); - - g_arch_operand_print(operand->base, line, syntax); - - if (!operand->not_post_indexed) - g_buffer_line_append_text(line, BLC_ASSEMBLY, "]", 1, RTT_HOOK, NULL); - - if (operand->offset != NULL) - { - g_buffer_line_append_text(line, BLC_ASSEMBLY, ",", 1, RTT_PUNCT, NULL); - g_buffer_line_append_text(line, BLC_ASSEMBLY, " ", 1, RTT_RAW, NULL); - - g_arch_operand_print(operand->offset, line, syntax); - - } - - if (operand->shift != NULL) - { - g_buffer_line_append_text(line, BLC_ASSEMBLY, ",", 1, RTT_PUNCT, NULL); - g_buffer_line_append_text(line, BLC_ASSEMBLY, " ", 1, RTT_RAW, NULL); - - g_arch_operand_print(operand->shift, line, syntax); - - } - - if (operand->not_post_indexed) - g_buffer_line_append_text(line, BLC_ASSEMBLY, "]", 1, RTT_HOOK, NULL); - - if (operand->write_back) - g_buffer_line_append_text(line, BLC_ASSEMBLY, "!", 1, RTT_PUNCT, NULL); - -} - - -/****************************************************************************** -* * -* Paramètres : base = représente le registre de la base d'accès. * -* offset = détermine le décallage entre l'adresse et la base. * -* shift = opération de décallage pour jouer sur le décallage.* -* indexed = précise la forme donnée au décallage à appliquer. * -* wback = indique une mise à jour de la base après usage. * -* * -* Description : Crée un accès à la mémoire depuis une base et un décallage. * -* * -* Retour : Opérande mis en place. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArchOperand *g_armv7_maccess_operand_new(GArchOperand *base, GArchOperand *offset, GArchOperand *shift, bool indexed, bool wback) -{ - GArmV7MAccessOperand *result; /* Structure à retourner */ - - result = g_object_new(G_TYPE_ARMV7_MACCESS_OPERAND, NULL); - - result->base = base; - result->offset = offset; - result->shift = shift; - - result->not_post_indexed = indexed; - result->write_back = wback; - - return G_ARCH_OPERAND(result); - -} - - -/****************************************************************************** -* * -* Paramètres : operand = opérande à consulter. * -* * -* Description : Founit la base d'un accès à la mémoire. * -* * -* Retour : Opérande en place. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArchOperand *g_armv7_maccess_operand_get_base(const GArmV7MAccessOperand *operand) -{ - return operand->base; - -} - - -/****************************************************************************** -* * -* Paramètres : operand = opérande à consulter. * -* * -* Description : Founit le décallage d'un accès à la mémoire depuis la base. * -* * -* Retour : Opérande en place. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArchOperand *g_armv7_maccess_operand_get_offset(const GArmV7MAccessOperand *operand) -{ - return operand->offset; - -} - - -/****************************************************************************** -* * -* Paramètres : operand = opérande à consulter. * -* * -* Description : Founit le décallage d'un décallage pour un accès mémoire. * -* * -* Retour : Opérande en place. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArchOperand *g_armv7_maccess_operand_get_shift(const GArmV7MAccessOperand *operand) -{ - return operand->shift; - -} - - -/****************************************************************************** -* * -* Paramètres : operand = opérande à consulter. * -* * -* Description : Indique si le décallage est post-indexé. * -* * -* Retour : Statut des opérations menées. * -* * -* Remarques : - * -* * -******************************************************************************/ - -bool g_armv7_maccess_operand_is_post_indexed(const GArmV7MAccessOperand *operand) -{ - return !operand->not_post_indexed; - -} - - -/****************************************************************************** -* * -* Paramètres : operand = opérande à consulter. * -* * -* Description : Indique si la base est mise à jour après usage. * -* * -* Retour : Statut des opérations menées. * -* * -* Remarques : - * -* * -******************************************************************************/ - -bool g_armv7_maccess_operand_has_to_write_back(const GArmV7MAccessOperand *operand) -{ - return operand->write_back; - -} diff --git a/src/arch/arm/v7/operands/maccess.h b/src/arch/arm/v7/operands/maccess.h deleted file mode 100644 index 6e99e0b..0000000 --- a/src/arch/arm/v7/operands/maccess.h +++ /dev/null @@ -1,75 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * maccess.h - prototypes pour les accès à la mémorie à partir d'un registre et d'un décallage - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_ARM_V7_OPERANDS_MACCESS_H -#define _ARCH_ARM_V7_OPERANDS_MACCESS_H - - -#include <glib-object.h> -#include <stdbool.h> - - -#include "../pseudo.h" -#include "../../../operand.h" - - - -#define G_TYPE_ARMV7_MACCESS_OPERAND g_armv7_maccess_operand_get_type() -#define G_ARMV7_MACCESS_OPERAND(obj) (G_TYPE_CHECK_INSTANCE_CAST((obj), g_armv7_maccess_operand_get_type(), GArmV7MAccessOperand)) -#define G_IS_ARMV7_MACCESS_OPERAND(obj) (G_TYPE_CHECK_INSTANCE_TYPE((obj), g_armv7_maccess_operand_get_type())) -#define G_ARMV7_MACCESS_OPERAND_CLASS(klass) (G_TYPE_CHECK_CLASS_CAST((klass), G_TYPE_ARMV7_MACCESS_OPERAND, GArmV7MAccessOperandClass)) -#define G_IS_ARMV7_MACCESS_OPERAND_CLASS(klass) (G_TYPE_CHECK_CLASS_TYPE((klass), G_TYPE_ARMV7_MACCESS_OPERAND)) -#define G_ARMV7_MACCESS_OPERAND_GET_CLASS(obj) (G_TYPE_INSTANCE_GET_CLASS((obj), G_TYPE_ARMV7_MACCESS_OPERAND, GArmV7MAccessOperandClass)) - - -/* Définition d'un opérande offrant un accès à la mémoire depuis une base (instance) */ -typedef struct _GArmV7MAccessOperand GArmV7MAccessOperand; - -/* Définition d'un opérande offrant un accès à la mémoire depuis une base (classe) */ -typedef struct _GArmV7MAccessOperandClass GArmV7MAccessOperandClass; - - -/* Indique le type défini par la GLib pour un accès à la mémoire depuis une base. */ -GType g_armv7_maccess_operand_get_type(void); - -/* Crée un accès à la mémoire depuis une base et un décallage. */ -GArchOperand *g_armv7_maccess_operand_new(GArchOperand *, GArchOperand *, GArchOperand *, bool, bool); - -/* Founit la base d'un accès à la mémoire. */ -GArchOperand *g_armv7_maccess_operand_get_base(const GArmV7MAccessOperand *); - -/* Founit le décallage d'un accès à la mémoire depuis la base. */ -GArchOperand *g_armv7_maccess_operand_get_offset(const GArmV7MAccessOperand *); - -/* Founit le décallage d'un décallage pour un accès mémoire. */ -GArchOperand *g_armv7_maccess_operand_get_shift(const GArmV7MAccessOperand *); - -/* Indique si le décallage est post-indexé. */ -bool g_armv7_maccess_operand_is_post_indexed(const GArmV7MAccessOperand *); - -/* Indique si la base est mise à jour après usage. */ -bool g_armv7_maccess_operand_has_to_write_back(const GArmV7MAccessOperand *); - - - -#endif /* _ARCH_ARM_V7_OPERANDS_MACCESS_H */ diff --git a/src/arch/arm/v7/operands/offset.c b/src/arch/arm/v7/operands/offset.c deleted file mode 100644 index b8df640..0000000 --- a/src/arch/arm/v7/operands/offset.c +++ /dev/null @@ -1,283 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * offset.c - constitution d'un décallage positif ou négatif - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#include "offset.h" - - -#include "../../../operand-int.h" -#include "../../../../common/sort.h" - - - -/* Définition d'un opérande visant à constituer un décallage relatif ARMv7 (instance) */ -struct _GArmV7OffsetOperand -{ - GArchOperand parent; /* Instance parente */ - - bool positive; /* Sens du décallage */ - GArchOperand *value; /* Valeur du décallage */ - -}; - - -/* Définition d'un opérande visant à constituer un décallage relatif ARMv7 (classe) */ -struct _GArmV7OffsetOperandClass -{ - GArchOperandClass parent; /* Classe parente */ - -}; - - -/* Initialise la classe des décallages relatifs ARMv7. */ -static void g_armv7_offset_operand_class_init(GArmV7OffsetOperandClass *); - -/* Initialise une instance de décallage relatif ARMv7. */ -static void g_armv7_offset_operand_init(GArmV7OffsetOperand *); - -/* Supprime toutes les références externes. */ -static void g_armv7_offset_operand_dispose(GArmV7OffsetOperand *); - -/* Procède à la libération totale de la mémoire. */ -static void g_armv7_offset_operand_finalize(GArmV7OffsetOperand *); - -/* Compare un opérande avec un autre. */ -static int g_armv7_offset_operand_compare(const GArmV7OffsetOperand *, const GArmV7OffsetOperand *); - -/* Traduit un opérande en version humainement lisible. */ -static void g_armv7_offset_operand_print(const GArmV7OffsetOperand *, GBufferLine *, AsmSyntax); - - - -/* Indique le type défini par la GLib pour un décallage relatif ARMv7. */ -G_DEFINE_TYPE(GArmV7OffsetOperand, g_armv7_offset_operand, G_TYPE_ARCH_OPERAND); - - -/****************************************************************************** -* * -* Paramètres : klass = classe à initialiser. * -* * -* Description : Initialise la classe des décallages relatifs ARMv7. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_offset_operand_class_init(GArmV7OffsetOperandClass *klass) -{ - GObjectClass *object; /* Autre version de la classe */ - GArchOperandClass *operand; /* Version de classe parente */ - - object = G_OBJECT_CLASS(klass); - operand = G_ARCH_OPERAND_CLASS(klass); - - object->dispose = (GObjectFinalizeFunc/* ! */)g_armv7_offset_operand_dispose; - object->finalize = (GObjectFinalizeFunc)g_armv7_offset_operand_finalize; - - operand->compare = (operand_compare_fc)g_armv7_offset_operand_compare; - operand->print = (operand_print_fc)g_armv7_offset_operand_print; - -} - - -/****************************************************************************** -* * -* Paramètres : operand = instance à initialiser. * -* * -* Description : Initialise une instance de décallage relatif ARMv7. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_offset_operand_init(GArmV7OffsetOperand *operand) -{ - -} - - -/****************************************************************************** -* * -* Paramètres : operand = instance d'objet GLib à traiter. * -* * -* Description : Supprime toutes les références externes. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_offset_operand_dispose(GArmV7OffsetOperand *operand) -{ - g_object_unref(G_OBJECT(operand->value)); - - G_OBJECT_CLASS(g_armv7_offset_operand_parent_class)->dispose(G_OBJECT(operand)); - -} - - -/****************************************************************************** -* * -* Paramètres : operand = instance d'objet GLib à traiter. * -* * -* Description : Procède à la libération totale de la mémoire. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_offset_operand_finalize(GArmV7OffsetOperand *operand) -{ - G_OBJECT_CLASS(g_armv7_offset_operand_parent_class)->finalize(G_OBJECT(operand)); - -} - - -/****************************************************************************** -* * -* Paramètres : a = premier opérande à consulter. * -* b = second opérande à consulter. * -* * -* Description : Compare un opérande avec un autre. * -* * -* Retour : Bilan de la comparaison. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static int g_armv7_offset_operand_compare(const GArmV7OffsetOperand *a, const GArmV7OffsetOperand *b) -{ - int result; /* Bilan à faire remonter */ - - result = sort_boolean(a->positive, b->positive); - if (result != 0) goto gaooc_done; - - result = g_arch_operand_compare(a->value, b->value); - - gaooc_done: - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : operand = opérande à traiter. * -* line = ligne tampon où imprimer l'opérande donné. * -* syntax = type de représentation demandée. * -* * -* Description : Traduit un opérande en version humainement lisible. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_offset_operand_print(const GArmV7OffsetOperand *operand, GBufferLine *line, AsmSyntax syntax) -{ - if (!operand->positive) - g_buffer_line_append_text(line, BLC_ASSEMBLY, "-", 1, RTT_KEY_WORD, NULL); - - g_arch_operand_print(operand->value, line, syntax); - -} - - -/****************************************************************************** -* * -* Paramètres : positive = indique si la quantité doit être ajoutée ou non. * -* value = valeur du décallage à appliquer. * -* * -* Description : Crée un décallage selon un sens et une valeur donnés. * -* * -* Retour : Opérande mis en place. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArchOperand *g_armv7_offset_operand_new(bool positive, GArchOperand *value) -{ - GArmV7OffsetOperand *result; /* Structure à retourner */ - - result = g_object_new(G_TYPE_ARMV7_OFFSET_OPERAND, NULL); - - result->positive = positive; - result->value = value; - - return G_ARCH_OPERAND(result); - -} - - -/****************************************************************************** -* * -* Paramètres : operand = opérande à consulter. * -* * -* Description : Indique le sens du décallage représenté. * -* * -* Retour : Indication d'ajout ou de retrait. * -* * -* Remarques : - * -* * -******************************************************************************/ - -bool g_armv7_offset_operand_is_positive(const GArmV7OffsetOperand *operand) -{ - return operand->positive; - -} - - -/****************************************************************************** -* * -* Paramètres : operand = opérande à consulter. * -* * -* Description : Founit la valeur utilisée pour un décallage. * -* * -* Retour : Opérande en place. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArchOperand *g_armv7_offset_operand_get_value(const GArmV7OffsetOperand *operand) -{ - GArchOperand *result; /* Instance à retourner */ - - result = operand->value; - - g_object_ref(G_OBJECT(result)); - - return result; - -} diff --git a/src/arch/arm/v7/operands/offset.h b/src/arch/arm/v7/operands/offset.h deleted file mode 100644 index 64744df..0000000 --- a/src/arch/arm/v7/operands/offset.h +++ /dev/null @@ -1,66 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * offset.h - prototypes pour la constitution d'un décallage positif ou négatif - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_ARM_V7_OPERANDS_OFFSET_H -#define _ARCH_ARM_V7_OPERANDS_OFFSET_H - - -#include <glib-object.h> -#include <stdbool.h> - - -#include "../pseudo.h" -#include "../../../operand.h" - - - -#define G_TYPE_ARMV7_OFFSET_OPERAND g_armv7_offset_operand_get_type() -#define G_ARMV7_OFFSET_OPERAND(obj) (G_TYPE_CHECK_INSTANCE_CAST((obj), g_armv7_offset_operand_get_type(), GArmV7OffsetOperand)) -#define G_IS_ARMV7_OFFSET_OPERAND(obj) (G_TYPE_CHECK_INSTANCE_TYPE((obj), g_armv7_offset_operand_get_type())) -#define G_ARMV7_OFFSET_OPERAND_CLASS(klass) (G_TYPE_CHECK_CLASS_CAST((klass), G_TYPE_ARMV7_OFFSET_OPERAND, GArmV7OffsetOperandClass)) -#define G_IS_ARMV7_OFFSET_OPERAND_CLASS(klass) (G_TYPE_CHECK_CLASS_TYPE((klass), G_TYPE_ARMV7_OFFSET_OPERAND)) -#define G_ARMV7_OFFSET_OPERAND_GET_CLASS(obj) (G_TYPE_INSTANCE_GET_CLASS((obj), G_TYPE_ARMV7_OFFSET_OPERAND, GArmV7OffsetOperandClass)) - - -/* Définition d'un opérande visant à constituer un décallage relatif ARMv7 (instance) */ -typedef struct _GArmV7OffsetOperand GArmV7OffsetOperand; - -/* Définition d'un opérande visant à constituer un décallage relatif ARMv7 (classe) */ -typedef struct _GArmV7OffsetOperandClass GArmV7OffsetOperandClass; - - -/* Indique le type défini par la GLib pour un décallage relatif ARMv7. */ -GType g_armv7_offset_operand_get_type(void); - -/* Crée un décallage selon un sens et une valeur donnés. */ -GArchOperand *g_armv7_offset_operand_new(bool, GArchOperand *); - -/* Indique le sens du décallage représenté. */ -bool g_armv7_offset_operand_is_positive(const GArmV7OffsetOperand *); - -/* Founit la valeur utilisée pour un décallage. */ -GArchOperand *g_armv7_offset_operand_get_value(const GArmV7OffsetOperand *); - - - -#endif /* _ARCH_ARM_V7_OPERANDS_OFFSET_H */ diff --git a/src/arch/arm/v7/operands/reglist.c b/src/arch/arm/v7/operands/reglist.c deleted file mode 100644 index 9f641b8..0000000 --- a/src/arch/arm/v7/operands/reglist.c +++ /dev/null @@ -1,376 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * reglist.c - accès à la mémorie à partir d'un registre et d'un décallage - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#include "reglist.h" - - -#include <assert.h> -#include <malloc.h> - - -#include "../../../operand-int.h" -#include "../../../register.h" -#include "../../../../common/sort.h" - - - -/* Définition d'un opérande listant une série de registres ARM (instance) */ -struct _GArmV7RegListOperand -{ - GArchOperand parent; /* Instance parente */ - - GArmV7Register **registers; /* Liste de registres intégrés */ - size_t count; /* Taille de cette liste */ - -}; - - -/* Définition d'un opérande listant une série de registres ARM (classe) */ -struct _GArmV7RegListOperandClass -{ - GArchOperandClass parent; /* Classe parente */ - -}; - - -/* Initialise la classe des listes de registres ARM. */ -static void g_armv7_reglist_operand_class_init(GArmV7RegListOperandClass *); - -/* Initialise une instance de liste de registres ARM. */ -static void g_armv7_reglist_operand_init(GArmV7RegListOperand *); - -/* Supprime toutes les références externes. */ -static void g_armv7_reglist_operand_dispose(GArmV7RegListOperand *); - -/* Procède à la libération totale de la mémoire. */ -static void g_armv7_reglist_operand_finalize(GArmV7RegListOperand *); - -/* Compare un opérande avec un autre. */ -static int g_armv7_reglist_operand_compare(const GArmV7RegListOperand *, const GArmV7RegListOperand *); - -/* Traduit un opérande en version humainement lisible. */ -static void g_armv7_reglist_operand_print(const GArmV7RegListOperand *, GBufferLine *, AsmSyntax); - - - -/* Indique le type défini par la GLib pour une liste de registres ARM. */ -G_DEFINE_TYPE(GArmV7RegListOperand, g_armv7_reglist_operand, G_TYPE_ARCH_OPERAND); - - -/****************************************************************************** -* * -* Paramètres : klass = classe à initialiser. * -* * -* Description : Initialise la classe des listes de registres ARM. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_reglist_operand_class_init(GArmV7RegListOperandClass *klass) -{ - GObjectClass *object; /* Autre version de la classe */ - GArchOperandClass *operand; /* Version de classe parente */ - - object = G_OBJECT_CLASS(klass); - operand = G_ARCH_OPERAND_CLASS(klass); - - object->dispose = (GObjectFinalizeFunc/* ! */)g_armv7_reglist_operand_dispose; - object->finalize = (GObjectFinalizeFunc)g_armv7_reglist_operand_finalize; - - operand->compare = (operand_compare_fc)g_armv7_reglist_operand_compare; - operand->print = (operand_print_fc)g_armv7_reglist_operand_print; - -} - - -/****************************************************************************** -* * -* Paramètres : operand = instance à initialiser. * -* * -* Description : Initialise une instance de liste de registres ARM. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_reglist_operand_init(GArmV7RegListOperand *operand) -{ - -} - - -/****************************************************************************** -* * -* Paramètres : operand = instance d'objet GLib à traiter. * -* * -* Description : Supprime toutes les références externes. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_reglist_operand_dispose(GArmV7RegListOperand *operand) -{ - size_t i; /* Boucle de parcours */ - - for (i = 0; i < operand->count; i++) - g_object_unref(G_OBJECT(operand->registers[i])); - - G_OBJECT_CLASS(g_armv7_reglist_operand_parent_class)->dispose(G_OBJECT(operand)); - -} - - -/****************************************************************************** -* * -* Paramètres : operand = instance d'objet GLib à traiter. * -* * -* Description : Procède à la libération totale de la mémoire. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_reglist_operand_finalize(GArmV7RegListOperand *operand) -{ - if (operand->registers != NULL) - free(operand->registers); - - G_OBJECT_CLASS(g_armv7_reglist_operand_parent_class)->finalize(G_OBJECT(operand)); - -} - - -/****************************************************************************** -* * -* Paramètres : a = premier opérande à consulter. * -* b = second opérande à consulter. * -* * -* Description : Compare un opérande avec un autre. * -* * -* Retour : Bilan de la comparaison. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static int g_armv7_reglist_operand_compare(const GArmV7RegListOperand *a, const GArmV7RegListOperand *b) -{ - int result; /* Bilan à faire remonter */ - size_t i; /* Boucle de parcours */ - GArchRegister *ra; /* Registre de la liste A */ - GArchRegister *rb; /* Registre de la liste B */ - - /* Création de l'objet... */ - if (b == NULL) - { - result = 1; - goto garoc_done; - } - - result = sort_unsigned_long(a->count, b->count); - if (result != 0) goto garoc_done; - - for (i = 0; i < a->count && result == 0; i++) - { - ra = G_ARCH_REGISTER(a->registers[i]); - rb = G_ARCH_REGISTER(b->registers[i]); - - result = g_arch_register_compare(ra, rb); - - } - - garoc_done: - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : operand = opérande à traiter. * -* line = ligne tampon où imprimer l'opérande donné. * -* syntax = type de représentation demandée. * -* * -* Description : Traduit un opérande en version humainement lisible. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_reglist_operand_print(const GArmV7RegListOperand *operand, GBufferLine *line, AsmSyntax syntax) -{ - size_t i; /* Boucle de parcours */ - - g_buffer_line_append_text(line, BLC_ASSEMBLY, "{", 1, RTT_HOOK, NULL); - - for (i = 0; i < operand->count; i++) - { - if (i > 0) - { - g_buffer_line_append_text(line, BLC_ASSEMBLY, ",", 1, RTT_PUNCT, NULL); - g_buffer_line_append_text(line, BLC_ASSEMBLY, " ", 1, RTT_RAW, NULL); - } - - g_arch_register_print(G_ARCH_REGISTER(operand->registers[i]), line, syntax); - - } - - g_buffer_line_append_text(line, BLC_ASSEMBLY, "}", 1, RTT_HOOK, NULL); - -} - - -/****************************************************************************** -* * -* Paramètres : - * -* * -* Description : Crée une liste vierge de registres ARM. * -* * -* Retour : Opérande mis en place. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArchOperand *g_armv7_reglist_operand_new(void) -{ - GArchOperand *result; /* Structure à retourner */ - - result = g_object_new(G_TYPE_ARMV7_REGLIST_OPERAND, NULL); - - return G_ARCH_OPERAND(result); - -} - - -/****************************************************************************** -* * -* Paramètres : operand = liste de registres à compléter. * -* selected = masque de bits pour les registres à intégrer. * -* * -* Description : Remplit une liste de registres de registres ARM. * -* * -* Retour : Bilan de l'opération. * -* * -* Remarques : - * -* * -******************************************************************************/ - -bool g_armv7_reglist_load_registers(GArmV7RegListOperand *operand, uint32_t selected) -{ - uint8_t i; /* Boucle de parcours */ - GArmV7Register *reg; /* Nouveau registre à intégrer */ - - for (i = 18; i < 32; i++) - if (selected & (1 << i)) return false; - - for (i = 0; i < 18; i++) - { - if ((selected & (1 << i)) == 0) continue; - - reg = g_armv7_register_new(i); - g_armv7_reglist_add_register(operand, reg); - - } - - return true; - -} - - -/****************************************************************************** -* * -* Paramètres : operand = liste de registres à compléter. * -* reg = nouveau registre à intégrer. * -* * -* Description : Ajoute un registre à une liste de registres ARM. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -void g_armv7_reglist_add_register(GArmV7RegListOperand *operand, GArmV7Register *reg) -{ - operand->registers = (GArmV7Register **)realloc(operand->registers, - ++operand->count * sizeof(GArmV7Register *)); - - operand->registers[operand->count - 1] = reg; - -} - - - -/****************************************************************************** -* * -* Paramètres : operand = opérande à consulter. * -* * -* Description : Compte le nombre de registres ARM composant la liste. * -* * -* Retour : Nombre positif ou nul. * -* * -* Remarques : - * -* * -******************************************************************************/ - -size_t g_armv7_reglist_count_registers(const GArmV7RegListOperand *operand) -{ - return operand->count; - -} - - -/****************************************************************************** -* * -* Paramètres : operand = opérande à consulter. * -* index = indice de l'élément à fournier. * -* * -* Description : Founit un élément donné d'une liste de registres ARM. * -* * -* Retour : Registre intégré à la liste manipulée. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArmV7Register *g_armv7_reglist_operand_get_register(const GArmV7RegListOperand *operand, size_t index) -{ - assert(index < operand->count); - - return operand->registers[index]; - -} diff --git a/src/arch/arm/v7/operands/reglist.h b/src/arch/arm/v7/operands/reglist.h deleted file mode 100644 index 7c60805..0000000 --- a/src/arch/arm/v7/operands/reglist.h +++ /dev/null @@ -1,72 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * reglist.h - prototypes pour les accès à la mémorie à partir d'un registre et d'un décallage - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_ARM_V7_OPERANDS_REGLIST_H -#define _ARCH_ARM_V7_OPERANDS_REGLIST_H - - -#include <glib-object.h> -#include <stdbool.h> - - -#include "../register.h" -#include "../../../operand.h" - - - -#define G_TYPE_ARMV7_REGLIST_OPERAND g_armv7_reglist_operand_get_type() -#define G_ARMV7_REGLIST_OPERAND(obj) (G_TYPE_CHECK_INSTANCE_CAST((obj), g_armv7_reglist_operand_get_type(), GArmV7RegListOperand)) -#define G_IS_ARMV7_REGLIST_OPERAND(obj) (G_TYPE_CHECK_INSTANCE_TYPE((obj), g_armv7_reglist_operand_get_type())) -#define G_ARMV7_REGLIST_OPERAND_CLASS(klass) (G_TYPE_CHECK_CLASS_CAST((klass), G_TYPE_ARMV7_REGLIST_OPERAND, GArmV7RegListOperandClass)) -#define G_IS_ARMV7_REGLIST_OPERAND_CLASS(klass) (G_TYPE_CHECK_CLASS_TYPE((klass), G_TYPE_ARMV7_REGLIST_OPERAND)) -#define G_ARMV7_REGLIST_OPERAND_GET_CLASS(obj) (G_TYPE_INSTANCE_GET_CLASS((obj), G_TYPE_ARMV7_REGLIST_OPERAND, GArmV7RegListOperandClass)) - - -/* Définition d'un opérande listant une série de registres ARM (instance) */ -typedef struct _GArmV7RegListOperand GArmV7RegListOperand; - -/* Définition d'un opérande listant une série de registres ARM (classe) */ -typedef struct _GArmV7RegListOperandClass GArmV7RegListOperandClass; - - -/* Indique le type défini par la GLib pour une liste de registres ARM. */ -GType g_armv7_reglist_operand_get_type(void); - -/* Crée une liste vierge de registres ARM. */ -GArchOperand *g_armv7_reglist_operand_new(void); - -/* Remplit une liste de registres de registres ARM. */ -bool g_armv7_reglist_load_registers(GArmV7RegListOperand *, uint32_t); - -/* Ajoute un registre à une liste de registres ARM. */ -void g_armv7_reglist_add_register(GArmV7RegListOperand *, GArmV7Register *); - -/* Compte le nombre de registres ARM composant la liste. */ -size_t g_armv7_reglist_count_registers(const GArmV7RegListOperand *); - -/* Founit un élément donné d'une liste de registres ARM. */ -GArmV7Register *g_armv7_reglist_operand_get_register(const GArmV7RegListOperand *, size_t ); - - - -#endif /* _ARCH_ARM_V7_OPERANDS_REGLIST_H */ diff --git a/src/arch/arm/v7/operands/rotation.c b/src/arch/arm/v7/operands/rotation.c deleted file mode 100644 index ba31441..0000000 --- a/src/arch/arm/v7/operands/rotation.c +++ /dev/null @@ -1,256 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * rotation.c - rotations de valeurs - * - * Copyright (C) 2015-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#include "rotation.h" - - -#include "../../../operand-int.h" - - - -/* Définition d'un opérande visant une opérande de rotation ARMv7 (instance) */ -struct _GArmV7RotationOperand -{ - GArchOperand parent; /* Instance parente */ - - GArchOperand *value; /* Valeur du décallage */ - -}; - - -/* Définition d'un opérande visant une opérande de rotation ARMv7 (classe) */ -struct _GArmV7RotationOperandClass -{ - GArchOperandClass parent; /* Classe parente */ - -}; - - -/* Initialise la classe des opérandes de rotation ARMv7. */ -static void g_armv7_rotation_operand_class_init(GArmV7RotationOperandClass *); - -/* Initialise une instance d'opérande de rotation ARMv7. */ -static void g_armv7_rotation_operand_init(GArmV7RotationOperand *); - -/* Supprime toutes les références externes. */ -static void g_armv7_rotation_operand_dispose(GArmV7RotationOperand *); - -/* Procède à la libération totale de la mémoire. */ -static void g_armv7_rotation_operand_finalize(GArmV7RotationOperand *); - -/* Compare un opérande avec un autre. */ -static int g_armv7_rotation_operand_compare(const GArmV7RotationOperand *, const GArmV7RotationOperand *); - -/* Traduit un opérande en version humainement lisible. */ -static void g_armv7_rotation_operand_print(const GArmV7RotationOperand *, GBufferLine *, AsmSyntax); - - - -/* Indique le type défini par la GLib pour une opérande de rotation ARMv7. */ -G_DEFINE_TYPE(GArmV7RotationOperand, g_armv7_rotation_operand, G_TYPE_ARCH_OPERAND); - - -/****************************************************************************** -* * -* Paramètres : klass = classe à initialiser. * -* * -* Description : Initialise la classe des opérandes de rotation ARMv7. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_rotation_operand_class_init(GArmV7RotationOperandClass *klass) -{ - GObjectClass *object; /* Autre version de la classe */ - GArchOperandClass *operand; /* Version de classe parente */ - - object = G_OBJECT_CLASS(klass); - operand = G_ARCH_OPERAND_CLASS(klass); - - object->dispose = (GObjectFinalizeFunc/* ! */)g_armv7_rotation_operand_dispose; - object->finalize = (GObjectFinalizeFunc)g_armv7_rotation_operand_finalize; - - operand->compare = (operand_compare_fc)g_armv7_rotation_operand_compare; - operand->print = (operand_print_fc)g_armv7_rotation_operand_print; - -} - - -/****************************************************************************** -* * -* Paramètres : operand = instance à initialiser. * -* * -* Description : Initialise une instance d'opérande de rotation ARMv7. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_rotation_operand_init(GArmV7RotationOperand *operand) -{ - -} - - -/****************************************************************************** -* * -* Paramètres : operand = instance d'objet GLib à traiter. * -* * -* Description : Supprime toutes les références externes. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_rotation_operand_dispose(GArmV7RotationOperand *operand) -{ - g_object_unref(G_OBJECT(operand->value)); - - G_OBJECT_CLASS(g_armv7_rotation_operand_parent_class)->dispose(G_OBJECT(operand)); - -} - - -/****************************************************************************** -* * -* Paramètres : operand = instance d'objet GLib à traiter. * -* * -* Description : Procède à la libération totale de la mémoire. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_rotation_operand_finalize(GArmV7RotationOperand *operand) -{ - G_OBJECT_CLASS(g_armv7_rotation_operand_parent_class)->finalize(G_OBJECT(operand)); - -} - - -/****************************************************************************** -* * -* Paramètres : a = premier opérande à consulter. * -* b = second opérande à consulter. * -* * -* Description : Compare un opérande avec un autre. * -* * -* Retour : Bilan de la comparaison. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static int g_armv7_rotation_operand_compare(const GArmV7RotationOperand *a, const GArmV7RotationOperand *b) -{ - int result; /* Bilan à faire remonter */ - - result = g_arch_operand_compare(a->value, b->value); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : operand = opérande à traiter. * -* line = ligne tampon où imprimer l'opérande donné. * -* syntax = type de représentation demandée. * -* * -* Description : Traduit un opérande en version humainement lisible. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_rotation_operand_print(const GArmV7RotationOperand *operand, GBufferLine *line, AsmSyntax syntax) -{ - g_buffer_line_append_text(line, BLC_ASSEMBLY, "ror", 3, RTT_KEY_WORD, NULL); - - g_buffer_line_append_text(line, BLC_ASSEMBLY, " ", 1, RTT_RAW, NULL); - - g_arch_operand_print(operand->value, line, syntax); - -} - - -/****************************************************************************** -* * -* Paramètres : - * -* * -* Description : Crée un réceptacle pour opérandes de rotation ARMv7. * -* * -* Retour : Opérande mis en place. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArchOperand *g_armv7_rotation_operand_new(GArchOperand *value) -{ - GArmV7RotationOperand *result; /* Structure à retourner */ - - result = g_object_new(G_TYPE_ARMV7_ROTATION_OPERAND, NULL); - - result->value = value; - - return G_ARCH_OPERAND(result); - -} - - -/****************************************************************************** -* * -* Paramètres : operand = opérande à consulter. * -* * -* Description : Founit la valeur utilisée pour une rotation. * -* * -* Retour : Opérande en place. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArchOperand *g_armv7_rotation_operand_get_value(const GArmV7RotationOperand *operand) -{ - GArchOperand *result; /* Instance à retourner */ - - result = operand->value; - - g_object_ref(G_OBJECT(result)); - - return result; - -} diff --git a/src/arch/arm/v7/operands/rotation.h b/src/arch/arm/v7/operands/rotation.h deleted file mode 100644 index 7fb6c09..0000000 --- a/src/arch/arm/v7/operands/rotation.h +++ /dev/null @@ -1,61 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * rotation.h - prototypes pour les rotations de valeurs - * - * Copyright (C) 2015-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_ARM_V7_OPERANDS_ROTATION_H -#define _ARCH_ARM_V7_OPERANDS_ROTATION_H - - -#include <glib-object.h> - - -#include "../../../operand.h" - - - -#define G_TYPE_ARMV7_ROTATION_OPERAND g_armv7_rotation_operand_get_type() -#define G_ARMV7_ROTATION_OPERAND(obj) (G_TYPE_CHECK_INSTANCE_CAST((obj), g_armv7_rotation_operand_get_type(), GArmV7RotationOperand)) -#define G_IS_ARMV7_ROTATION_OPERAND(obj) (G_TYPE_CHECK_INSTANCE_TYPE((obj), g_armv7_rotation_operand_get_type())) -#define G_ARMV7_ROTATION_OPERAND_CLASS(klass) (G_TYPE_CHECK_CLASS_CAST((klass), G_TYPE_ARMV7_ROTATION_OPERAND, GArmV7RotationOperandClass)) -#define G_IS_ARMV7_ROTATION_OPERAND_CLASS(klass) (G_TYPE_CHECK_CLASS_TYPE((klass), G_TYPE_ARMV7_ROTATION_OPERAND)) -#define G_ARMV7_ROTATION_OPERAND_GET_CLASS(obj) (G_TYPE_INSTANCE_GET_CLASS((obj), G_TYPE_ARMV7_ROTATION_OPERAND, GArmV7RotationOperandClass)) - - -/* Définition d'un opérande visant une opérande de rotation ARMv7 (instance) */ -typedef struct _GArmV7RotationOperand GArmV7RotationOperand; - -/* Définition d'un opérande visant une opérande de rotation ARMv7 (classe) */ -typedef struct _GArmV7RotationOperandClass GArmV7RotationOperandClass; - - -/* Indique le type défini par la GLib pour une opérande de rotation ARMv7. */ -GType g_armv7_rotation_operand_get_type(void); - -/* Crée un réceptacle pour opérandes de rotation ARMv7. */ -GArchOperand *g_armv7_rotation_operand_new(GArchOperand *); - -/* Founit la valeur utilisée pour une rotation. */ -GArchOperand *g_armv7_rotation_operand_get_value(const GArmV7RotationOperand *); - - - -#endif /* _ARCH_ARM_V7_OPERANDS_ROTATION_H */ diff --git a/src/arch/arm/v7/operands/shift.c b/src/arch/arm/v7/operands/shift.c deleted file mode 100644 index 6fbdbcb..0000000 --- a/src/arch/arm/v7/operands/shift.c +++ /dev/null @@ -1,300 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * shift.c - décallages de valeurs - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#include "shift.h" - - -#include "../../../operand-int.h" -#include "../../../../common/sort.h" - - - -/* Définition d'un opérande visant une opérande de décallage ARMv7 (instance) */ -struct _GArmV7ShiftOperand -{ - GArchOperand parent; /* Instance parente */ - - SRType shift_type; /* Type de décallage */ - GArchOperand *shift_value; /* Valeur du décallage */ - -}; - - -/* Définition d'un opérande visant une opérande de décallage ARMv7 (classe) */ -struct _GArmV7ShiftOperandClass -{ - GArchOperandClass parent; /* Classe parente */ - -}; - - -/* Initialise la classe des opérandes de décallage ARMv7. */ -static void g_armv7_shift_operand_class_init(GArmV7ShiftOperandClass *); - -/* Initialise une instance d'opérande de décallage ARMv7. */ -static void g_armv7_shift_operand_init(GArmV7ShiftOperand *); - -/* Supprime toutes les références externes. */ -static void g_armv7_shift_operand_dispose(GArmV7ShiftOperand *); - -/* Procède à la libération totale de la mémoire. */ -static void g_armv7_shift_operand_finalize(GArmV7ShiftOperand *); - -/* Compare un opérande avec un autre. */ -static int g_armv7_shift_operand_compare(const GArmV7ShiftOperand *, const GArmV7ShiftOperand *); - -/* Traduit un opérande en version humainement lisible. */ -static void g_armv7_shift_operand_print(const GArmV7ShiftOperand *, GBufferLine *, AsmSyntax); - - - -/* Indique le type défini par la GLib pour une opérande de décallage ARMv7. */ -G_DEFINE_TYPE(GArmV7ShiftOperand, g_armv7_shift_operand, G_TYPE_ARCH_OPERAND); - - -/****************************************************************************** -* * -* Paramètres : klass = classe à initialiser. * -* * -* Description : Initialise la classe des opérandes de décallage ARMv7. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_shift_operand_class_init(GArmV7ShiftOperandClass *klass) -{ - GObjectClass *object; /* Autre version de la classe */ - GArchOperandClass *operand; /* Version de classe parente */ - - object = G_OBJECT_CLASS(klass); - operand = G_ARCH_OPERAND_CLASS(klass); - - object->dispose = (GObjectFinalizeFunc/* ! */)g_armv7_shift_operand_dispose; - object->finalize = (GObjectFinalizeFunc)g_armv7_shift_operand_finalize; - - operand->compare = (operand_compare_fc)g_armv7_shift_operand_compare; - operand->print = (operand_print_fc)g_armv7_shift_operand_print; - -} - - -/****************************************************************************** -* * -* Paramètres : operand = instance à initialiser. * -* * -* Description : Initialise une instance d'opérande de décallage ARMv7. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_shift_operand_init(GArmV7ShiftOperand *operand) -{ - -} - - -/****************************************************************************** -* * -* Paramètres : operand = instance d'objet GLib à traiter. * -* * -* Description : Supprime toutes les références externes. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_shift_operand_dispose(GArmV7ShiftOperand *operand) -{ - g_object_unref(G_OBJECT(operand->shift_value)); - - G_OBJECT_CLASS(g_armv7_shift_operand_parent_class)->dispose(G_OBJECT(operand)); - -} - - -/****************************************************************************** -* * -* Paramètres : operand = instance d'objet GLib à traiter. * -* * -* Description : Procède à la libération totale de la mémoire. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_shift_operand_finalize(GArmV7ShiftOperand *operand) -{ - G_OBJECT_CLASS(g_armv7_shift_operand_parent_class)->finalize(G_OBJECT(operand)); - -} - - -/****************************************************************************** -* * -* Paramètres : a = premier opérande à consulter. * -* b = second opérande à consulter. * -* * -* Description : Compare un opérande avec un autre. * -* * -* Retour : Bilan de la comparaison. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static int g_armv7_shift_operand_compare(const GArmV7ShiftOperand *a, const GArmV7ShiftOperand *b) -{ - int result; /* Bilan à faire remonter */ - - result = sort_unsigned_long(a->shift_type, b->shift_type); - if (result != 0) goto gasoc_done; - - result = g_arch_operand_compare(a->shift_value, b->shift_value); - - gasoc_done: - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : operand = opérande à traiter. * -* line = ligne tampon où imprimer l'opérande donné. * -* syntax = type de représentation demandée. * -* * -* Description : Traduit un opérande en version humainement lisible. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_shift_operand_print(const GArmV7ShiftOperand *operand, GBufferLine *line, AsmSyntax syntax) -{ - switch (operand->shift_type) - { - case SRType_LSL: - g_buffer_line_append_text(line, BLC_ASSEMBLY, "lsl", 3, RTT_KEY_WORD, NULL); - break; - case SRType_LSR: - g_buffer_line_append_text(line, BLC_ASSEMBLY, "lsr", 3, RTT_KEY_WORD, NULL); - break; - case SRType_ASR: - g_buffer_line_append_text(line, BLC_ASSEMBLY, "asr", 3, RTT_KEY_WORD, NULL); - break; - case SRType_ROR: - g_buffer_line_append_text(line, BLC_ASSEMBLY, "ror", 3, RTT_KEY_WORD, NULL); - break; - case SRType_RRX: - g_buffer_line_append_text(line, BLC_ASSEMBLY, "rrx", 3, RTT_KEY_WORD, NULL); - break; - } - - g_buffer_line_append_text(line, BLC_ASSEMBLY, " ", 1, RTT_RAW, NULL); - - g_arch_operand_print(operand->shift_value, line, syntax); - -} - - -/****************************************************************************** -* * -* Paramètres : - * -* * -* Description : Crée un réceptacle pour opérande de décallage ARMv7. * -* * -* Retour : Opérande mis en place. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArchOperand *g_armv7_shift_operand_new(SRType type, GArchOperand *value) -{ - GArmV7ShiftOperand *result; /* Structure à retourner */ - - result = g_object_new(G_TYPE_ARMV7_SHIFT_OPERAND, NULL); - - result->shift_type = type; - result->shift_value = value; - - return G_ARCH_OPERAND(result); - -} - - -/****************************************************************************** -* * -* Paramètres : operand = opérande à consulter. * -* * -* Description : Indique la forme de décallage représenté. * -* * -* Retour : Type de décallage. * -* * -* Remarques : - * -* * -******************************************************************************/ - -SRType g_armv7_shift_operand_get_shift_type(const GArmV7ShiftOperand *operand) -{ - return operand->shift_type; - -} - - -/****************************************************************************** -* * -* Paramètres : operand = opérande à consulter. * -* * -* Description : Founit la valeur utilisée pour un décallage. * -* * -* Retour : Opérande en place. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArchOperand *g_armv7_shift_operand_get_shift_value(const GArmV7ShiftOperand *operand) -{ - GArchOperand *result; /* Instance à retourner */ - - result = operand->shift_value; - - g_object_ref(G_OBJECT(result)); - - return result; - -} diff --git a/src/arch/arm/v7/operands/shift.h b/src/arch/arm/v7/operands/shift.h deleted file mode 100644 index 2eac092..0000000 --- a/src/arch/arm/v7/operands/shift.h +++ /dev/null @@ -1,65 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * shift.h - prototypes pour les décallages de valeurs - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_ARM_V7_OPERANDS_SHIFT_H -#define _ARCH_ARM_V7_OPERANDS_SHIFT_H - - -#include <glib-object.h> - - -#include "../pseudo.h" -#include "../../../operand.h" - - - -#define G_TYPE_ARMV7_SHIFT_OPERAND g_armv7_shift_operand_get_type() -#define G_ARMV7_SHIFT_OPERAND(obj) (G_TYPE_CHECK_INSTANCE_CAST((obj), g_armv7_shift_operand_get_type(), GArmV7ShiftOperand)) -#define G_IS_ARMV7_SHIFT_OPERAND(obj) (G_TYPE_CHECK_INSTANCE_TYPE((obj), g_armv7_shift_operand_get_type())) -#define G_ARMV7_SHIFT_OPERAND_CLASS(klass) (G_TYPE_CHECK_CLASS_CAST((klass), G_TYPE_ARMV7_SHIFT_OPERAND, GArmV7ShiftOperandClass)) -#define G_IS_ARMV7_SHIFT_OPERAND_CLASS(klass) (G_TYPE_CHECK_CLASS_TYPE((klass), G_TYPE_ARMV7_SHIFT_OPERAND)) -#define G_ARMV7_SHIFT_OPERAND_GET_CLASS(obj) (G_TYPE_INSTANCE_GET_CLASS((obj), G_TYPE_ARMV7_SHIFT_OPERAND, GArmV7ShiftOperandClass)) - - -/* Définition d'un opérande visant une opérande de décallage ARMv7 (instance) */ -typedef struct _GArmV7ShiftOperand GArmV7ShiftOperand; - -/* Définition d'un opérande visant une opérande de décallage ARMv7 (classe) */ -typedef struct _GArmV7ShiftOperandClass GArmV7ShiftOperandClass; - - -/* Indique le type défini par la GLib pour une opérande de décallage ARMv7. */ -GType g_armv7_shift_operand_get_type(void); - -/* Crée un réceptacle pour opérande de décallage ARMv7. */ -GArchOperand *g_armv7_shift_operand_new(SRType, GArchOperand *); - -/* Indique la forme de décallage représenté. */ -SRType g_armv7_shift_operand_get_shift_type(const GArmV7ShiftOperand *); - -/* Founit la valeur utilisée pour un décallage. */ -GArchOperand *g_armv7_shift_operand_get_shift_value(const GArmV7ShiftOperand *); - - - -#endif /* _ARCH_ARM_V7_OPERANDS_SHIFT_H */ diff --git a/src/arch/arm/v7/post.c b/src/arch/arm/v7/post.c deleted file mode 100644 index 46a1792..0000000 --- a/src/arch/arm/v7/post.c +++ /dev/null @@ -1,99 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * post.c - traitements complémentaires à la phase de désassemblage - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#include "post.h" - - -#include "../../target.h" - - - -/****************************************************************************** -* * -* Paramètres : instr = instruction ARMv7 à traiter. * -* proc = représentation de l'architecture utilisée. * -* context = contexte associé à la phase de désassemblage. * -* format = accès aux données du binaire d'origine. * -* * -* Description : Complète un désassemblage accompli pour une instruction. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -void post_process_ldr_instructions(GArchInstruction *instr, GArchProcessor *proc, GProcContext *context, GExeFormat *format) -{ - GArchOperand *op; /* Opérande numérique en place */ - uint32_t addr; /* Adresse visée par le saut */ - GBinFormat *bfmt; /* Version basique du format */ - GTargetOperand *new; /* Instruction de ciblage */ - vmpa2t target; /* Défination finale précise */ - mrange_t trange; /* Etendue du symbole à créer */ - VMPA_BUFFER(loc); /* Espace pour une conversion */ - char name[5 + VMPA_MAX_LEN]; /* Etiquette à constituer */ - GBinSymbol *symbol; /* Nouveau symbole construit */ - - g_arch_instruction_lock_operands(instr); - - op = _g_arch_instruction_get_operand(instr, 1); - - if (!G_IS_IMM_OPERAND(op)) - goto ppli_release; - - if (g_imm_operand_get_value(G_IMM_OPERAND(op), MDS_32_BITS_UNSIGNED, &addr) - && g_exe_format_translate_address_into_vmpa(format, addr, &target)) - { - bfmt = G_BIN_FORMAT(format); - - new = G_TARGET_OPERAND(g_target_operand_new(MDS_32_BITS_UNSIGNED, &target)); - - if (!g_target_operand_resolve(new, bfmt, true)) - { - addr &= ~0x1; - - init_mrange(&trange, &target, 0); - - vmpa2_virt_to_string(&target, MDS_UNDEFINED, loc, NULL); - snprintf(name, sizeof(name), "loc_%s", loc + 2); - - symbol = g_binary_symbol_new(&trange, STP_CODE_LABEL); - g_binary_symbol_set_alt_label(symbol, name); - g_binary_format_add_symbol(bfmt, symbol); - - g_target_operand_resolve(new, bfmt, true); - - } - - _g_arch_instruction_replace_operand(instr, op, G_ARCH_OPERAND(new)); - - } - - ppli_release: - - g_object_unref(G_OBJECT(op)); - - g_arch_instruction_unlock_operands(instr); - -} diff --git a/src/arch/arm/v7/post.h b/src/arch/arm/v7/post.h deleted file mode 100644 index 89a86a6..0000000 --- a/src/arch/arm/v7/post.h +++ /dev/null @@ -1,57 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * post.h - prototypes pour les traitements complémentaires à la phase de désassemblage - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_ARM_V7_POST_H -#define _ARCH_ARM_V7_POST_H - - -#include "../../instruction.h" -#include "../../post.h" - - - -static inline void post_process_branch_instructions(GArchInstruction *ins, GArchProcessor *proc, GProcContext *ctx, GExeFormat *fmt) -{ - post_process_target_resolution(ins, proc, ctx, fmt, 0, STP_CODE_LABEL); - -} - -static inline void post_process_branch_and_link_instructions(GArchInstruction *ins, GArchProcessor *proc, GProcContext *ctx, GExeFormat *fmt) -{ - post_process_target_resolution(ins, proc, ctx, fmt, 0, STP_ROUTINE); - -} - -static inline void post_process_comp_and_branch_instructions(GArchInstruction *ins, GArchProcessor *proc, GProcContext *ctx, GExeFormat *fmt) -{ - post_process_target_resolution(ins, proc, ctx, fmt, 1, STP_CODE_LABEL); - -} - - -/* Complète un désassemblage accompli pour une instruction. */ -void post_process_ldr_instructions(GArchInstruction *, GArchProcessor *, GProcContext *, GExeFormat *); - - - -#endif /* _ARCH_ARM_V7_POST_H */ diff --git a/src/arch/arm/v7/processor.c b/src/arch/arm/v7/processor.c deleted file mode 100644 index b310652..0000000 --- a/src/arch/arm/v7/processor.c +++ /dev/null @@ -1,295 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * processor.c - manipulation du processeur ARMv7 - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#include "processor.h" - - -#include <assert.h> - - -#include "arm.h" -#include "context.h" -#include "thumb_16.h" -#include "thumb_32.h" -#include "../processor-int.h" -#include "../../raw.h" - - - -/* Définition du processeur ARMv7 (instance) */ -struct _GArmV7Processor -{ - GArmProcessor parent; /* Instance parente */ - -}; - - -/* Définition du processeur ARMv7 (classe) */ -struct _GArmV7ProcessorClass -{ - GArmProcessorClass parent; /* Classe parente */ - -}; - - -/* Initialise la classe des registres ARMv7. */ -static void g_armv7_processor_class_init(GArmV7ProcessorClass *); - -/* Initialise une instance de registre ARMv7. */ -static void g_armv7_processor_init(GArmV7Processor *); - -/* Supprime toutes les références externes. */ -static void g_armv7_processor_dispose(GArmV7Processor *); - -/* Procède à la libération totale de la mémoire. */ -static void g_armv7_processor_finalize(GArmV7Processor *); - -/* Fournit un contexte pour l'exécution du processeur ARM. */ -static GArmV7Context *g_armv7_processor_get_context(const GArmV7Processor *); - -/* Décode une instruction dans un flux de données. */ -static GArchInstruction *g_armv7_processor_disassemble(const GArmV7Processor *, GArmV7Context *, const GBinContent *, vmpa2t *, GExeFormat *); - - - -/* Indique le type défini par la GLib pour le processeur ARMv7. */ -G_DEFINE_TYPE(GArmV7Processor, g_armv7_processor, G_TYPE_ARM_PROCESSOR); - - -/****************************************************************************** -* * -* Paramètres : klass = classe à initialiser. * -* * -* Description : Initialise la classe des processeurs ARMv7. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_processor_class_init(GArmV7ProcessorClass *klass) -{ - GObjectClass *object_class; /* Autre version de la classe */ - GArchProcessorClass *proc; /* Encore une autre vision... */ - - object_class = G_OBJECT_CLASS(klass); - proc = G_ARCH_PROCESSOR_CLASS(klass); - - object_class->dispose = (GObjectFinalizeFunc/* ! */)g_armv7_processor_dispose; - object_class->finalize = (GObjectFinalizeFunc)g_armv7_processor_finalize; - - proc->disassemble = (disass_instr_fc)g_armv7_processor_disassemble; - -} - - -/****************************************************************************** -* * -* Paramètres : proc = instance à initialiser. * -* * -* Description : Initialise une instance de processeur ARMv7. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_processor_init(GArmV7Processor *proc) -{ - - GArchProcessor *parent; /* Instance parente */ - - parent = G_ARCH_PROCESSOR(proc); - - parent->endianness = SRE_LITTLE; - parent->memsize = MDS_32_BITS; - parent->inssize = MDS_32_BITS; - - - - - parent->get_ctx = (get_processor_context_fc)g_armv7_processor_get_context; - - -} - - -/****************************************************************************** -* * -* Paramètres : proc = instance d'objet GLib à traiter. * -* * -* Description : Supprime toutes les références externes. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_processor_dispose(GArmV7Processor *proc) -{ - G_OBJECT_CLASS(g_armv7_processor_parent_class)->dispose(G_OBJECT(proc)); - -} - - -/****************************************************************************** -* * -* Paramètres : proc = instance d'objet GLib à traiter. * -* * -* Description : Procède à la libération totale de la mémoire. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_processor_finalize(GArmV7Processor *proc) -{ - G_OBJECT_CLASS(g_armv7_processor_parent_class)->finalize(G_OBJECT(proc)); - -} - - -/****************************************************************************** -* * -* Paramètres : - * -* * -* Description : Crée le support de l'architecture ARMv7. * -* * -* Retour : Adresse de la structure mise en place. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArmV7Processor *g_armv7_processor_new(void) -{ - GArmV7Processor *result; /* Structure à retourner */ - - result = g_object_new(G_TYPE_ARMV7_PROCESSOR, NULL); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : proc = architecture, spectatrice ici. * -* * -* Description : Fournit un contexte pour l'exécution du processeur Arm. * -* * -* Retour : Contexte mis en place. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArmV7Context *g_armv7_processor_get_context(const GArmV7Processor *proc) -{ - return g_armv7_context_new(); - -} - - -/****************************************************************************** -* * -* Paramètres : proc = architecture visée par la procédure. * -* ctx = contexte lié à l'exécution du processeur. * -* content = flux de données à analyser. * -* pos = position courante dans ce flux. [OUT] * -* format = format du fichier contenant le code. * -* * -* Description : Désassemble une instruction dans un flux de données. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *g_armv7_processor_disassemble(const GArmV7Processor *proc, GArmV7Context *ctx, const GBinContent *content, vmpa2t *pos, GExeFormat *format) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - SourceEndian endian; /* Boutisme des données lues */ - uint16_t raw16; /* Donnée 16 bits à analyser */ - uint32_t raw32; /* Donnée 32 bits à analyser */ - ArmV7InstrSet iset; /* Type de jeu d'instructions */ - - endian = G_ARCH_PROCESSOR(proc)->endianness; - - iset = g_armv7_context_find_encoding(ctx, get_virt_addr(pos)); - - switch (iset) - { - case AV7IS_ARM: - - if (!g_binary_content_read_u32(content, pos, endian, &raw32)) - return NULL; - - result = process_armv7_arm_instruction_set_encoding(raw32); - - break; - - case AV7IS_THUMB: - - if (!g_binary_content_read_u16(content, pos, endian, &raw16)) - return NULL; - - switch (raw16 >> 11) - { - case 0b11101: - case 0b11110: - case 0b11111: - - raw32 = raw16 << 16; - - if (!g_binary_content_read_u16(content, pos, endian, &raw16)) - return NULL; - - raw32 |= raw16; - - result = process_armv7_thumb_32_instruction_set_encoding(raw32); - break; - - default: - result = process_armv7_thumb_16_instruction_set_encoding(raw16); - break; - - } - - break; - - default: - assert(0); - break; - - } - - return result; - -} diff --git a/src/arch/arm/v7/processor.h b/src/arch/arm/v7/processor.h deleted file mode 100644 index 2e0805c..0000000 --- a/src/arch/arm/v7/processor.h +++ /dev/null @@ -1,56 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * processor.h - prototypes pour la manipulation du processeur ARMv7 - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_ARM_V7_PROCESSOR_H -#define _ARCH_ARM_V7_PROCESSOR_H - - -#include <glib-object.h> -#include <stdint.h> - - - -#define G_TYPE_ARMV7_PROCESSOR g_armv7_processor_get_type() -#define G_ARMV7_PROCESSOR(obj) (G_TYPE_CHECK_INSTANCE_CAST((obj), g_armv7_processor_get_type(), GArmV7Processor)) -#define G_IS_ARMV7_PROCESSOR(obj) (G_TYPE_CHECK_INSTANCE_TYPE((obj), g_armv7_processor_get_type())) -#define G_ARMV7_PROCESSOR_CLASS(klass) (G_TYPE_CHECK_CLASS_CAST((klass), G_TYPE_ARMV7_PROCESSOR, GArmV7ProcessorClass)) -#define G_IS_ARMV7_PROCESSOR_CLASS(klass) (G_TYPE_CHECK_CLASS_TYPE((klass), G_TYPE_ARMV7_PROCESSOR)) -#define G_ARMV7_PROCESSOR_GET_CLASS(obj) (G_TYPE_INSTANCE_GET_CLASS((obj), G_TYPE_ARMV7_PROCESSOR, GArmV7ProcessorClass)) - - -/* Définition du processeur ARMv7 (instance) */ -typedef struct _GArmV7Processor GArmV7Processor; - -/* Définition du processeur ARMv7 (classe) */ -typedef struct _GArmV7ProcessorClass GArmV7ProcessorClass; - - -/* Indique le type défini par la GLib pour le processeur ARMv7. */ -GType g_armv7_processor_get_type(void); - -/* Crée le support de l'architecture ARMv7. */ -GArmV7Processor *g_armv7_processor_new(void); - - - -#endif /* _ARCH_ARM_V7_PROCESSOR_H */ diff --git a/src/arch/arm/v7/pseudo.c b/src/arch/arm/v7/pseudo.c deleted file mode 100644 index 8dc4c6e..0000000 --- a/src/arch/arm/v7/pseudo.c +++ /dev/null @@ -1,683 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * pseudo.c - implémentation des pseudo-fonctions de spécification - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#include "pseudo.h" - - -#include <stddef.h> - - -#include "../../../common/bconst.h" - - - -/****************************************************************************** -* * -* Paramètres : x = valeur sur 32 bits maximum à traiter. * -* n = nombre de bits à prendre en compte. * -* shift = nombre de décallages visés. * -* carry = retenue enventuelle à constituer. [OUT] * -* value = nouvelle valeur calculée. [OUT] * -* * -* Description : Traduit la fonction 'LSL_C'. * -* * -* Retour : Bilan de l'opération. * -* * -* Remarques : - * -* * -******************************************************************************/ - -bool armv7_lsl_c(uint32_t x, unsigned int n, unsigned int shift, bool *carry, uint32_t *value) -{ - if (n > 32) return false; - if (shift == 0) return false; - - if (carry != NULL) - *carry = x & (1 << (n - 1)); - - *value = x << shift; - - return true; - -} - - -/****************************************************************************** -* * -* Paramètres : x = valeur sur 32 bits maximum à traiter. * -* n = nombre de bits à prendre en compte. * -* shift = nombre de décallages visés. * -* value = nouvelle valeur calculée. [OUT] * -* * -* Description : Traduit la fonction 'LSL'. * -* * -* Retour : Bilan de l'opération. * -* * -* Remarques : - * -* * -******************************************************************************/ - -bool armv7_lsl(uint32_t x, unsigned int n, unsigned int shift, uint32_t *value) -{ - bool result; /* Bilan final à retourner */ - - if (shift == 0) - result = true; - - else - result = armv7_lsl_c(x, n, shift, NULL, value); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : x = valeur sur 32 bits maximum à traiter. * -* n = nombre de bits à prendre en compte. * -* shift = nombre de décallages visés. * -* carry = retenue enventuelle à constituer. [OUT] * -* value = nouvelle valeur calculée. [OUT] * -* * -* Description : Traduit la fonction 'LSR_C'. * -* * -* Retour : Bilan de l'opération. * -* * -* Remarques : - * -* * -******************************************************************************/ - -bool armv7_lsr_c(uint32_t x, unsigned int n, unsigned int shift, bool *carry, uint32_t *value) -{ - if (n > 32) return false; - if (shift == 0) return false; - - if (carry != NULL) - *carry = x & (1 << (shift - 1)); - - *value = x >> shift; - - return true; - -} - - -/****************************************************************************** -* * -* Paramètres : x = valeur sur 32 bits maximum à traiter. * -* n = nombre de bits à prendre en compte. * -* shift = nombre de décallages visés. * -* value = nouvelle valeur calculée. [OUT] * -* * -* Description : Traduit la fonction 'LSR'. * -* * -* Retour : Bilan de l'opération. * -* * -* Remarques : - * -* * -******************************************************************************/ - -bool armv7_lsr(uint32_t x, unsigned int n, unsigned int shift, uint32_t *value) -{ - bool result; /* Bilan final à retourner */ - - if (shift == 0) - result = x; - - else - result = armv7_lsr_c(x, n, shift, NULL, value); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : x = valeur sur 32 bits maximum à traiter. * -* n = nombre de bits à prendre en compte. * -* shift = nombre de décallages visés. * -* carry = retenue enventuelle à constituer. [OUT] * -* value = nouvelle valeur calculée. [OUT] * -* * -* Description : Traduit la fonction 'ASR_C'. * -* * -* Retour : Bilan de l'opération. * -* * -* Remarques : - * -* * -******************************************************************************/ - -bool armv7_asr_c(uint32_t x, unsigned int n, unsigned int shift, bool *carry, uint32_t *value) -{ - if (n > 32) return false; - if (shift == 0) return false; - - if (carry != NULL) - *carry = x & (1 << (shift - 1)); - - *value = ((int32_t)x) >> shift; - - return true; - -} - - -/****************************************************************************** -* * -* Paramètres : x = valeur sur 32 bits maximum à traiter. * -* n = nombre de bits à prendre en compte. * -* shift = nombre de décallages visés. * -* value = nouvelle valeur calculée. [OUT] * -* * -* Description : Traduit la fonction 'ASR'. * -* * -* Retour : Bilan de l'opération. * -* * -* Remarques : - * -* * -******************************************************************************/ - -bool armv7_asr(uint32_t x, unsigned int n, unsigned int shift, uint32_t *value) -{ - bool result; /* Bilan final à retourner */ - - if (shift == 0) - result = true; - - else - result = armv7_asr_c(x, n, shift, NULL, value); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : x = valeur sur 32 bits maximum à traiter. * -* n = nombre de bits à prendre en compte. * -* shift = nombre de décallages visés. * -* carry = retenue enventuelle à constituer. [OUT] * -* value = nouvelle valeur calculée. [OUT] * -* * -* Description : Traduit la fonction 'ROR_C'. * -* * -* Retour : Bilan de l'opération. * -* * -* Remarques : - * -* * -******************************************************************************/ - -bool armv7_ror_c(uint32_t x, unsigned int n, unsigned int shift, bool *carry, uint32_t *value) -{ - if (n > 32) return false; - if (shift == 0) return false; - - *value = (x >> shift) | (x << (32 - shift)); - - if (carry != NULL) - *carry = *value & (1 << (n - 1)); - - return true; - -} - - -/****************************************************************************** -* * -* Paramètres : x = valeur sur 32 bits maximum à traiter. * -* n = nombre de bits à prendre en compte. * -* shift = nombre de décallages visés. * -* value = nouvelle valeur calculée. [OUT] * -* * -* Description : Traduit la fonction 'ROR'. * -* * -* Retour : Bilan de l'opération. * -* * -* Remarques : - * -* * -******************************************************************************/ - -bool armv7_ror(uint32_t x, unsigned int n, unsigned int shift, uint32_t *value) -{ - bool result; /* Bilan final à retourner */ - - if (shift == 0) - result = true; - - else - result = armv7_ror_c(x, n, shift, NULL, value); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : x = valeur sur 32 bits maximum à traiter. * -* n = nombre de bits à prendre en compte. * -* carry = retenue enventuelle à utiliser puis constituer. [OUT]* -* value = nouvelle valeur calculée. [OUT] * -* * -* Description : Traduit la fonction 'RRX_C'. * -* * -* Retour : Bilan de l'opération. * -* * -* Remarques : - * -* * -******************************************************************************/ - -bool armv7_rrx_c(uint32_t x, unsigned int n, bool *carry, uint32_t *value) -{ - bool new_c; /* Nouvelle retenue à retenir */ - - new_c = x & 0x1; - - *value = (*carry ? 1 : 0) << (n - 1) | x >> 1; - - *carry = new_c; - - return true; - -} - - -/****************************************************************************** -* * -* Paramètres : x = valeur sur 32 bits maximum à traiter. * -* n = nombre de bits à prendre en compte. * -* carry = retenue enventuelle à utiliser. * -* value = nouvelle valeur calculée. [OUT] * -* * -* Description : Traduit la fonction 'RRX'. * -* * -* Retour : Bilan de l'opération. * -* * -* Remarques : - * -* * -******************************************************************************/ - -bool armv7_rrx(uint32_t x, unsigned int n, bool carry, uint32_t *value) -{ - return armv7_rrx_c(x, n, &carry, value); - -} - - -/****************************************************************************** -* * -* Paramètres : imm12 = valeur sur 32 bits maximum à traiter. * -* carry = retenue enventuelle à utiliser / constituer. [OUT] * -* value = nouvelle valeur calculée. [OUT] * -* * -* Description : Traduit la fonction 'ARMExpandImm_C'. * -* * -* Retour : Bilan de l'opération. * -* * -* Remarques : - * -* * -******************************************************************************/ - -bool armv7_arm_expand_imm_c(uint32_t imm12, bool *carry, uint32_t *value) -{ - bool result; /* Bilan final à retourner */ - uint32_t unrotated; /* Transformation à décaller */ - - /** - * Selon les spécifications, x contient toujours 12 bits utiles seulement. - */ - - unrotated = armv7_zero_extend(imm12 & 0xff, 8, 32); - - result = armv7_shift(unrotated, 32, SRType_ROR, 2 * ((imm12 >> 8) & 0xf), carry, value); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : imm12 = valeur sur 32 bits maximum à traiter. * -* carry = retenue enventuelle à utiliser / constituer. [OUT] * -* value = nouvelle valeur calculée. [OUT] * -* * -* Description : Traduit la fonction 'ARMExpandImm'. * -* * -* Retour : Bilan de l'opération. * -* * -* Remarques : - * -* * -******************************************************************************/ - -bool armv7_arm_expand_imm(uint32_t imm12, uint32_t *value) -{ - return armv7_arm_expand_imm_c(imm12, (bool []) { false /* FIXME : APSR.C */ }, value); - -} - - -/****************************************************************************** -* * -* Paramètres : imm12 = valeur sur 32 bits maximum à traiter. * -* carry = retenue enventuelle à utiliser / constituer. [OUT] * -* value = nouvelle valeur calculée. [OUT] * -* * -* Description : Traduit la fonction 'ThumbExpandImm_C'. * -* * -* Retour : Bilan de l'opération. * -* * -* Remarques : - * -* * -******************************************************************************/ - -bool armv7_thumb_expand_imm_c(uint32_t imm12, bool *carry, uint32_t *value) -{ - bool result; /* Conclusion à faire remonter */ - uint8_t byte; /* Octet à reproduire */ - uint32_t unrotated; /* Transformation à décaller */ - - result = true; - - if (((imm12 >> 10) & b11) == b00) - { - byte = imm12 & 0xff; - - switch ((imm12 >> 8) & b11) - { - case b00: - *value = armv7_zero_extend(byte, 8, 32); - break; - - case b01: - if (byte == 0) - result = false; - else - *value = byte << 16 | byte; - break; - - case b10: - if (byte == 0) - result = false; - else - *value = byte << 24 | byte << 8; - break; - - case b11: - if (byte == 0) - result = false; - else - *value = byte << 24 | byte << 16 | byte << 8 | byte; - break; - - } - - } - else - { - unrotated = 1 << 7 | (imm12 & 0x3f); - result = armv7_ror_c(unrotated, 32, (imm12 >> 7) & 0x1f, carry, value); - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : imm12 = valeur sur 32 bits maximum à traiter. * -* carry = retenue enventuelle à utiliser / constituer. [OUT] * -* value = nouvelle valeur calculée. [OUT] * -* * -* Description : Traduit la fonction 'ThumbExpandImm'. * -* * -* Retour : Bilan de l'opération. * -* * -* Remarques : - * -* * -******************************************************************************/ - -bool armv7_thumb_expand_imm(uint32_t imm12, uint32_t *value) -{ - return armv7_thumb_expand_imm_c(imm12, (bool []) { false /* FIXME : APSR.C */ }, value); - -} - - -/****************************************************************************** -* * -* Paramètres : type2 = type de décallage encodé sur 2 bits. * -* imm5 = valeur de décallage entière sur 5 bits. * -* type = type de décallage à constituer. [OUT] * -* value = valeur pleine et entière à utiliser. [OUT] * -* * -* Description : Traduit la fonction 'DecodeImmShift'. * -* * -* Retour : Bilan de l'opération. * -* * -* Remarques : - * -* * -******************************************************************************/ - -bool armv7_decode_imm_shift(uint8_t type2, uint8_t imm5, SRType *type, uint32_t *value) -{ - bool result; /* Bilan à retourner */ - - result = true; - - switch (type2) - { - case b00: - *type = SRType_LSL; - *value = imm5; - break; - - case b01: - *type = SRType_LSR; - *value = (imm5 == 0 ? 32 : imm5); - break; - - case b10: - *type = SRType_ASR; - *value = (imm5 == 0 ? 32 : imm5); - break; - - case b11: - if (imm5 == 0) - { - *type = SRType_RRX; - *value = 1; - } - else - { - *type = SRType_ROR; - *value = imm5; - } - break; - - default: - result = false; - break; - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : type2 = type de décallage encodé sur 2 bits. * -* type = type de décallage à constituer. [OUT] * -* * -* Description : Traduit la fonction 'DecodeRegShift'. * -* * -* Retour : Bilan de l'opération. * -* * -* Remarques : - * -* * -******************************************************************************/ - -bool armv7_decode_reg_shift(uint8_t type2, SRType *type) -{ - bool result; /* Bilan à retourner */ - - result = true; - - switch (type2) - { - case b00: - *type = SRType_LSL; - break; - - case b01: - *type = SRType_LSR; - break; - - case b10: - *type = SRType_ASR; - break; - - case b11: - *type = SRType_ROR; - break; - - default: - result = false; - break; - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : x = valeur sur 32 bits maximum à traiter. * -* n = nombre de bits à prendre en compte. * -* type = type d'opération à mener. * -* amount = quantité liée à l'opération à mener. * -* carry = retenue enventuelle à utiliser / constituer. [OUT] * -* value = nouvelle valeur calculée. [OUT] * -* * -* Description : Traduit la fonction 'Shift_C'. * -* * -* Retour : Bilan de l'opération. * -* * -* Remarques : - * -* * -******************************************************************************/ - -bool armv7_shift_c(uint32_t x, unsigned int n, SRType type, unsigned int amount, bool *carry, uint32_t *value) -{ - bool result; /* Bilan final à retourner */ - - if (type == SRType_RRX && amount != 1) return false; - - if (amount == 0) - { - *value = x; - return true; - } - - result = true; /* Pour GCC... */ - - switch (type) - { - case SRType_LSL: - result = armv7_lsl_c(x, n, amount, carry, value); - break; - - case SRType_LSR: - result = armv7_lsr_c(x, n, amount, carry, value); - break; - - case SRType_ASR: - result = armv7_asr_c(x, n, amount, carry, value); - break; - - case SRType_ROR: - result = armv7_ror_c(x, n, amount, carry, value); - break; - - case SRType_RRX: - result = armv7_rrx_c(x, n, carry, value); - break; - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : x = valeur sur 32 bits maximum à traiter. * -* n = nombre de bits à prendre en compte. * -* type = type d'opération à mener. * -* amount = quantité liée à l'opération à mener. * -* carry = retenue enventuelle à utiliser. * -* value = nouvelle valeur calculée. [OUT] * -* * -* Description : Traduit la fonction 'Shift'. * -* * -* Retour : Bilan de l'opération. * -* * -* Remarques : - * -* * -******************************************************************************/ - -bool armv7_shift(uint32_t x, unsigned int n, SRType type, unsigned int amount, bool carry, uint32_t *value) -{ - return armv7_shift_c(x, n, type, amount, &carry, value); - -} - - -/****************************************************************************** -* * -* Paramètres : x = valeur sur 32 bits maximum à traiter. * -* n = nombre de bits à prendre en compte. * -* i = taille finale à obtenir. * -* * -* Description : Traduit la fonction 'ZeroExtend'. * -* * -* Retour : Nouvelle valeur calculée. * -* * -* Remarques : - * -* * -******************************************************************************/ - -uint32_t armv7_zero_extend(uint32_t x, unsigned int n, unsigned int i) -{ - return x; - -} diff --git a/src/arch/arm/v7/pseudo.h b/src/arch/arm/v7/pseudo.h deleted file mode 100644 index 48d73b8..0000000 --- a/src/arch/arm/v7/pseudo.h +++ /dev/null @@ -1,136 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * pseudo.h - prototypes pour l'implémentation des pseudo-fonctions de spécification - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_ARM_V7_PSEUDO_H -#define _ARCH_ARM_V7_PSEUDO_H - - -#include <stdbool.h> -#include <stdint.h> - - - -/** - * § A2.2.1 - Integer arithmetic - */ - - -/* Traduit la fonction 'LSL_C'. */ -bool armv7_lsl_c(uint32_t, unsigned int, unsigned int, bool *, uint32_t *); - -/* Traduit la fonction 'LSL'. */ -bool armv7_lsl(uint32_t, unsigned int, unsigned int, uint32_t *); - -/* Traduit la fonction 'LSR_C'. */ -bool armv7_lsr_c(uint32_t, unsigned int, unsigned int, bool *, uint32_t *); - -/* Traduit la fonction 'LSR'. */ -bool armv7_lsr(uint32_t, unsigned int, unsigned int, uint32_t *); - -/* Traduit la fonction 'ASR_C'. */ -bool armv7_asr_c(uint32_t, unsigned int, unsigned int, bool *, uint32_t *); - -/* Traduit la fonction 'ASR'. */ -bool armv7_asr(uint32_t, unsigned int, unsigned int, uint32_t *); - -/* Traduit la fonction 'ROR_C'. */ -bool armv7_ror_c(uint32_t, unsigned int, unsigned int, bool *, uint32_t *); - -/* Traduit la fonction 'ROR'. */ -bool armv7_ror(uint32_t, unsigned int, unsigned int, uint32_t *); - -/* Traduit la fonction 'RRX_C'. */ -bool armv7_rrx_c(uint32_t, unsigned int, bool *, uint32_t *); - -/* Traduit la fonction 'RRX'. */ -bool armv7_rrx(uint32_t, unsigned int, bool, uint32_t *); - - - -/** - * § A5.2.4 - Modified immediate constants in ARM instructions - */ - - -/* Traduit la fonction 'ARMExpandImm_C'. */ -bool armv7_arm_expand_imm_c(uint32_t, bool *, uint32_t *); - -/* Traduit la fonction 'ARMExpandImm'. */ -bool armv7_arm_expand_imm(uint32_t, uint32_t *); - - - -/** - * § A6.3.2 - Modified immediate constants in Thumb instructions - */ - - -/* Traduit la fonction 'ThumbExpandImm_C'. */ -bool armv7_thumb_expand_imm_c(uint32_t, bool *, uint32_t *); - -/* Traduit la fonction 'ThumbExpandImm'. */ -bool armv7_thumb_expand_imm(uint32_t, uint32_t *); - - - -/** - * § A8.4.3 - Pseudocode details of instruction-specified shifts and rotates - */ - - -typedef enum _SRType -{ - SRType_LSL, - SRType_LSR, - SRType_ASR, - SRType_ROR, - SRType_RRX - -} SRType; - - -/* Traduit la fonction 'DecodeImmShift'. */ -bool armv7_decode_imm_shift(uint8_t, uint8_t, SRType *, uint32_t *); - -/* Traduit la fonction 'DecodeRegShift'. */ -bool armv7_decode_reg_shift(uint8_t, SRType *); - -/* Traduit la fonction 'Shift_C'. */ -bool armv7_shift_c(uint32_t, unsigned int, SRType, unsigned int, bool *, uint32_t *); - -/* Traduit la fonction 'Shift'. */ -bool armv7_shift(uint32_t, unsigned int, SRType, unsigned int, bool, uint32_t *); - - - -/** - * § P.5.3 - Bitstring manipulation - */ - - -/* Traduit la fonction 'ZeroExtend'. */ -uint32_t armv7_zero_extend(uint32_t, unsigned int, unsigned int); - - - -#endif /* _ARCH_ARM_V7_PSEUDO_H */ diff --git a/src/arch/arm/v7/register.c b/src/arch/arm/v7/register.c deleted file mode 100644 index 3cd9e0f..0000000 --- a/src/arch/arm/v7/register.c +++ /dev/null @@ -1,229 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * registers.c - aides auxiliaires relatives aux registres ARMv7 - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#include "register.h" - - -#include <stdio.h> - - -#include "../register-int.h" - - - -/* Représentation d'un registre ARMv7 (instance) */ -struct _GArmV7Register -{ - GArmRegister parent; /* Instance parente */ - -}; - - -/* Représentation d'un registre ARMv7 (classe) */ -struct _GArmV7RegisterClass -{ - GArmRegisterClass parent; /* Classe parente */ - -}; - - -#define MAX_REGNAME_LEN 8 - - -/* Initialise la classe des registres ARMv7. */ -static void g_armv7_register_class_init(GArmV7RegisterClass *); - -/* Initialise une instance de registre ARMv7. */ -static void g_armv7_register_init(GArmV7Register *); - -/* Supprime toutes les références externes. */ -static void g_armv7_register_dispose(GArmV7Register *); - -/* Procède à la libération totale de la mémoire. */ -static void g_armv7_register_finalize(GArmV7Register *); - -/* Traduit un registre en version humainement lisible. */ -static void g_armv7_register_print(const GArmV7Register *, GBufferLine *, AsmSyntax); - - - -/* Indique le type défini pour une représentation d'un registre ARMv7. */ -G_DEFINE_TYPE(GArmV7Register, g_armv7_register, G_TYPE_ARM_REGISTER); - - -/****************************************************************************** -* * -* Paramètres : klass = classe à initialiser. * -* * -* Description : Initialise la classe des registres ARMv7. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_register_class_init(GArmV7RegisterClass *klass) -{ - GObjectClass *object_class; /* Autre version de la classe */ - GArchRegisterClass *reg_class; /* Classe de haut niveau */ - - object_class = G_OBJECT_CLASS(klass); - reg_class = G_ARCH_REGISTER_CLASS(klass); - - object_class->dispose = (GObjectFinalizeFunc/* ! */)g_armv7_register_dispose; - object_class->finalize = (GObjectFinalizeFunc)g_armv7_register_finalize; - - reg_class->print = (reg_print_fc)g_armv7_register_print; - -} - - -/****************************************************************************** -* * -* Paramètres : reg = instance à initialiser. * -* * -* Description : Initialise une instance de registre ARMv7. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_register_init(GArmV7Register *reg) -{ - -} - - -/****************************************************************************** -* * -* Paramètres : reg = instance d'objet GLib à traiter. * -* * -* Description : Supprime toutes les références externes. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_register_dispose(GArmV7Register *reg) -{ - G_OBJECT_CLASS(g_armv7_register_parent_class)->dispose(G_OBJECT(reg)); - -} - - -/****************************************************************************** -* * -* Paramètres : reg = instance d'objet GLib à traiter. * -* * -* Description : Procède à la libération totale de la mémoire. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_register_finalize(GArmV7Register *reg) -{ - G_OBJECT_CLASS(g_armv7_register_parent_class)->finalize(G_OBJECT(reg)); - -} - - -/****************************************************************************** -* * -* Paramètres : reg = registre à transcrire. * -* line = ligne tampon où imprimer l'opérande donné. * -* syntax = type de représentation demandée. * -* * -* Description : Traduit un registre en version humainement lisible. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void g_armv7_register_print(const GArmV7Register *reg, GBufferLine *line, AsmSyntax syntax) -{ - char key[MAX_REGNAME_LEN]; /* Mot clef principal */ - size_t klen; /* Taille de ce mot clef */ - - switch (G_ARM_REGISTER(reg)->index) - { - case 0 ... 12: - klen = snprintf(key, MAX_REGNAME_LEN, "r%hhu", G_ARM_REGISTER(reg)->index); - break; - case 13: - klen = snprintf(key, MAX_REGNAME_LEN, "sp"); - break; - case 14: - klen = snprintf(key, MAX_REGNAME_LEN, "lr"); - break; - case 15: - klen = snprintf(key, MAX_REGNAME_LEN, "pc"); - break; - case 16: - klen = snprintf(key, MAX_REGNAME_LEN, "cpsr"); - break; - case 17: - klen = snprintf(key, MAX_REGNAME_LEN, "spsr"); - break; - default: - klen = snprintf(key, MAX_REGNAME_LEN, "r??"); - break; - } - - g_buffer_line_append_text(line, BLC_ASSEMBLY, key, klen, RTT_REGISTER, NULL); - -} - - -/****************************************************************************** -* * -* Paramètres : index = indice du registre correspondant. * -* * -* Description : Crée une réprésentation de registre ARMv7. * -* * -* Retour : Adresse de la structure mise en place. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArmV7Register *g_armv7_register_new(uint8_t index) -{ - GArmV7Register *result; /* Structure à retourner */ - - result = g_object_new(G_TYPE_ARMV7_REGISTER, NULL); - - G_ARM_REGISTER(result)->index = index; - - return result; - -} diff --git a/src/arch/arm/v7/register.h b/src/arch/arm/v7/register.h deleted file mode 100644 index d0a89f2..0000000 --- a/src/arch/arm/v7/register.h +++ /dev/null @@ -1,57 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * registers.h - prototypes pour les aides auxiliaires relatives aux registres ARMv7 - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_ARM_V7_REGISTER_H -#define _ARCH_ARM_V7_REGISTER_H - - -#include <glib-object.h> -#include <stdbool.h> -#include <stdint.h> - - - -#define G_TYPE_ARMV7_REGISTER g_armv7_register_get_type() -#define G_ARMV7_REGISTER(obj) (G_TYPE_CHECK_INSTANCE_CAST((obj), g_armv7_register_get_type(), GArmV7Register)) -#define G_IS_ARMV7_REGISTER(obj) (G_TYPE_CHECK_INSTANCE_TYPE((obj), g_armv7_register_get_type())) -#define G_ARMV7_REGISTER_CLASS(klass) (G_TYPE_CHECK_CLASS_CAST((klass), G_TYPE_ARMV7_REGISTER, GArmV7RegisterClass)) -#define G_IS_ARMV7_REGISTER_CLASS(klass) (G_TYPE_CHECK_CLASS_TYPE((klass), G_TYPE_ARMV7_REGISTER)) -#define G_ARMV7_REGISTER_GET_CLASS(obj) (G_TYPE_INSTANCE_GET_CLASS((obj), G_TYPE_ARMV7_REGISTER, GArmV7RegisterClass)) - - -/* Représentation d'un registre ARMv7 (instance) */ -typedef struct _GArmV7Register GArmV7Register; - -/* Représentation d'un registre ARMv7 (classe) */ -typedef struct _GArmV7RegisterClass GArmV7RegisterClass; - - -/* Indique le type défini pour une représentation d'un registre ARMv7. */ -GType g_armv7_register_get_type(void); - -/* Crée une réprésentation de registre ARMv7. */ -GArmV7Register *g_armv7_register_new(uint8_t); - - - -#endif /* _ARCH_ARM_V7_REGISTER_H */ diff --git a/src/arch/arm/v7/simd.c b/src/arch/arm/v7/simd.c deleted file mode 100644 index c722757..0000000 --- a/src/arch/arm/v7/simd.c +++ /dev/null @@ -1,1539 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * simd.c - désassemblage des instructions ARMv7 SIMD - * - * Copyright (C) 2016-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#include "simd.h" - - -#include <stdint.h> - - -//#include "opcodes/simd_opcodes.h" -#include "opcodes/opcodes_tmp_simd.h" -#include "../../undefined.h" -#include "../../../common/bconst.h" - - - -/* Désassemble une instruction ARMv7 liées au chapitre A7.4.1. */ -static GArchInstruction *process_armv7_simd_three_registers_of_the_same_length(uint32_t, bool); - -/* Désassemble une instruction ARMv7 liées au chapitre A7.4.2. */ -static GArchInstruction *process_armv7_simd_three_registers_of_different_lengths(uint32_t, bool); - -/* Désassemble une instruction ARMv7 liées au chapitre A7.4.3. */ -static GArchInstruction *process_armv7_simd_two_registers_and_a_scalar(uint32_t, bool); - -/* Désassemble une instruction ARMv7 liées au chapitre A7.4.4. */ -static GArchInstruction *process_armv7_simd_two_registers_and_a_shift_amount(uint32_t, bool); - -/* Désassemble une instruction ARMv7 liées au chapitre A7.4.5. */ -static GArchInstruction *process_armv7_simd_two_registers_miscellaneous(uint32_t, bool); - -/* Désassemble une instruction ARMv7 liées au chapitre A7.4.6. */ -static GArchInstruction *process_armv7_simd_one_register_and_a_modified_immediate_value(uint32_t, bool); - - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 16 bits à désassembler. * -* arm = précise si l'encodage est en mode ARM ou Thumb. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A7.4. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArchInstruction *process_armv7_simd_advanced_simd_data_processing_instructions(uint32_t raw, bool arm) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t u; /* Champ 'u' à retrouver */ - uint32_t a; /* Champ 'a' à retrouver */ - uint32_t b; /* Champ 'b' à retrouver */ - uint32_t c; /* Champ 'c' à retrouver */ - - /** - * Suit les directives de : - * § A7.4 Advanced SIMD data-processing instructions - */ - - if (arm) - { - if ((raw & 0xfe000000) != 0xf2000000) return NULL; - } - else - { - if ((raw & 0xef000000) != 0xef000000) return NULL; - } - - result = NULL; - - if (arm) - { - u = (raw >> 24) & b1; - a = (raw >> 19) & b11111; - b = (raw >> 8) & b1111; - c = (raw >> 4) & b1111; - } - else - { - u = (raw >> 28) & b1; - a = (raw >> 19) & b11111; - b = (raw >> 8) & b1111; - c = (raw >> 4) & b1111; - } - - if ((a & b10000) == b00000) - result = process_armv7_simd_three_registers_of_the_same_length(raw, arm); - - else if ((a & b10111) == b10000 && (c & b1001) == b0001) - result = process_armv7_simd_one_register_and_a_modified_immediate_value(raw, arm); - - else if ((a & b10111) == b10001 && (c & b1001) == b0001) - result = process_armv7_simd_two_registers_and_a_shift_amount(raw, arm); - - else if ((a & b10110) == b10010 && (c & b1001) == b0001) - result = process_armv7_simd_two_registers_and_a_shift_amount(raw, arm); - - else if ((a & b10100) == b10100 && (c & b1001) == b0001) - result = process_armv7_simd_two_registers_and_a_shift_amount(raw, arm); - - else if ((a & b10000) == b10000 && (c & b1001) == b1001) - result = process_armv7_simd_two_registers_and_a_shift_amount(raw, arm); - - else if ((a & b10100) == b10000 && (c & b0101) == b0000) - result = process_armv7_simd_three_registers_of_different_lengths(raw, arm); - - else if ((a & b10110) == b10100 && (c & b0101) == b0000) - result = process_armv7_simd_three_registers_of_different_lengths(raw, arm); - - else if ((a & b10100) == b10000 && (c & b0101) == b0100) - result = process_armv7_simd_two_registers_and_a_scalar(raw, arm); - - else if ((a & b10110) == b10100 && (c & b0101) == b0100) - result = process_armv7_simd_two_registers_and_a_scalar(raw, arm); - - else if (u == b0 && (a & b10110) == b10110 && (c & b0001) == b0000) - result = armv7_read_simd_instr_vext(raw, arm); - - else if (u == b1 && (a & b10110) == b10110) - { - if ((b & b1000) == b0000 && (c & b0001) == b0000) - result = process_armv7_simd_two_registers_miscellaneous(raw, arm); - - else if ((b & b1100) == b1000 && (c & b0001) == b0000) - result = armv7_read_simd_instr_vtbl_vtbx(raw, arm); - - else if (b == b1100 && (c & b1001) == b0000) - result = armv7_read_simd_instr_vdup_scalar(raw, arm); - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 16 bits à désassembler. * -* arm = précise si l'encodage est en mode ARM ou Thumb. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A7.4.1. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_simd_three_registers_of_the_same_length(uint32_t raw, bool arm) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t u; /* Champ 'u' à retrouver */ - uint32_t c; /* Champ 'c' à retrouver */ - uint32_t a; /* Champ 'a' à retrouver */ - uint32_t b; /* Champ 'b' à retrouver */ - - /** - * Suit les directives de : - * § A7.4.1 Three registers of the same length - */ - - if (arm) - { - if ((raw & 0xfe800000) != 0xf2000000) return NULL; - } - else - { - if ((raw & 0xef800000) != 0xef000000) return NULL; - } - - result = NULL; - - if (arm) - { - u = (raw >> 24) & b1; - c = (raw >> 20) & b11; - a = (raw >> 8) & b1111; - b = (raw >> 4) & b1; - } - else - { - u = (raw >> 28) & b1; - c = (raw >> 20) & b11; - a = (raw >> 8) & b1111; - b = (raw >> 4) & b1; - } - - if (a == b0000) - { - if (b == b0) - result = armv7_read_simd_instr_vhadd_vhsub(raw, arm); - - else/* if (b == b1)*/ - result = armv7_read_simd_instr_vqadd(raw, arm); - - } - - else if (a == b0001) - { - if (b == b0) - result = armv7_read_simd_instr_vrhadd(raw, arm); - - else/* if (b == b1)*/ - { - if (u == b0) - switch (c) - { - case b00: - result = armv7_read_simd_instr_vand_register(raw, arm); - break; - - case b01: - result = armv7_read_simd_instr_vbic_register(raw, arm); - break; - - case b10: - /* Cf. vmov_register aussi */ - result = armv7_read_simd_instr_vorr_register(raw, arm); - break; - - case b11: - result = armv7_read_simd_instr_vorn_register(raw, arm); - break; - - } - - else/* if (u == b1)*/ - switch (c) - { - case b00: - result = armv7_read_simd_instr_veor(raw, arm); - break; - - case b01: - result = armv7_read_simd_instr_vbif_vbit_vbsl(raw, arm); - break; - - case b10: - result = armv7_read_simd_instr_vbif_vbit_vbsl(raw, arm); - break; - - case b11: - result = armv7_read_simd_instr_vbif_vbit_vbsl(raw, arm); - break; - - } - - } - - } - - else if (a == b0010) - { - if (b == b0) - result = armv7_read_simd_instr_vhadd_vhsub(raw, arm); - - else/* if (b == b1)*/ - result = armv7_read_simd_instr_vqsub(raw, arm); - - } - - else if (a == b0011) - { - if (b == b0) - result = armv7_read_simd_instr_vcgt_register(raw, arm); - - else/* if (b == b1)*/ - result = armv7_read_simd_instr_vcge_register(raw, arm); - - } - - else if (a == b0100) - { - if (b == b0) - result = armv7_read_simd_instr_vshl_register(raw, arm); - - else/* if (b == b1)*/ - result = armv7_read_simd_instr_vqshl_register(raw, arm); - - } - - else if (a == b0101) - { - if (b == b0) - result = armv7_read_simd_instr_vrshl(raw, arm); - - else/* if (b == b1)*/ - result = armv7_read_simd_instr_vqrshl(raw, arm); - - } - - else if (a == b0110) - result = armv7_read_simd_instr_vmax_vmin_integer(raw, arm); - - else if (a == b0111) - { - if (b == b0) - result = armv7_read_simd_instr_vabd_vabdl_integer(raw, arm); - - else/* if (b == b1)*/ - result = armv7_read_simd_instr_vaba_vabal(raw, arm); - - } - - else if (a == b1000) - { - if (b == b0) - { - if (u == b0) - result = armv7_read_simd_instr_vadd_integer(raw, arm); - - else/* if (u == b1)*/ - result = armv7_read_simd_instr_vsub_integer(raw, arm); - - } - - else/* if (b == b1)*/ - { - if (u == b0) - result = armv7_read_simd_instr_vtst(raw, arm); - - else/* if (u == b1)*/ - result = armv7_read_simd_instr_vceq_register(raw, arm); - - } - - } - - else if (a == b1001) - { - if (b == b0) - result = armv7_read_simd_instr_vmla_vmlal_vmls_vmlsl_integer(raw, arm); - - else/* if (b == b1)*/ - result = armv7_read_simd_instr_vmul_vmull_integer_and_polynomial(raw, arm); - - } - - else if (a == b1010) - result = armv7_read_simd_instr_vpmax_vpmin_integer(raw, arm); - - else if (a == b1011) - { - if (b == b0) - { - if (u == b0) - result = armv7_read_simd_instr_vqdmulh(raw, arm); - - else/* if (u == b1)*/ - result = armv7_read_simd_instr_vqrdmulh(raw, arm); - - } - - else/* if (b == b1)*/ - { - if (u == b0) - result = armv7_read_simd_instr_vpadd_integer(raw, arm); - - } - - } - - else if (a == b1100) - { - if (b == b1 && u == b0) - result = armv7_read_simd_instr_vfma_vfms(raw, arm); - - } - - else if (a == b1101) - { - if (b == b0) - { - if (u == b0) - { - if ((c & b10) == b00) - result = armv7_read_simd_instr_vadd_floating_point(raw, arm); - - else/* if ((c & b10) == b10)*/ - result = armv7_read_simd_instr_vsub_floating_point(raw, arm); - - } - - else/* if (u == b1)*/ - { - if ((c & b10) == b00) - result = armv7_read_simd_instr_vpadd_floating_point(raw, arm); - - else/* if ((c & b10) == b10)*/ - result = armv7_read_simd_instr_vabd_floating_point(raw, arm); - - } - - } - - else/* if (b == b1)*/ - { - if (u == b0) - result = armv7_read_simd_instr_vmla_vmls_floating_point(raw, arm); - - else/* if (u == b1)*/ - { - if ((c & b10) == b00) - result = armv7_read_simd_instr_vmul_floating_point(raw, arm); - - } - - } - - } - - else if (a == b1110) - { - if (b == b0) - { - if (u == b0) - { - if ((c & b10) == b00) - result = armv7_read_simd_instr_vceq_register(raw, arm); - - } - - else/* if (u == b1)*/ - { - if ((c & b10) == b00) - result = armv7_read_simd_instr_vcge_register(raw, arm); - - else/* if ((c & b10) == b10)*/ - result = armv7_read_simd_instr_vcgt_register(raw, arm); - - } - - } - - else/* if (b == b1)*/ - { - if (u == b1) - result = armv7_read_simd_instr_vacge_vacgt_vacle_vaclt(raw, arm); - - } - - } - - else if (a == b1111) - { - if (b == b0) - { - if (u == b0) - result = armv7_read_simd_instr_vmax_vmin_floating_point(raw, arm); - - else/* if (u == b1)*/ - result = armv7_read_simd_instr_vpmax_vpmin_floating_point(raw, arm); - - } - - else/* if (b == b1)*/ - { - if (u == b0) - { - if ((c & b10) == b00) - result = armv7_read_simd_instr_vrecps(raw, arm); - - else/* if ((c & b10) == b10)*/ - result = armv7_read_simd_instr_vrsqrts(raw, arm); - - } - - } - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 16 bits à désassembler. * -* arm = précise si l'encodage est en mode ARM ou Thumb. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A7.4.2. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_simd_three_registers_of_different_lengths(uint32_t raw, bool arm) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t u; /* Champ 'u' à retrouver */ - uint32_t a; /* Champ 'a' à retrouver */ - - /** - * Suit les directives de : - * § A7.4.2 Three registers of different lengths - */ - - if (arm) - { - if ((raw & 0xfe800050) != 0xf2800000) return NULL; - } - else - { - if ((raw & 0xef800050) != 0xef800000) return NULL; - } - - result = NULL; - - if (arm) - { - u = (raw >> 24) & b1; - a = (raw >> 8) & b1111; - } - else - { - u = (raw >> 28) & b1; - a = (raw >> 8) & b1111; - } - - if ((a & b1110) == b0000) - result = armv7_read_simd_instr_vaddl_vaddw(raw, arm); - - else if ((a & b1110) == b0010) - result = armv7_read_simd_instr_vsubl_vsubw(raw, arm); - - else if (a == b0100) - { - if (u == b0) - result = armv7_read_simd_instr_vaddhn(raw, arm); - - else/* if (u == b1)*/ - result = armv7_read_simd_instr_vraddhn(raw, arm); - - } - - else if (a == b0101) - result = armv7_read_simd_instr_vaba_vabal(raw, arm); - - else if (a == b0110) - { - if (u == b0) - result = armv7_read_simd_instr_vsubhn(raw, arm); - - else/* if (u == b1)*/ - result = armv7_read_simd_instr_vrsubhn(raw, arm); - - } - - else if (a == b0111) - result = armv7_read_simd_instr_vabd_vabdl_integer(raw, arm); - - else if ((a & b1101) == b1000) - result = armv7_read_simd_instr_vmla_vmlal_vmls_vmlsl_integer(raw, arm); - - else if ((a & b1101) == b1001) - { - if (u == b0) - result = armv7_read_simd_instr_vqdmlal_vqdmlsl(raw, arm); - - } - - else if (a == b1100) - result = armv7_read_simd_instr_vmul_vmull_integer_and_polynomial(raw, arm); - - else if (a == b1101) - { - if (u == b0) - result = armv7_read_simd_instr_vqdmull(raw, arm); - - } - - else if (a == b1110) - result = armv7_read_simd_instr_vmul_vmull_integer_and_polynomial(raw, arm); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 16 bits à désassembler. * -* arm = précise si l'encodage est en mode ARM ou Thumb. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A7.4.3. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_simd_two_registers_and_a_scalar(uint32_t raw, bool arm) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t u; /* Champ 'u' à retrouver */ - uint32_t a; /* Champ 'a' à retrouver */ - - /** - * Suit les directives de : - * § A7.4.3 Two registers and a scalar - */ - - if (arm) - { - if ((raw & 0xfe800050) != 0xf2800040) return NULL; - } - else - { - if ((raw & 0xef800050) != 0xef800040) return NULL; - } - - result = NULL; - - if (arm) - { - u = (raw >> 24) & b1; - a = (raw >> 8) & b1111; - } - else - { - u = (raw >> 28) & b1; - a = (raw >> 8) & b1111; - } - - if ((a & b1010) == b0000) - result = armv7_read_simd_instr_vmla_vmlal_vmls_vmlsl_by_scalar(raw, arm); - - else if ((a & b1010) == b0010) - result = armv7_read_simd_instr_vmla_vmlal_vmls_vmlsl_by_scalar(raw, arm); - - else if ((a & b1011) == b0011 && u == b0) - result = armv7_read_simd_instr_vqdmlal_vqdmlsl(raw, arm); - - else if ((a & b1110) == b1000) - result = armv7_read_simd_instr_vmul_vmull_by_scalar(raw, arm); - - else if (a == b1010) - result = armv7_read_simd_instr_vmul_vmull_by_scalar(raw, arm); - - else if (a == b1011 && u == b0) - result = armv7_read_simd_instr_vqdmull(raw, arm); - - else if (a == b1100) - result = armv7_read_simd_instr_vqdmulh(raw, arm); - - else if (a == b1101) - result = armv7_read_simd_instr_vqrdmulh(raw, arm); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 16 bits à désassembler. * -* arm = précise si l'encodage est en mode ARM ou Thumb. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A7.4.4. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_simd_two_registers_and_a_shift_amount(uint32_t raw, bool arm) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t u; /* Champ 'u' à retrouver */ - uint32_t a; /* Champ 'a' à retrouver */ - uint32_t l; /* Champ 'l' à retrouver */ - uint32_t b; /* Champ 'b' à retrouver */ - - /** - * Suit les directives de : - * § A7.4.4 Two registers and a shift amount - */ - - if (arm) - { - if ((raw & 0xfe800010) != 0xf2800010) return NULL; - } - else - { - if ((raw & 0xef800010) != 0xef800010) return NULL; - } - - result = NULL; - - if (arm) - { - u = (raw >> 24) & b1; - a = (raw >> 8) & b1111; - l = (raw >> 7) & b1; - b = (raw >> 6) & b1; - } - else - { - u = (raw >> 28) & b1; - a = (raw >> 8) & b1111; - l = (raw >> 7) & b1; - b = (raw >> 6) & b1; - } - - if (a == b0000) - result = armv7_read_simd_instr_vshr(raw, arm); - - else if (a == b0001) - result = armv7_read_simd_instr_vsra(raw, arm); - - else if (a == b0010) - result = armv7_read_simd_instr_vrshr(raw, arm); - - else if (a == b0011) - result = armv7_read_simd_instr_vrsra(raw, arm); - - else if (a == b0100 && u == b1) - result = armv7_read_simd_instr_vsri(raw, arm); - - else if (a == b0101) - { - if (u == b0) - result = armv7_read_simd_instr_vshl_immediate(raw, arm); - - else/* if (u == b1)*/ - result = armv7_read_simd_instr_vsli(raw, arm); - - } - - else if ((a & b1110) == b0110) - result = armv7_read_simd_instr_vqshl_vqshlu_immediate(raw, arm); - - else if (a == b1000) - { - if (u == b0) - { - if (b == b0 && l == b0) - result = armv7_read_simd_instr_vshrn(raw, arm); - - else if (b == b1 && l == b0) - result = armv7_read_simd_instr_vrshrn(raw, arm); - - } - else/* if (u == b1)*/ - { - if (b == b0 && l == b0) - result = armv7_read_simd_instr_vqshrn_vqshrun(raw, arm); - - else if (b == b1 && l == b0) - result = armv7_read_simd_instr_vqrshrn_vqrshrun(raw, arm); - - } - - } - - else if (a == b1001) - { - if (b == b0 && l == b0) - result = armv7_read_simd_instr_vqshrn_vqshrun(raw, arm); - - else if (b == b1 && l == b0) - result = armv7_read_simd_instr_vqrshrn_vqrshrun(raw, arm); - - } - - else if (a == b1010 && b == b0 && l == b0) - { - result = armv7_read_simd_instr_vshll(raw, arm); - - /* ??? */ - if (result == NULL) - result = armv7_read_simd_instr_vmovl(raw, arm); - - } - - else if ((a & b1110) == b1110 && l == b0) - result = armv7_read_simd_instr_vcvt_between_floating_point_and_fixed_point_advanced_simd(raw, arm); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 16 bits à désassembler. * -* arm = précise si l'encodage est en mode ARM ou Thumb. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A7.4.5. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_simd_two_registers_miscellaneous(uint32_t raw, bool arm) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t a; /* Champ 'a' à retrouver */ - uint32_t b; /* Champ 'b' à retrouver */ - - /** - * Suit les directives de : - * § A7.4.5 Two registers, miscellaneous - */ - - if (arm) - { - if ((raw & 0xffb00810) != 0xf3b00000) return NULL; - } - else - { - if ((raw & 0xffb00810) != 0xffb00000) return NULL; - } - - result = NULL; - - a = (raw >> 16) & b11; - b = (raw >> 6) & b11111; - - if (a == b00) - { - if ((b & b11110) == b00000) - result = armv7_read_simd_instr_vrev16_vrev32_vrev64(raw, arm); - - else if ((b & b11110) == b00010) - result = armv7_read_simd_instr_vrev16_vrev32_vrev64(raw, arm); - - else if ((b & b11110) == b00100) - result = armv7_read_simd_instr_vrev16_vrev32_vrev64(raw, arm); - - else if ((b & b11100) == b01000) - result = armv7_read_simd_instr_vpaddl(raw, arm); - - else if ((b & b11110) == b10000) - result = armv7_read_simd_instr_vcls(raw, arm); - - else if ((b & b11110) == b10010) - result = armv7_read_simd_instr_vclz(raw, arm); - - else if ((b & b11110) == b10100) - result = armv7_read_simd_instr_vcnt(raw, arm); - - else if ((b & b11110) == b10110) - result = armv7_read_simd_instr_vmvn_register(raw, arm); - - else if ((b & b11100) == b11000) - result = armv7_read_simd_instr_vpadal(raw, arm); - - else if ((b & b11110) == b11100) - result = armv7_read_simd_instr_vqabs(raw, arm); - - else if ((b & b11110) == b11110) - result = armv7_read_simd_instr_vqneg(raw, arm); - - } - - else if (a == b01) - { - if ((b & b01110) == b00000) - result = armv7_read_simd_instr_vcgt_immediate_0(raw, arm); - - else if ((b & b01110) == b00010) - result = armv7_read_simd_instr_vcge_immediate_0(raw, arm); - - else if ((b & b01110) == b00100) - result = armv7_read_simd_instr_vceq_immediate_0(raw, arm); - - else if ((b & b01110) == b00110) - result = armv7_read_simd_instr_vcle_immediate_0(raw, arm); - - else if ((b & b01110) == b01000) - result = armv7_read_simd_instr_vclt_immediate_0(raw, arm); - - else if ((b & b01110) == b01100) - result = armv7_read_simd_instr_vabs(raw, arm); - - else if ((b & b01110) == b01110) - result = armv7_read_simd_instr_vneg(raw, arm); - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 16 bits à désassembler. * -* arm = précise si l'encodage est en mode ARM ou Thumb. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A7.4.6. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_simd_one_register_and_a_modified_immediate_value(uint32_t raw, bool arm) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t cmode; /* Champ 'cmode' à retrouver */ - uint32_t op; /* Champ 'op' à retrouver */ - - /** - * Suit les directives de : - * § A7.4.6 One register and a modified immediate value - */ - - if (arm) - { - if ((raw & 0xfeb80090) != 0xf2800010) return NULL; - } - else - { - if ((raw & 0xefb80090) != 0xef800010) return NULL; - } - - result = NULL; - - cmode = (raw >> 8) & b1111; - op = (raw >> 5) & b1; - - if (op == b0) - { - if ((cmode & b1001) == b0000) - result = armv7_read_simd_instr_vmov_immediate(raw, arm); - - else if ((cmode & b1001) == b0001) - result = armv7_read_simd_instr_vorr_immediate(raw, arm); - - else if ((cmode & b1101) == b1000) - result = armv7_read_simd_instr_vmov_immediate(raw, arm); - - else if ((cmode & b1101) == b1001) - result = armv7_read_simd_instr_vorr_immediate(raw, arm); - - else if ((cmode & b1100) == b1100) - result = armv7_read_simd_instr_vmov_immediate(raw, arm); - - } - - else/* if (op == b1)*/ - { - if ((cmode & b1001) == b0000) - result = armv7_read_simd_instr_vmvn_immediate(raw, arm); - - else if ((cmode & b1001) == b0001) - result = armv7_read_simd_instr_vbic_immediate(raw, arm); - - else if ((cmode & b1101) == b1000) - result = armv7_read_simd_instr_vmvn_immediate(raw, arm); - - else if ((cmode & b1101) == b1001) - result = armv7_read_simd_instr_vbic_immediate(raw, arm); - - else if ((cmode & b1110) == b1100) - result = armv7_read_simd_instr_vmvn_immediate(raw, arm); - - else if (cmode == b1110) - result = armv7_read_simd_instr_vmov_immediate(raw, arm); - - else if (cmode == b1111) - result = g_undef_instruction_new(IBS_UNDEFINED); - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 16 bits à désassembler. * -* arm = précise si l'encodage est en mode ARM ou Thumb. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A7.5. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArchInstruction *process_armv7_simd_floating_point_data_processing_instructions(uint32_t raw, bool arm) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t opc1; /* Champ 'opc1' à retrouver */ - uint32_t opc2; /* Champ 'opc2' à retrouver */ - uint32_t opc3; /* Champ 'opc3' à retrouver */ - - /** - * Suit les directives de : - * § A7.5 Floating-point data-processing instructions - */ - - if (arm) - { - if ((raw & 0x0f000e10) != 0xee000a00) return NULL; - } - else - { - if ((raw & 0xef000e10) != 0x0e000a00) return NULL; - } - - result = NULL; - - opc1 = (raw >> 20) & b1111; - opc2 = (raw >> 16) & b1111; - opc3 = (raw >> 6) & b11; - - - if ((opc1 & b1011) == b0000) - result = armv7_read_simd_instr_vmla_vmls_floating_point(raw, arm); - - else if ((opc1 & b1011) == b0001) - result = armv7_read_simd_instr_vnmla_vnmls_vnmul(raw, arm); - - else if ((opc1 & b1011) == b0010) - { - if ((opc3 & b01) == b01) - result = armv7_read_simd_instr_vnmla_vnmls_vnmul(raw, arm); - - else/* if ((opc3 & b01) == b00)*/ - result = armv7_read_simd_instr_vmul_floating_point(raw, arm); - - } - - else if ((opc1 & b1011) == b0011) - { - if ((opc3 & b01) == b00) - result = armv7_read_simd_instr_vadd_floating_point(raw, arm); - - else/* if ((opc3 & b01) == b01)*/ - result = armv7_read_simd_instr_vsub_floating_point(raw, arm); - - } - - else if ((opc1 & b1011) == b1000) - { - if ((opc3 & b01) == b00) - result = armv7_read_simd_instr_vdiv(raw, arm); - - } - - else if ((opc1 & b1011) == b1001) - result = armv7_read_simd_instr_vfnma_vfnms(raw, arm); - - else if ((opc1 & b1011) == b1010) - result = armv7_read_simd_instr_vfma_vfms(raw, arm); - - else if ((opc1 & b1011) == b1011) - { - if ((opc3 & b01) == b00) - result = armv7_read_simd_instr_vmov_immediate(raw, arm); - - else if (opc2 == b0000) - { - if (opc3 == b01) - result = armv7_read_simd_instr_vmov_register(raw, arm); - - else if (opc3 == b11) - result = armv7_read_simd_instr_vabs(raw, arm); - - } - - else if (opc2 == b0001) - { - if (opc3 == b01) - result = armv7_read_simd_instr_vneg(raw, arm); - - else if (opc3 == b11) - result = armv7_read_simd_instr_vsqrt(raw, arm); - - } - - else if ((opc2 & b1110) == b0010 && (opc3 & b01) == b01) - result = armv7_read_simd_instr_vcvtb_vcvtt(raw, arm); - - else if ((opc2 & b1110) == b0100 && (opc3 & b01) == b01) - result = armv7_read_simd_instr_vcmp_vcmpe(raw, arm); - - else if (opc2 == b0111 && opc3 == b11) - result = armv7_read_simd_instr_vcvt_between_double_precision_and_single_precision(raw, arm); - - else if (opc2 == b1000 && (opc3 & b01) == b01) - result = armv7_read_simd_instr_vcvt_vcvtr_between_floating_point_and_integer_floating_point(raw, arm); - - else if ((opc2 & b1110) == b1010 && (opc3 & b01) == b01) - result = armv7_read_simd_instr_vcvt_between_floating_point_and_fixed_point_floating_point(raw, arm); - - else if ((opc2 & b1110) == b1100 && (opc3 & b01) == b01) - result = armv7_read_simd_instr_vcvt_vcvtr_between_floating_point_and_integer_floating_point(raw, arm); - - else if ((opc2 & b1110) == b1110 && (opc3 & b01) == b01) - result = armv7_read_simd_instr_vcvt_between_floating_point_and_fixed_point_floating_point(raw, arm); - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 16 bits à désassembler. * -* arm = précise si l'encodage est en mode ARM ou Thumb. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A7.6. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArchInstruction *process_armv7_simd_extension_register_load_store_instructions(uint32_t raw, bool arm) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t opcode; /* Champ 'opcode' à retrouver */ - uint32_t rn; /* Champ 'rn' à retrouver */ - - /** - * Suit les directives de : - * § A7.6 Extension register load/store instructions - */ - - if (arm) - { - if ((raw & 0x0e000e00) != 0x0c000a00) return NULL; - } - else - { - if ((raw & 0xee000e00) != 0xec000a00) return NULL; - } - - result = NULL; - - opcode = (raw >> 20) & b11111; - rn = (raw >> 16) & b1111; - - if ((opcode & b11110) == b00100) - result = process_armv7_simd_64_bit_transfers_between_arm_core_and_extension_registers(raw, arm); - - else if ((opcode & b11011) == b01000) - result = armv7_read_simd_instr_vstm(raw, arm); - - else if ((opcode & b11011) == b01010) - result = armv7_read_simd_instr_vstm(raw, arm); - - else if ((opcode & b10011) == b10000) - result = armv7_read_simd_instr_vstr(raw, arm); - - else if ((opcode & b11011) == b10010) - { - if (rn != b1101) - result = armv7_read_simd_instr_vstm(raw, arm); - - else/* if (rn == b1101)*/ - result = armv7_read_simd_instr_vpush(raw, arm); - - } - - else if ((opcode & b11011) == b01001) - result = armv7_read_simd_instr_vldm(raw, arm); - - else if ((opcode & b11011) == b01011) - { - if (rn != 1101) - result = armv7_read_simd_instr_vldm(raw, arm); - - else/* if (rn == 1101)*/ - result = armv7_read_simd_instr_vpop(raw, arm); - - } - - else if ((opcode & b10011) == b10001) - result = armv7_read_simd_instr_vldr(raw, arm); - - else if ((opcode & b11011) == b10011) - result = armv7_read_simd_instr_vldm(raw, arm); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 16 bits à désassembler. * -* arm = précise si l'encodage est en mode ARM ou Thumb. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A7.7. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArchInstruction *process_armv7_simd_advanced_simd_element_or_structure_load_store_instructions(uint32_t raw, bool arm) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t a; /* Champ 'a' à retrouver */ - uint32_t l; /* Champ 'l' à retrouver */ - uint32_t b; /* Champ 'b' à retrouver */ - - /** - * Suit les directives de : - * § A7.7 Advanced SIMD element or structure load/store instructions - */ - - if (arm) - { - if ((raw & 0xff100000) != 0xf4000000) return NULL; - } - else - { - if ((raw & 0xff100000) != 0xf9000000) return NULL; - } - - result = NULL; - - a = (raw >> 23) & b1; - l = (raw >> 21) & b1; - b = (raw >> 8) & b1111; - - if (l == b0) - { - if (a == b0) - { - if (b == b0010) - result = armv7_read_simd_instr_vst1_multiple_single_elements(raw, arm); - - else if ((b & b1110) == b0110) - result = armv7_read_simd_instr_vst1_multiple_single_elements(raw, arm); - - else if (b == b1010) - result = armv7_read_simd_instr_vst1_multiple_single_elements(raw, arm); - - else if (b == b0011) - result = armv7_read_simd_instr_vst2_multiple_2_element_structures(raw, arm); - - else if ((b & b1110) == b1000) - result = armv7_read_simd_instr_vst2_multiple_2_element_structures(raw, arm); - - else if ((b & b1110) == b0100) - result = armv7_read_simd_instr_vst3_multiple_3_element_structures(raw, arm); - - else if ((b & b1110) == b0000) - result = armv7_read_simd_instr_vst4_multiple_4_element_structures(raw, arm); - - } - - else/* if (a == b1)*/ - { - if ((b & b1011) == b0000) - result = armv7_read_simd_instr_vst1_single_element_from_one_lane(raw, arm); - - else if (b == b1000) - result = armv7_read_simd_instr_vst1_single_element_from_one_lane(raw, arm); - - else if ((b & b1011) == b0001) - result = armv7_read_simd_instr_vst2_single_2_element_structure_from_one_lane(raw, arm); - - else if (b == b1001) - result = armv7_read_simd_instr_vst2_single_2_element_structure_from_one_lane(raw, arm); - - else if ((b & b1011) == b0010) - result = armv7_read_simd_instr_vst3_single_3_element_structure_from_one_lane(raw, arm); - - else if (b == b1010) - result = armv7_read_simd_instr_vst3_single_3_element_structure_from_one_lane(raw, arm); - - else if ((b & b1011) == b0011) - result = armv7_read_simd_instr_vst4_single_4_element_structure_from_one_lane(raw, arm); - - else if (b == b1011) - result = armv7_read_simd_instr_vst4_single_4_element_structure_from_one_lane(raw, arm); - - } - - } - - else/* if (l == b1)*/ - { - if (a == b0) - { - if (b == b0010) - result = armv7_read_simd_instr_vld1_multiple_single_elements(raw, arm); - - else if ((b & b1110) == b0110) - result = armv7_read_simd_instr_vld1_multiple_single_elements(raw, arm); - - else if (b == b1010) - result = armv7_read_simd_instr_vld1_multiple_single_elements(raw, arm); - - else if (b == b0011) - result = armv7_read_simd_instr_vld2_multiple_2_element_structures(raw, arm); - - else if ((b & b1110) == b1000) - result = armv7_read_simd_instr_vld2_multiple_2_element_structures(raw, arm); - - else if ((b & b1110) == b0100) - result = armv7_read_simd_instr_vld3_multiple_3_element_structures(raw, arm); - - else if ((b & b1110) == b0000) - result = armv7_read_simd_instr_vld4_multiple_4_element_structures(raw, arm); - - } - - else/* if (a == b1)*/ - { - if ((b & b1011) == b0000) - result = armv7_read_simd_instr_vld1_single_element_to_one_lane(raw, arm); - - else if (b == b1000) - result = armv7_read_simd_instr_vld1_single_element_to_one_lane(raw, arm); - - else if (b == b1100) - result = armv7_read_simd_instr_vld1_single_element_to_all_lanes(raw, arm); - - else if ((b & b1011) == b0001) - result = armv7_read_simd_instr_vld2_single_2_element_structure_to_one_lane(raw, arm); - - else if (b == b1001) - result = armv7_read_simd_instr_vld2_single_2_element_structure_to_one_lane(raw, arm); - - else if (b == b1101) - result = armv7_read_simd_instr_vld2_single_2_element_structure_to_all_lanes(raw, arm); - - else if ((b & b1011) == b0010) - result = armv7_read_simd_instr_vld3_single_3_element_structure_to_one_lane(raw, arm); - - else if (b == b1010) - result = armv7_read_simd_instr_vld3_single_3_element_structure_to_one_lane(raw, arm); - - else if (b == b1110) - result = armv7_read_simd_instr_vld3_single_3_element_structure_to_all_lanes(raw, arm); - - else if ((b & b1011) == b0011) - result = armv7_read_simd_instr_vld4_single_4_element_structure_to_one_lane(raw, arm); - - else if (b == b1011) - result = armv7_read_simd_instr_vld4_single_4_element_structure_to_one_lane(raw, arm); - - else if (b == b1111) - result = armv7_read_simd_instr_vld4_single_4_element_structure_to_all_lanes(raw, arm); - - } - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 16 bits à désassembler. * -* arm = précise si l'encodage est en mode ARM ou Thumb. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A7.8. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArchInstruction *process_armv7_simd_8_16_and_32_bit_transfer_between_arm_core_and_extension_registers(uint32_t raw, bool arm) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t a; /* Champ 'a' à retrouver */ - uint32_t l; /* Champ 'l' à retrouver */ - uint32_t c; /* Champ 'c' à retrouver */ - uint32_t b; /* Champ 'b' à retrouver */ - - /** - * Suit les directives de : - * § A7.8 8, 16, and 32-bit transfer between ARM core and extension registers - */ - - if (arm) - { - if ((raw & 0x0f000e10) != 0x0e000a10) return NULL; - } - else - { - if ((raw & 0xef000e10) != 0xee000a10) return NULL; - } - - result = NULL; - - a = (raw >> 21) & b111; - l = (raw >> 20) & b1; - c = (raw >> 8) & b1; - b = (raw >> 5) & b11; - - if (l == b0) - { - if (c == b0) - { - if (a == b000) - result = armv7_read_simd_instr_vmov_between_arm_core_register_and_single_precision_register(raw, arm); - - else if (a == b111) - { - result = armv7_read_simd_instr_vmsr(raw, arm); - - if (result == NULL /* ! */) - result = armv7_read_simd_instr_vmsr_b9(raw, arm); - - } - - } - - else/* if (c == b1)*/ - { - if ((a & b100) == b000) - result = armv7_read_simd_instr_vmov_arm_core_register_to_scalar(raw, arm); - - else if (/*(a & b100) == b000) && */(b & b10) == b00) - result = armv7_read_simd_instr_vdup_arm_core_register(raw, arm); - - } - - } - - else/* if (l == b1)*/ - { - if (c == b0) - { - if (a == b000) - result = armv7_read_simd_instr_vmov_between_arm_core_register_and_single_precision_register(raw, arm); - - else if (a == b111) - { - result = armv7_read_simd_instr_vmrs(raw, arm); - - if (result == NULL /* ! */) - result = armv7_read_simd_instr_vmrs_b9(raw, arm); - - } - - } - - else/* if (c == b1)*/ - result = armv7_read_simd_instr_vmov_scalar_to_arm_core_register(raw, arm); - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 16 bits à désassembler. * -* arm = précise si l'encodage est en mode ARM ou Thumb. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A7.9. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArchInstruction *process_armv7_simd_64_bit_transfers_between_arm_core_and_extension_registers(uint32_t raw, bool arm) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t c; /* Champ 'c' à retrouver */ - uint32_t op; /* Champ 'op' à retrouver */ - - /** - * Suit les directives de : - * § A7.9 64-bit transfers between ARM core and extension registers - */ - - if (arm) - { - if ((raw & 0x0fe00e00) != 0x0c400a00) return NULL; - } - else - { - if ((raw & 0xefe00e00) != 0xec400a00) return NULL; - } - - result = NULL; - - c = (raw >> 8) & b1; - op = (raw >> 4) & b1111; - - if (c == b0 && (op & b1101) == 0001) - result = armv7_read_simd_instr_vmov_between_two_arm_core_registers_and_two_single_precision_registers(raw, arm); - - else if (c == b1 && (op & b1101) == 0001) - result = armv7_read_simd_instr_vmov_between_two_arm_core_registers_and_a_doubleword_extension_register(raw, arm); - - return result; - -} diff --git a/src/arch/arm/v7/simd.h b/src/arch/arm/v7/simd.h deleted file mode 100644 index f4fe556..0000000 --- a/src/arch/arm/v7/simd.h +++ /dev/null @@ -1,55 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * simd.h - prototypes pour le désassemblage des instructions ARMv7 SIMD - * - * Copyright (C) 2016-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_ARM_V7_SIMD_H -#define _ARCH_ARM_V7_SIMD_H - - -#include <stdbool.h> - - -#include "../../instruction.h" - - - -/* Désassemble une instruction ARMv7 liées au chapitre A7.4. */ -GArchInstruction *process_armv7_simd_advanced_simd_data_processing_instructions(uint32_t, bool); - -/* Désassemble une instruction ARMv7 liées au chapitre A7.5. */ -GArchInstruction *process_armv7_simd_floating_point_data_processing_instructions(uint32_t, bool); - -/* Désassemble une instruction ARMv7 liées au chapitre A7.6. */ -GArchInstruction *process_armv7_simd_extension_register_load_store_instructions(uint32_t, bool); - -/* Désassemble une instruction ARMv7 liées au chapitre A7.7. */ -GArchInstruction *process_armv7_simd_advanced_simd_element_or_structure_load_store_instructions(uint32_t, bool); - -/* Désassemble une instruction ARMv7 liées au chapitre A7.8. */ -GArchInstruction *process_armv7_simd_8_16_and_32_bit_transfer_between_arm_core_and_extension_registers(uint32_t, bool); - -/* Désassemble une instruction ARMv7 liées au chapitre A7.9. */ -GArchInstruction *process_armv7_simd_64_bit_transfers_between_arm_core_and_extension_registers(uint32_t, bool); - - - -#endif /* _ARCH_ARM_V7_SIMD_H */ diff --git a/src/arch/arm/v7/thumb_16.c b/src/arch/arm/v7/thumb_16.c deleted file mode 100644 index 7f59481..0000000 --- a/src/arch/arm/v7/thumb_16.c +++ /dev/null @@ -1,670 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * thumb_16.c - désassemblage des instructions ARMv7 Thumb 16 bits - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#include "thumb_16.h" - - -#include <stdint.h> - - -#include "opcodes/thumb_16_opcodes.h" -#include "opcodes/opcodes_tmp_thumb_16.h" -#include "../../../common/bconst.h" - - - -/* Désassemble une instruction ARMv7 liées au chapitre A6.2.1 */ -static GArchInstruction *process_armv7_thumb_16_shift_immediate_add_subtract_move_and_compare(uint16_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A6.2.2. */ -static GArchInstruction *process_armv7_thumb_16_data_processing(uint16_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A6.2.3. */ -static GArchInstruction *process_armv7_thumb_16_special_data_instructions_and_branch_and_exchange(uint16_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A6.2.4. */ -static GArchInstruction *process_armv7_thumb_16_load_store_single_data_item(uint16_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A6.2.5. */ -static GArchInstruction *process_armv7_thumb_16_miscellaneous_16_bit_instructions(uint16_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A6.2.5.b. */ -static GArchInstruction *process_armv7_thumb_16_miscellaneous_16_bit_instructions_if_then_and_hints(uint16_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A6.2.6. */ -static GArchInstruction *process_armv7_thumb_16_conditional_branch_and_supervisor_call(uint16_t); - - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 16 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A6.2. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArchInstruction *process_armv7_thumb_16_instruction_set_encoding(uint16_t raw) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint16_t opcode; /* Champ 'opcode' à retrouver */ - - /** - * Suit les directives de : - * § A6.2 16-bit Thumb instruction encoding - */ - - result = NULL; - - opcode = (raw >> 10) & b111111; - - if ((opcode & b110000) == b000000) - result = process_armv7_thumb_16_shift_immediate_add_subtract_move_and_compare(raw); - - else if (opcode == b010000) - result = process_armv7_thumb_16_data_processing(raw); - - else if (opcode == b010001) - result = process_armv7_thumb_16_special_data_instructions_and_branch_and_exchange(raw); - - else if ((opcode & b111110) == b010010) - result = armv7_read_thumb_16_instr_ldr_literal(raw); - - else if ((opcode & b111100) == b010100) - result = process_armv7_thumb_16_load_store_single_data_item(raw); - - else if ((opcode & b111000) == b011000) - result = process_armv7_thumb_16_load_store_single_data_item(raw); - - else if ((opcode & b111000) == b100000) - result = process_armv7_thumb_16_load_store_single_data_item(raw); - - else if ((opcode & b111110) == b101000) - result = armv7_read_thumb_16_instr_adr(raw); - - else if ((opcode & b111110) == b101010) - result = armv7_read_thumb_16_instr_add_sp_plus_immediate(raw); - - else if ((opcode & b111100) == b101100) - result = process_armv7_thumb_16_miscellaneous_16_bit_instructions(raw); - - else if ((opcode & b111110) == b110000) - result = armv7_read_thumb_16_instr_stm_stmia_stmea(raw); - - else if ((opcode & b111110) == b110010) - result = armv7_read_thumb_16_instr_ldm_ldmia_ldmfd_thumb(raw); - - else if ((opcode & b111100) == b110100) - result = process_armv7_thumb_16_conditional_branch_and_supervisor_call(raw); - - else if ((opcode & b111110) == b111000) - result = armv7_read_thumb_16_instr_b(raw); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 16 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A6.2.1. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_thumb_16_shift_immediate_add_subtract_move_and_compare(uint16_t raw) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint16_t opcode; /* Champ 'opcode' à retrouver */ - - /** - * Suit les directives de : - * § A6.2.1 Shift (immediate), add, subtract, move, and compare - */ - - if ((raw & 0xc000) != 0x0000) return NULL; - - result = NULL; - - opcode = (raw >> 9) & b11111; - - if ((opcode & b11100) == b00000) - result = armv7_read_thumb_16_instr_lsl_immediate(raw); - - else if ((opcode & b11100) == b00100) - result = armv7_read_thumb_16_instr_lsr_immediate(raw); - - else if ((opcode & b11100) == b01000) - result = armv7_read_thumb_16_instr_asr_immediate(raw); - - else if (opcode == b01100) - result = armv7_read_thumb_16_instr_add_register_thumb(raw); - - else if (opcode == b01101) - result = armv7_read_thumb_16_instr_sub_register(raw); - - else if (opcode == b01110) - result = armv7_read_thumb_16_instr_add_immediate_thumb(raw); - - else if (opcode == b01111) - result = armv7_read_thumb_16_instr_sub_immediate_thumb(raw); - - else if ((opcode & b11100) == b10000) - result = armv7_read_thumb_16_instr_mov_immediate(raw); - - else if ((opcode & b11100) == b10100) - result = armv7_read_thumb_16_instr_cmp_immediate(raw); - - else if ((opcode & b11100) == b11000) - result = armv7_read_thumb_16_instr_add_immediate_thumb(raw); - - else if ((opcode & b11100) == b11100) - result = armv7_read_thumb_16_instr_sub_immediate_thumb(raw); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 16 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A6.2.2. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_thumb_16_data_processing(uint16_t raw) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint16_t opcode; /* Champ 'opcode' à retrouver */ - - /** - * Suit les directives de : - * § A6.2.2 Data-processing - */ - - if ((raw & 0xfc00) != 0x4000) return NULL; - - result = NULL; - - opcode = (raw >> 6) & b1111; - - switch (opcode) - { - case b0000: - result = armv7_read_thumb_16_instr_and_register(raw); - break; - - case b0001: - result = armv7_read_thumb_16_instr_eor_register(raw); - break; - - case b0010: - result = armv7_read_thumb_16_instr_lsl_register(raw); - break; - - case b0011: - result = armv7_read_thumb_16_instr_lsr_register(raw); - break; - - case b0100: - result = armv7_read_thumb_16_instr_asr_register(raw); - break; - - case b0101: - result = armv7_read_thumb_16_instr_adc_register(raw); - break; - - case b0110: - result = armv7_read_thumb_16_instr_sbc_register(raw); - break; - - case b0111: - result = armv7_read_thumb_16_instr_ror_register(raw); - break; - - case b1000: - result = armv7_read_thumb_16_instr_tst_register(raw); - break; - - case b1001: - result = armv7_read_thumb_16_instr_rsb_immediate(raw); - break; - - case b1010: - result = armv7_read_thumb_16_instr_cmp_register(raw); - break; - - case b1011: - result = armv7_read_thumb_16_instr_cmn_register(raw); - break; - - case b1100: - result = armv7_read_thumb_16_instr_orr_register(raw); - break; - - case b1101: - result = armv7_read_thumb_16_instr_mul(raw); - break; - - case b1110: - result = armv7_read_thumb_16_instr_bic_register(raw); - break; - - case b1111: - result = armv7_read_thumb_16_instr_mvn_register(raw); - break; - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 16 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A6.2.3. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_thumb_16_special_data_instructions_and_branch_and_exchange(uint16_t raw) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint16_t opcode; /* Champ 'opcode' à retrouver */ - - /** - * Suit les directives de : - * § A6.2.3 Special data instructions and branch and exchange - */ - - if ((raw & 0xfc00) != 0x4400) return NULL; - - result = NULL; - - opcode = (raw >> 6) & b1111; - - if (opcode == b0000) - result = armv7_read_thumb_16_instr_add_register_thumb(raw); - - else if (opcode == b0001) - result = armv7_read_thumb_16_instr_add_register_thumb(raw); - - else if ((opcode & b1110) == b0010) - result = armv7_read_thumb_16_instr_add_register_thumb(raw); - - else if ((opcode & b1100) == b0100) - result = armv7_read_thumb_16_instr_cmp_register(raw); - - else if (opcode == b1000) - result = armv7_read_thumb_16_instr_mov_register_thumb(raw); - - else if (opcode == b1001) - result = armv7_read_thumb_16_instr_mov_register_thumb(raw); - - else if ((opcode & b1110) == b1010) - result = armv7_read_thumb_16_instr_mov_register_thumb(raw); - - else if ((opcode & b1110) == b1100) - result = armv7_read_thumb_16_instr_bx(raw); - - else if ((opcode & b1110) == b1110) - result = armv7_read_thumb_16_instr_blx_register(raw); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 16 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A6.2.4. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_thumb_16_load_store_single_data_item(uint16_t raw) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint16_t opa; /* Champ 'opa' à retrouver */ - uint16_t opb; /* Champ 'opb' à retrouver */ - - /** - * Suit les directives de : - * § A6.2.4 Load/store single data item - */ - - result = NULL; - - opa = (raw >> 12) & b1111; - opb = (raw >> 9) & b111; - - switch (opa) - { - case b0101: - switch (opb) - { - case b000: - result = armv7_read_thumb_16_instr_str_register(raw); - break; - - case b001: - result = armv7_read_thumb_16_instr_strh_register(raw); - break; - - case b010: - result = armv7_read_thumb_16_instr_strb_register(raw); - break; - - case b011: - result = armv7_read_thumb_16_instr_ldrsb_register(raw); - break; - - case b100: - result = armv7_read_thumb_16_instr_ldr_register_thumb(raw); - break; - - case b101: - result = armv7_read_thumb_16_instr_ldrh_register(raw); - break; - - case b110: - result = armv7_read_thumb_16_instr_ldrb_register(raw); - break; - - case b111: - result = armv7_read_thumb_16_instr_ldrsh_register(raw); - break; - - } - break; - - case b0110: - - if ((opb & b100) == b000) - result = armv7_read_thumb_16_instr_str_immediate_thumb(raw); - else /*if ((opb & b100) == b100)*/ - result = armv7_read_thumb_16_instr_ldr_immediate_thumb(raw); - - break; - - case b0111: - - if ((opb & b100) == b000) - result = armv7_read_thumb_16_instr_strb_immediate_thumb(raw); - else /*if ((opb & b100) == b100)*/ - result = armv7_read_thumb_16_instr_ldrb_immediate_thumb(raw); - - break; - - case b1000: - - if ((opb & b100) == b000) - result = armv7_read_thumb_16_instr_strh_immediate_thumb(raw); - else /*if ((opb & b100) == b100)*/ - result = armv7_read_thumb_16_instr_ldrh_immediate_thumb(raw); - - break; - - case b1001: - - if ((opb & b100) == b000) - result = armv7_read_thumb_16_instr_str_immediate_thumb(raw); - else /*if ((opb & b100) == b100)*/ - result = armv7_read_thumb_16_instr_ldr_immediate_thumb(raw); - - break; - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 16 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A6.2.5. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_thumb_16_miscellaneous_16_bit_instructions(uint16_t raw) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint16_t opcode; /* Champ 'opcode' à retrouver */ - - /** - * Suit les directives de : - * § A6.2.5 Miscellaneous 16-bit instructions - */ - - if ((raw & 0xf000) != 0xb000) return NULL; - - result = NULL; - - opcode = (raw >> 5) & b1111111; - - if ((opcode & b1111100) == b0000000) - result = armv7_read_thumb_16_instr_add_sp_plus_immediate(raw); - - else if ((opcode & b1111100) == b0000100) - result = armv7_read_thumb_16_instr_sub_sp_minus_immediate(raw); - - else if ((opcode & b1111000) == b0001000) - result = armv7_read_thumb_16_instr_cbnz_cbz(raw); - - else if ((opcode & b1111110) == b0010000) - result = armv7_read_thumb_16_instr_sxth(raw); - - else if ((opcode & b1111110) == b0010010) - result = armv7_read_thumb_16_instr_sxtb(raw); - - else if ((opcode & b1111110) == b0010100) - result = armv7_read_thumb_16_instr_uxth(raw); - - else if ((opcode & b1111110) == b0010110) - result = armv7_read_thumb_16_instr_uxtb(raw); - - else if ((opcode & b1111000) == b0011000) - result = armv7_read_thumb_16_instr_cbnz_cbz(raw); - - else if ((opcode & b1110000) == b0100000) - result = armv7_read_thumb_16_instr_push(raw); - - else if (opcode == b0110010) - result = armv7_read_thumb_16_instr_setend(raw); - - else if (opcode == b0110011) - result = armv7_read_thumb_16_instr_cps_thumb(raw); - - else if ((opcode & b1111000) == b1001000) - result = armv7_read_thumb_16_instr_cbnz_cbz(raw); - - else if ((opcode & b1111110) == b1010000) - result = armv7_read_thumb_16_instr_rev(raw); - - else if ((opcode & b1111110) == b1010010) - result = armv7_read_thumb_16_instr_rev16(raw); - - else if ((opcode & b1111110) == b1010110) - result = armv7_read_thumb_16_instr_revsh(raw); - - else if ((opcode & b1111000) == b1011000) - result = armv7_read_thumb_16_instr_cbnz_cbz(raw); - - else if ((opcode & b1110000) == b1100000) - result = armv7_read_thumb_16_instr_pop_thumb(raw); - - else if ((opcode & b1111000) == b1110000) - result = armv7_read_thumb_16_instr_bkpt(raw); - - else if ((opcode & b1111000) == b1111000) - result = process_armv7_thumb_16_miscellaneous_16_bit_instructions_if_then_and_hints(raw); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 16 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A6.2.5.b.* -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_thumb_16_miscellaneous_16_bit_instructions_if_then_and_hints(uint16_t raw) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint16_t opa; /* Champ 'opa' à retrouver */ - uint16_t opb; /* Champ 'opb' à retrouver */ - - /** - * Suit les directives de : - * § A6.2.5 Miscellaneous 16-bit instructions - * |-> If-Then, and hints - */ - - if ((raw & 0xff00) != 0xbf00) return NULL; - - result = NULL; - - opa = (raw >> 4) & b1111; - opb = (raw >> 0) & b1111; - - if (opb != b0000) - result = armv7_read_thumb_16_instr_it(raw); - - else - switch (opa) - { - case b0000: - result = armv7_read_thumb_16_instr_nop(raw); - break; - - case b0001: - result = armv7_read_thumb_16_instr_yield(raw); - break; - - case b0010: - result = armv7_read_thumb_16_instr_wfe(raw); - break; - - case b0011: - result = armv7_read_thumb_16_instr_wfi(raw); - break; - - case b0100: - result = armv7_read_thumb_16_instr_sev(raw); - break; - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 16 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A6.2.6. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_thumb_16_conditional_branch_and_supervisor_call(uint16_t raw) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint16_t opcode; /* Champ 'opcode' à retrouver */ - - /** - * Suit les directives de : - * § A6.2.6 Conditional branch, and Supervisor Call - */ - - if ((raw & 0xf000) != 0xd000) return NULL; - - result = NULL; - - opcode = (raw >> 8) & b1111; - - switch (opcode) - { - case b1110: - result = armv7_read_thumb_16_instr_udf(raw); - break; - - case b1111: - result = armv7_read_thumb_16_instr_svc_previously_swi(raw); - break; - - default: - result = armv7_read_thumb_16_instr_b(raw); - break; - - } - - return result; - -} diff --git a/src/arch/arm/v7/thumb_16.h b/src/arch/arm/v7/thumb_16.h deleted file mode 100644 index d75f490..0000000 --- a/src/arch/arm/v7/thumb_16.h +++ /dev/null @@ -1,37 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * thumb_16.h - prototypes pour le désassemblage des instructions ARMv7 Thumb 16 bits - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_ARM_V7_THUMB_16_H -#define _ARCH_ARM_V7_THUMB_16_H - - -#include "../../instruction.h" - - - -/* Désassemble une instruction ARMv7 liées au chapitre A6.2. */ -GArchInstruction *process_armv7_thumb_16_instruction_set_encoding(uint16_t); - - - -#endif /* _ARCH_ARM_V7_THUMB_16_H */ diff --git a/src/arch/arm/v7/thumb_32.c b/src/arch/arm/v7/thumb_32.c deleted file mode 100644 index f9de2e6..0000000 --- a/src/arch/arm/v7/thumb_32.c +++ /dev/null @@ -1,2268 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * thumb_32.c - désassemblage des instructions ARMv7 Thumb 32 bits - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#include "thumb_32.h" - - -#include <stdint.h> - - -#include "simd.h" -#include "opcodes/thumb_32_opcodes.h" -#include "opcodes/opcodes_tmp_thumb_32.h" -#include "../../undefined.h" -#include "../../../common/bconst.h" - - - -/* Désassemble une instruction ARMv7 liées au chapitre A6.3.1. */ -static GArchInstruction *process_armv7_thumb_32_data_processing_modified_immediate(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A6.3.3. */ -static GArchInstruction *process_armv7_thumb_32_data_processing_plain_binary_immediate(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A6.3.4. */ -static GArchInstruction *process_armv7_thumb_32_branches_and_miscellaneous_control(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A6.3.4b. */ -static GArchInstruction *process_armv7_thumb_32_change_processor_state_and_hints(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A6.3.4t. */ -static GArchInstruction *process_armv7_thumb_32_miscellaneous_control_instructions(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A6.3.5. */ -static GArchInstruction *process_armv7_thumb_32_load_store_multiple(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A6.3.6. */ -static GArchInstruction *process_armv7_thumb_32_load_store_dual_load_store_exclusive_table_branch(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A6.3.7. */ -static GArchInstruction *process_armv7_thumb_32_load_word(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A6.3.8. */ -static GArchInstruction *process_armv7_thumb_32_load_halfword_memory_hints(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A6.3.9. */ -static GArchInstruction *process_armv7_thumb_32_load_byte_memory_hints(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A6.3.10. */ -static GArchInstruction *process_armv7_thumb_32_store_single_data_item(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A6.3.11. */ -static GArchInstruction *process_armv7_thumb_32_data_processing_shifted_register(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A6.3.11b. */ -static GArchInstruction *process_armv7_thumb_32_move_register_and_immediate_shifts(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A6.3.12. */ -static GArchInstruction *process_armv7_thumb_32_data_processing_register(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A6.3.13. */ -static GArchInstruction *process_armv7_thumb_32_parallel_addition_and_subtraction_signed(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A6.3.14. */ -static GArchInstruction *process_armv7_thumb_32_parallel_addition_and_subtraction_unsigned(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A6.3.15. */ -static GArchInstruction *process_armv7_thumb_32_miscellaneous_operations(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A6.3.16. */ -static GArchInstruction *process_armv7_thumb_32_multiply_multiply_accumulate_and_absolute_difference(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A6.3.17. */ -static GArchInstruction *process_armv7_thumb_32_long_multiply_long_multiply_accumulate_and_divide(uint32_t); - -/* Désassemble une instruction ARMv7 liées au chapitre A6.3.18. */ -static GArchInstruction *process_armv7_thumb_32_coprocessor_advanced_simd_and_floating_point_instructions(uint32_t); - - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArchInstruction *process_armv7_thumb_32_instruction_set_encoding(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t op1; /* Champ 'op1' à retrouver */ - uint32_t op2; /* Champ 'op2' à retrouver */ - uint32_t op; /* Champ 'op' à retrouver */ - - /** - * Suit les directives de : - * § A6.3 32-bit Thumb instruction encoding - */ - - if (((raw >> 29) & b111) != b111) return NULL; - - result = NULL; - - op1 = (raw >> 27) & b11; - op2 = (raw >> 20) & b1111111; - op = (raw >> 15) & b1; - - switch (op1) - { - case b01: - - if ((op2 & b1100100) == b0000000) - result = process_armv7_thumb_32_load_store_multiple(raw); - - else if ((op2 & b1100100) == b0000100) - result = process_armv7_thumb_32_load_store_dual_load_store_exclusive_table_branch(raw); - - else if ((op2 & b1100000) == b0100000) - result = process_armv7_thumb_32_data_processing_shifted_register(raw); - - else if ((op2 & b1000000) == b1000000) - result = process_armv7_thumb_32_coprocessor_advanced_simd_and_floating_point_instructions(raw); - - break; - - case b10: - - if (op == 1) - result = process_armv7_thumb_32_branches_and_miscellaneous_control(raw); - - else - { - if ((op2 & b0100000) == b0000000) - result = process_armv7_thumb_32_data_processing_modified_immediate(raw); - - else if ((op2 & b0100000) == b0100000) - result = process_armv7_thumb_32_data_processing_plain_binary_immediate(raw); - - } - - break; - - case b11: - - if ((op2 & b1110001) == b0000000) - result = process_armv7_thumb_32_store_single_data_item(raw); - - else if ((op2 & b1100111) == b0000001) - result = process_armv7_thumb_32_load_byte_memory_hints(raw); - - else if ((op2 & b1100111) == b0000011) - result = process_armv7_thumb_32_load_halfword_memory_hints(raw); - - else if ((op2 & b1100111) == b0000101) - result = process_armv7_thumb_32_load_word(raw); - - else if ((op2 & b1100111) == b0000111) - result = g_undef_instruction_new(IBS_UNDEFINED); - - else if ((op2 & b1110001) == b0010000) - result = process_armv7_simd_advanced_simd_element_or_structure_load_store_instructions(raw, false); - - else if ((op2 & b1110000) == b0100000) - result = process_armv7_thumb_32_data_processing_register(raw); - - else if ((op2 & b1111000) == b0110000) - result = process_armv7_thumb_32_multiply_multiply_accumulate_and_absolute_difference(raw); - - else if ((op2 & b1111000) == b0111000) - result = process_armv7_thumb_32_long_multiply_long_multiply_accumulate_and_divide(raw); - - else if ((op2 & b1000000) == b1000000) - result = process_armv7_thumb_32_coprocessor_advanced_simd_and_floating_point_instructions(raw); - - break; - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.1. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_thumb_32_data_processing_modified_immediate(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t op; /* Champ 'op' à retrouver */ - uint32_t rn; /* Champ 'rn' à retrouver */ - uint32_t rds; /* Champ 'rds' à retrouver */ - - /** - * Suit les directives de : - * § A6.3.1 Data-processing (modified immediate) - */ - - if ((raw & 0xfa008000) != 0xf0000000) return NULL; - - result = NULL; - - op = (raw >> 21) & b1111; - rn = (raw >> 16) & b1111; - rds = (((raw >> 8) & b1111) << 1) | ((raw >> 20) & b1); - - switch (op) - { - case b0000: - - if (rds == b11111) - result = armv7_read_thumb_32_instr_tst_immediate(raw); - - else - result = armv7_read_thumb_32_instr_and_immediate(raw); - - break; - - case b0001: - result = armv7_read_thumb_32_instr_bic_immediate(raw); - break; - - case b0010: - - if (rn == b1111) - result = armv7_read_thumb_32_instr_mov_immediate(raw); - - else - result = armv7_read_thumb_32_instr_orr_immediate(raw); - - break; - - case b0011: - - if (rn == b1111) - result = armv7_read_thumb_32_instr_mvn_immediate(raw); - - else - result = armv7_read_thumb_32_instr_orn_immediate(raw); - - break; - - case b0100: - - if (rds == b11111) - result = armv7_read_thumb_32_instr_teq_immediate(raw); - - else - result = armv7_read_thumb_32_instr_eor_immediate(raw); - - break; - - case b1000: - - if (rds == b11111) - result = armv7_read_thumb_32_instr_cmn_immediate(raw); - - else - result = armv7_read_thumb_32_instr_add_immediate_thumb(raw); - - break; - - case b1010: - result = armv7_read_thumb_32_instr_adc_immediate(raw); - break; - - case b1011: - result = armv7_read_thumb_32_instr_sbc_immediate(raw); - break; - - case b1101: - - if (rds == b11111) - result = armv7_read_thumb_32_instr_cmp_immediate(raw); - - else - result = armv7_read_thumb_32_instr_sub_immediate_thumb(raw); - - break; - - case b1110: - result = armv7_read_thumb_32_instr_rsb_immediate(raw); - break; - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.3. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_thumb_32_data_processing_plain_binary_immediate(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t op; /* Champ 'op' à retrouver */ - uint32_t rn; /* Champ 'rn' à retrouver */ - - /** - * Suit les directives de : - * § A6.3.3 Data-processing (plain binary immediate) - */ - - if ((raw & 0xfa008000) != 0xf2000000) return NULL; - - result = NULL; - - op = (raw >> 20) & b11111; - rn = (raw >> 16) & b1111; - - switch (op) - { - case b00000: - - if (rn == b1111) - result = armv7_read_thumb_32_instr_adr(raw); - - else - result = armv7_read_thumb_32_instr_add_immediate_thumb(raw); - - break; - - case b00100: - result = armv7_read_thumb_32_instr_mov_immediate(raw); - break; - - case b01010: - - if (rn == b11111) - result = armv7_read_thumb_32_instr_adr(raw); - - else - result = armv7_read_thumb_32_instr_sub_immediate_thumb(raw); - - break; - - case b01100: - result = armv7_read_thumb_32_instr_movt(raw); - break; - - case b10000: - result = armv7_read_thumb_32_instr_ssat(raw); - break; - - case b10010: - - if ((raw & 0x000070c0) != 0) - result = armv7_read_thumb_32_instr_ssat(raw); - - else - result = armv7_read_thumb_32_instr_ssat16(raw); - - break; - - case b10100: - result = armv7_read_thumb_32_instr_sbfx(raw); - break; - - case b10110: - - if (rn == b11111) - result = armv7_read_thumb_32_instr_bfc(raw); - - else - result = armv7_read_thumb_32_instr_bfi(raw); - - break; - - case b11000: - result = armv7_read_thumb_32_instr_usat(raw); - break; - - case b11010: - - if ((raw & 0x000070c0) != 0) - result = armv7_read_thumb_32_instr_usat(raw); - - else - result = armv7_read_thumb_32_instr_usat16(raw); - - break; - - case b11100: - result = armv7_read_thumb_32_instr_ubfx(raw); - break; - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.4. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_thumb_32_branches_and_miscellaneous_control(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t op; /* Champ 'op' à retrouver */ - uint32_t op1; /* Champ 'op1' à retrouver */ - uint32_t op2; /* Champ 'op2' à retrouver */ - uint32_t imm8; /* Champ 'imm8' à retrouver */ - - /** - * Suit les directives de : - * § A6.3.4 Branches and miscellaneous control - */ - - if ((raw & 0xf8000000) != 0xf0000000) return NULL; - - result = NULL; - - op = (raw >> 20) & b1111111; - op1 = (raw >> 12) & b111; - op2 = (raw >> 8) & b1111; - imm8 = (raw >> 0) & b11111111; - - if (op1 == b000 && op == b1111110) - result = armv7_read_thumb_32_instr_hvc(raw); - - else if (op1 == b000 && op == b1111111) - result = armv7_read_thumb_32_instr_smc_previously_smi(raw); - - else if ((op1 & b101) == b000) - { - if ((op & b0111000) != b0111000) - result = armv7_read_thumb_32_instr_b(raw); - - else if ((imm8 & b00100000) == b00100000 && (op & b1111110) == b0111000) - result = armv7_read_thumb_32_instr_msr_banked_register(raw); - - else if ((imm8 & b00100000) == b00000000 && op == b0111000 && (op2 & b0011) == b0000) - result = armv7_read_thumb_32_instr_msr_register(raw); - - else if ((imm8 & b00100000) == b00000000 && op == b0111000 && (op2 & b0011) == b0001) - result = armv7_read_thumb_32_instr_b_msr_register(raw); - - else if ((imm8 & b00100000) == b00000000 && op == b0111000 && (op2 & b0010) == b0010) - result = armv7_read_thumb_32_instr_b_msr_register(raw); - - else if ((imm8 & b00100000) == b00000000 && op == b0111001) - result = armv7_read_thumb_32_instr_b_msr_register(raw); - - else if (op == b0111010) - result = process_armv7_thumb_32_change_processor_state_and_hints(raw); - - else if (op == b0111011) - result = process_armv7_thumb_32_miscellaneous_control_instructions(raw); - - else if (op == b0111100) - result = armv7_read_thumb_32_instr_bxj(raw); - - else if (imm8 == b00000000 && op == b0111101) - result = armv7_read_thumb_32_instr_eret(raw); - - else if (imm8 != b00000000 && op == b0111101) - result = armv7_read_thumb_32_instr_subs_pc_lr_thumb(raw); - - else if ((imm8 & b00100000) == b00100000 && (op & b1111110) == b0111110) - result = armv7_read_thumb_32_instr_mrs_banked_register(raw); - - else if ((imm8 & b00100000) == b00000000 && op == b0111110) - result = armv7_read_thumb_32_instr_mrs(raw); - - else if ((imm8 & b00100000) == b00000000 && op == b0111111) - result = armv7_read_thumb_32_instr_b_mrs(raw); - - } - - else if ((op1 & b101) == b001) - result = armv7_read_thumb_32_instr_b(raw); - - else if (op1 == b010 && op == b1111111) - result = armv7_read_thumb_32_instr_udf(raw); - - else if ((op1 & b101) == b100) - result = armv7_read_thumb_32_instr_bl_blx_immediate(raw); - - else if ((op1 & b101) == b101) - result = armv7_read_thumb_32_instr_bl_blx_immediate(raw); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 classique. * -* * -* Retour : Désassemble une instruction ARMv7 liées au chapitre A6.3.4b. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_thumb_32_change_processor_state_and_hints(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t op1; /* Champ 'op1' à retrouver */ - uint32_t op2; /* Champ 'op2' à retrouver */ - - /** - * Suit les directives de : - * § A6.3.4 Branches and miscellaneous control - * |-> Change Processor State, and hints - */ - - if ((raw & 0xfff0d000) != 0xf3a08000) return NULL; - - result = NULL; - - op1 = (raw >> 8) & b111; - op2 = (raw >> 0) & b11111111; - - if (op1 != b000) - result = armv7_read_thumb_32_instr_cps_thumb(raw); - - else - { - if (op2 == b00000000) - result = armv7_read_thumb_32_instr_nop(raw); - - else if (op2 == b00000001) - result = armv7_read_thumb_32_instr_yield(raw); - - else if (op2 == b00000010) - result = armv7_read_thumb_32_instr_wfe(raw); - - else if (op2 == b00000011) - result = armv7_read_thumb_32_instr_wfi(raw); - - else if (op2 == b00000100) - result = armv7_read_thumb_32_instr_sev(raw); - - else if ((op2 & b11110000) == b11110000) - result = armv7_read_thumb_32_instr_dbg(raw); - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.4t. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_thumb_32_miscellaneous_control_instructions(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t op; /* Champ 'op' à retrouver */ - - /** - * Suit les directives de : - * § A6.3.4 Branches and miscellaneous control - * |-> Miscellaneous control instructions - */ - - if ((raw & 0xfff0d000) != 0xf3b08000) return NULL; - - result = NULL; - - op = (raw >> 4) & b1111; - - switch (op) - { - case b0000: - result = armv7_read_thumb_32_instr_enterx_leavex(raw); - break; - - case b0001: - result = armv7_read_thumb_32_instr_enterx_leavex(raw); - break; - - case b0010: - result = armv7_read_thumb_32_instr_clrex(raw); - break; - - case b0100: - result = armv7_read_thumb_32_instr_dsb(raw); - break; - - case b0101: - result = armv7_read_thumb_32_instr_dmb(raw); - break; - - case b0110: - result = armv7_read_thumb_32_instr_isb(raw); - break; - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.5. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_thumb_32_load_store_multiple(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t op; /* Champ 'op' à retrouver */ - uint32_t l; /* Champ 'l' à retrouver */ - uint32_t wrn; /* Champ 'wrn' à retrouver */ - - /** - * Suit les directives de : - * § A6.3.5 Load/store multiple - */ - - if ((raw & 0xfe400000) != 0xe8000000) return NULL; - - result = NULL; - - op = (raw >> 23) & b11; - l = (raw >> 20) & b1; - wrn = (((raw >> 21) & b1) << 4) | ((raw >> 16) & b1111); - - switch (op) - { - case b00: - - if (l == b0) - result = armv7_read_thumb_32_instr_srs_thumb(raw); - - else - result = armv7_read_thumb_32_instr_rfe(raw); - - break; - - case b01: - - if (l == b0) - result = armv7_read_thumb_32_instr_stm_stmia_stmea(raw); - - else - { - if (wrn == b11101) - result = armv7_read_thumb_32_instr_pop_thumb(raw); - - else - result = armv7_read_thumb_32_instr_ldm_ldmia_ldmfd_thumb(raw); - - } - - break; - - case b10: - - if (l == b0) - { - if (wrn == b11101) - result = armv7_read_thumb_32_instr_push(raw); - - else - result = armv7_read_thumb_32_instr_stmdb_stmfd(raw); - - } - - else - result = armv7_read_thumb_32_instr_ldmdb_ldmea(raw); - - break; - - case b11: - - if (l == b0) - result = armv7_read_thumb_32_instr_srs_thumb(raw); - - else - result = armv7_read_thumb_32_instr_rfe(raw); - - break; - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.6. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_thumb_32_load_store_dual_load_store_exclusive_table_branch(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t op1; /* Champ 'op1' à retrouver */ - uint32_t op2; /* Champ 'op2' à retrouver */ - uint32_t rn; /* Champ 'rn' à retrouver */ - uint32_t op3; /* Champ 'op3' à retrouver */ - - /** - * Suit les directives de : - * § A6.3.6 Load/store dual, load/store exclusive, table branch - */ - - if ((raw & 0xfe400000) != 0xe8400000) return NULL; - - result = NULL; - - op1 = (raw >> 23) & 0x3; - op2 = (raw >> 20) & 0x3; - rn = (raw >> 16) & 0xf; - op3 = (raw >> 4) & 0xf; - - if (op1 == b00 && op2 == b00) - result = armv7_read_thumb_32_instr_strex(raw); - - else if (op1 == b00 && op2 == b01) - result = armv7_read_thumb_32_instr_ldrex(raw); - - else if ((op1 & b10) == b00 && op2 == b10) - result = armv7_read_thumb_32_instr_strd_immediate(raw); - - else if ((op1 & b10) == b10 && (op2 & b01) == b00) - result = armv7_read_thumb_32_instr_strd_immediate(raw); - - else if ((op1 & b10) == b00 && op2 == b11) - { - if (rn != b1111) - result = armv7_read_thumb_32_instr_ldrd_immediate(raw); - - else/* if (rn == b1111)*/ - result = armv7_read_thumb_32_instr_ldrd_literal(raw); - - } - - else if ((op1 & b10) == b10 && (op2 & b01) == b01) - { - if (rn != b1111) - result = armv7_read_thumb_32_instr_ldrd_immediate(raw); - - else/* if (rn == b1111)*/ - result = armv7_read_thumb_32_instr_ldrd_literal(raw); - - } - - else if (op1 == b01 && op2 == b00) - switch (op3) - { - case b0100: - result = armv7_read_thumb_32_instr_strexb(raw); - break; - - case b0101: - result = armv7_read_thumb_32_instr_strexh(raw); - break; - - case b0111: - result = armv7_read_thumb_32_instr_strexd(raw); - break; - - } - - else if (op1 == b01 && op2 == b01) - switch (op3) - { - case b0000: - result = armv7_read_thumb_32_instr_tbb_tbh(raw); - break; - - case b0001: - result = armv7_read_thumb_32_instr_tbb_tbh(raw); - break; - - case b0100: - result = armv7_read_thumb_32_instr_ldrexb(raw); - break; - - case b0101: - result = armv7_read_thumb_32_instr_ldrexh(raw); - break; - - case b0111: - result = armv7_read_thumb_32_instr_ldrexd(raw); - break; - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.7. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_thumb_32_load_word(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t op1; /* Champ 'op1' à retrouver */ - uint32_t rn; /* Champ 'rn' à retrouver */ - uint32_t op2; /* Champ 'op2' à retrouver */ - - /** - * Suit les directives de : - * § A6.3.7 Load word - */ - - if ((raw & 0xfe700000) != 0xf8500000) return NULL; - - result = NULL; - - op1 = (raw >> 23) & b11; - rn = (raw >> 16) & b1111; - op2 = (raw >> 6) & b111111; - - switch (op1) - { - case b00: - - if (op2 == b000000 && rn != b1111) - result = armv7_read_thumb_32_instr_ldr_register_thumb(raw); - - else if ((op2 & b100100) == b100100 && rn != b1111) - result = armv7_read_thumb_32_instr_ldr_immediate_thumb(raw); - - else if ((op2 & b111100) == b110000 && rn != b1111) - result = armv7_read_thumb_32_instr_ldr_immediate_thumb(raw); - - else if ((op2 & b111100) == b111000 && rn != b1111) - result = armv7_read_thumb_32_instr_ldrt(raw); - - break; - - case b01: - if (rn != b1111) - result = armv7_read_thumb_32_instr_ldr_immediate_thumb(raw); - break; - - } - - if (result == NULL && (op1 & b10) == b00 && rn == b1111) - result = armv7_read_thumb_32_instr_ldr_literal(raw); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.8. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_thumb_32_load_halfword_memory_hints(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t op1; /* Champ 'op1' à retrouver */ - uint32_t rn; /* Champ 'rn' à retrouver */ - uint32_t rt; /* Champ 'rt' à retrouver */ - uint32_t op2; /* Champ 'op2' à retrouver */ - - /** - * Suit les directives de : - * § A6.3.8 Load halfword, memory hints - */ - - if ((raw & 0xfe700000) != 0xf8300000) return NULL; - - result = NULL; - - op1 = (raw >> 23) & 0x3; - rn = (raw >> 16) & 0xf; - rt = (raw >> 12) & 0xf; - op2 = (raw >> 6) & 0x3f; - - if (rn == b1111) - { - if ((op1 & b10) == b00) - { - if (rt != b1111) - result = armv7_read_thumb_32_instr_ldrh_literal(raw); - - else/* if (rt == b1111)*/ - result = armv7_read_thumb_32_instr_pld_literal(raw); - - } - - else/* if ((op1 & b10) == b10)*/ - { - if (rt != b1111) - result = armv7_read_thumb_32_instr_ldrsh_literal(raw); - - else/* if (rt == b1111)*/ - result = g_undef_instruction_new(IBS_NOP); - - } - - } - - else/* if (rn != b1111)*/ - { - if (op1 == b00) - { - if ((op2 & b100100) == b100100) - result = armv7_read_thumb_32_instr_ldrh_immediate_thumb(raw); - - else if ((op2 & b111100) == b110000 && rt != b1111) - result = armv7_read_thumb_32_instr_ldrh_immediate_thumb(raw); - - else if (op2 == b000000 && rt != b1111) - result = armv7_read_thumb_32_instr_ldrh_register(raw); - - else if ((op2 & b111100) == b111000) - result = armv7_read_thumb_32_instr_ldrht(raw); - - else if (op2 == b000000 && rt == b1111) - result = armv7_read_thumb_32_instr_pld_pldw_register(raw); - - else if ((op2 & b111100) == b110000 && rt == b1111) - result = armv7_read_thumb_32_instr_pld_pldw_immediate(raw); - - } - - else if (op1 == b01) - { - if (rt != b1111) - result = armv7_read_thumb_32_instr_ldrh_immediate_thumb(raw); - - else/* if (rt == b1111)*/ - result = armv7_read_thumb_32_instr_pld_pldw_immediate(raw); - - } - - else if (op1 == b10) - { - if ((op2 & b100100) == b100100) - result = armv7_read_thumb_32_instr_ldrsh_immediate(raw); - - else if ((op2 & b111100) == b110000 && rt != b1111) - result = armv7_read_thumb_32_instr_ldrsh_immediate(raw); - - else if (op2 == b000000 && rt != b1111) - result = armv7_read_thumb_32_instr_ldrsh_register(raw); - - else if ((op2 & b111100) == b111000) - result = armv7_read_thumb_32_instr_ldrsht(raw); - - else if (op2 == b000000 && rt == b1111) - result = g_undef_instruction_new(IBS_NOP); - - else if ((op2 & b111100) == b110000 && rt == b1111) - result = g_undef_instruction_new(IBS_NOP); - - } - - else if (op1 == b11) - { - if (rt != b1111) - result = armv7_read_thumb_32_instr_ldrsh_immediate(raw); - - else/* if (rt == b1111)*/ - result = g_undef_instruction_new(IBS_NOP); - - } - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.9. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_thumb_32_load_byte_memory_hints(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t op1; /* Champ 'op1' à retrouver */ - uint32_t rn; /* Champ 'rn' à retrouver */ - uint32_t rt; /* Champ 'rt' à retrouver */ - uint32_t op2; /* Champ 'op2' à retrouver */ - - /** - * Suit les directives de : - * § A6.3.9 Load byte, memory hints - */ - - if ((raw & 0xfe700000) != 0xf8100000) return NULL; - - result = NULL; - - op1 = (raw >> 23) & b11; - rn = (raw >> 16) & b1111; - rt = (raw >> 12) & b1111; - op2 = (raw >> 6) & b111111; - - if (op1 == b00 && op2 == b000000 && rn != b1111) - { - if (rt != b1111) - result = armv7_read_thumb_32_instr_ldrb_register(raw); - - else /*if (rt == b1111) */ - result = armv7_read_thumb_32_instr_pld_register(raw); - - } - - else if ((op1 & b10) == b00 && rn == b1111) - { - if (rt != b1111) - result = armv7_read_thumb_32_instr_ldrb_literal(raw); - - else /*if (rt == b1111) */ - result = armv7_read_thumb_32_instr_pld_literal(raw); - - } - - else if (op1 == b00 && (op2 & b100100) == b100100 && rn != b1111) - result = armv7_read_thumb_32_instr_ldrb_immediate_thumb(raw); - - else if (op1 == b00 && (op2 & b111100) == b110000 && rn != b1111) - { - if (rt != b1111) - result = armv7_read_thumb_32_instr_ldrb_immediate_thumb(raw); - - else /*if (rt == b1111) */ - result = armv7_read_thumb_32_instr_pld_immediate(raw); - - } - - else if (op1 == b00 && (op2 & b111100) == b111000 && rn != b1111) - result = armv7_read_thumb_32_instr_ldrbt(raw); - - else if (op1 == b01 && rn != b1111) - { - if (rt != b1111) - result = armv7_read_thumb_32_instr_ldrb_immediate_thumb(raw); - - else /*if (rt == b1111) */ - result = armv7_read_thumb_32_instr_pld_immediate(raw); - - } - - if (op1 == b10 && op2 == b000000 && rn != b1111) - { - if (rt != b1111) - result = armv7_read_thumb_32_instr_ldrsb_register(raw); - else /*if (rt == b1111) */ - result = armv7_read_thumb_32_instr_pli_register(raw); - } - - else if ((op1 & b10) == b10 && rn == b1111) - { - if (rt != b1111) - result = armv7_read_thumb_32_instr_ldrsb_literal(raw); - - else /*if (rt == b1111) */ - result = armv7_read_thumb_32_instr_pli_immediate_literal(raw); - - } - - else if (op1 == b10 && (op2 & b100100) == b100100 && rn != b1111) - result = armv7_read_thumb_32_instr_ldrsb_immediate(raw); - - else if (op1 == b10 && (op2 & b111100) == b110000 && rn != b1111) - { - if (rt != b1111) - result = armv7_read_thumb_32_instr_ldrsb_immediate(raw); - - else /*if (rt == b1111) */ - result = armv7_read_thumb_32_instr_pli_immediate_literal(raw); - - } - - else if (op1 == b10 && (op2 & b111100) == b111000 && rn != b1111) - result = armv7_read_thumb_32_instr_ldrsbt(raw); - - else if (op1 == b11 && rn != b1111) - { - if (rt != b1111) - result = armv7_read_thumb_32_instr_ldrsb_immediate(raw); - - else /*if (rt == b1111) */ - result = armv7_read_thumb_32_instr_pli_immediate_literal(raw); - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.10. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_thumb_32_store_single_data_item(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t op1; /* Champ 'op1' à retrouver */ - uint32_t op2; /* Champ 'op2' à retrouver */ - - /** - * Suit les directives de : - * § A6.3.10 Store single data item - */ - - if ((raw & 0xff100000) != 0xf8000000) return NULL; - - result = NULL; - - op1 = (raw >> 21) & b111; - op2 = (raw >> 6) & b111111; - - switch (op1) - { - case b000: - - if (op2 == b000000) - result = armv7_read_thumb_32_instr_strb_register(raw); - - else if ((op2 & b100100) == b100100) - result = armv7_read_thumb_32_instr_strb_immediate_thumb(raw); - - else if ((op2 & b111100) == b110000) - result = armv7_read_thumb_32_instr_strb_immediate_thumb(raw); - - else if ((op2 & b111100) == b111000) - result = armv7_read_thumb_32_instr_strbt(raw); - - break; - - case b001: - - if (op2 == b000000) - result = armv7_read_thumb_32_instr_strh_register(raw); - - else if ((op2 & b100100) == b100100) - result = armv7_read_thumb_32_instr_strh_immediate_thumb(raw); - - else if ((op2 & b111100) == b110000) - result = armv7_read_thumb_32_instr_strh_immediate_thumb(raw); - - else if ((op2 & b111100) == b111000) - result = armv7_read_thumb_32_instr_strht(raw); - - break; - - case b010: - - if (op2 == b000000) - result = armv7_read_thumb_32_instr_str_register(raw); - - else if ((op2 & b100100) == b100100) - result = armv7_read_thumb_32_instr_str_immediate_thumb(raw); - - else if ((op2 & b111100) == b110000) - result = armv7_read_thumb_32_instr_str_immediate_thumb(raw); - - else if ((op2 & b111100) == b111000) - result = armv7_read_thumb_32_instr_strt(raw); - - break; - - case b100: - result = armv7_read_thumb_32_instr_strb_immediate_thumb(raw); - break; - - case b101: - result = armv7_read_thumb_32_instr_strh_immediate_thumb(raw); - break; - - case b110: - result = armv7_read_thumb_32_instr_str_immediate_thumb(raw); - break; - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.11. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_thumb_32_data_processing_shifted_register(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t op; /* Champ 'op' à retrouver */ - uint32_t rn; /* Champ 'rn' à retrouver */ - uint32_t rds; /* Champ 'rds' à retrouver */ - - /** - * Suit les directives de : - * § A6.3.11 Data-processing (shifted register) - */ - - if ((raw & 0xfe000000) != 0xea000000) return NULL; - - result = NULL; - - op = (raw >> 21) & b1111; - rn = (raw >> 16) & b1111; - rds = (((raw >> 8) & b1111) << 1) | ((raw >> 20) & b1); - - switch (op) - { - case b0000: - - if (rds == b11111) - result = armv7_read_thumb_32_instr_tst_register(raw); - - else - result = armv7_read_thumb_32_instr_and_register(raw); - - break; - - case b0001: - result = armv7_read_thumb_32_instr_bic_register(raw); - break; - - case b0010: - - if (rn == b11111) - result = process_armv7_thumb_32_move_register_and_immediate_shifts(raw); - - else - result = armv7_read_thumb_32_instr_orr_register(raw); - - break; - - case b0011: - - if (rn == b11111) - result = armv7_read_thumb_32_instr_mvn_register(raw); - - else - result = armv7_read_thumb_32_instr_orn_register(raw); - - break; - - case b0100: - - if (rds == b11111) - result = armv7_read_thumb_32_instr_teq_register(raw); - - else - result = armv7_read_thumb_32_instr_eor_register(raw); - - break; - - case b0110: - result = armv7_read_thumb_32_instr_pkh(raw); - break; - - case b1000: - - if (rds == b11111) - result = armv7_read_thumb_32_instr_cmn_register(raw); - - else - result = armv7_read_thumb_32_instr_add_register_thumb(raw); - - break; - - case b1010: - result = armv7_read_thumb_32_instr_adc_register(raw); - break; - - case b1011: - result = armv7_read_thumb_32_instr_sbc_register(raw); - break; - - case b1101: - - if (rds == b11111) - result = armv7_read_thumb_32_instr_cmp_register(raw); - - else - result = armv7_read_thumb_32_instr_sub_register_thumb(raw); - - break; - - case b1110: - result = armv7_read_thumb_32_instr_rsb_register(raw); - break; - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.11b.* -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_thumb_32_move_register_and_immediate_shifts(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t imm5; /* Champs 'imm[32]' à retrouver*/ - uint32_t type; /* Champ 'type' à retrouver */ - - /** - * Suit les directives de : - * § A6.3.11 Data-processing (shifted register) - * |-> Move register and immediate shifts - */ - - if ((raw & 0xffef0000) != 0xea4f0000) return NULL; - - result = NULL; - - imm5 = (((raw >> 12) & 0x7) << 2) | ((raw >> 6) & 0x3); - type = (raw >> 4) & 0x3; - - switch (type) - { - case b00: - - if (imm5 == b00000) - result = armv7_read_thumb_32_instr_mov_register_thumb(raw); - - else/* if (imm5 != b00000)*/ - result = armv7_read_thumb_32_instr_lsl_immediate(raw); - - break; - - case b01: - result = armv7_read_thumb_32_instr_lsr_immediate(raw); - break; - - case b10: - result = armv7_read_thumb_32_instr_asr_immediate(raw); - break; - - case b11: - - if (imm5 == b00000) - result = armv7_read_thumb_32_instr_rrx(raw); - - else/* if (imm5 != b00000)*/ - result = armv7_read_thumb_32_instr_ror_immediate(raw); - - break; - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.12. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_thumb_32_data_processing_register(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t op1; /* Champ 'op1' à retrouver */ - uint32_t rn; /* Champ 'rn' à retrouver */ - uint32_t op2; /* Champ 'op2' à retrouver */ - - /** - * Suit les directives de : - * § A6.3.12 Data-processing (register) - */ - - if ((raw & 0xff00f000) != 0xfa00f000) return NULL; - - result = NULL; - - op1 = (raw >> 20) & b1111; - rn = (raw >> 16) & b1111; - op2 = (raw >> 4) & b1111; - - if ((op1 & b1110) == b0000 && op2 == b0000) - result = armv7_read_thumb_32_instr_lsl_register(raw); - - else if ((op1 & b1110) == b0010 && op2 == b0000) - result = armv7_read_thumb_32_instr_lsr_register(raw); - - else if ((op1 & b1110) == b0100 && op2 == b0000) - result = armv7_read_thumb_32_instr_asr_register(raw); - - else if ((op1 & b1110) == b0110 && op2 == b0000) - result = armv7_read_thumb_32_instr_ror_register(raw); - - else if (op1 == b0000 && (op2 & b1000) == b1000) - { - if (rn == b1111) - result = armv7_read_thumb_32_instr_sxth(raw); - - else - result = armv7_read_thumb_32_instr_sxtah(raw); - - } - - else if (op1 == b0001 && (op2 & b1000) == b1000) - { - if (rn == b1111) - result = armv7_read_thumb_32_instr_uxth(raw); - - else - result = armv7_read_thumb_32_instr_uxtah(raw); - - } - - else if (op1 == b0010 && (op2 & b1000) == b1000) - { - if (rn == b1111) - result = armv7_read_thumb_32_instr_sxtb16(raw); - - else - result = armv7_read_thumb_32_instr_sxtab16(raw); - - } - - else if (op1 == b0011 && (op2 & b1000) == b1000) - { - if (rn == b1111) - result = armv7_read_thumb_32_instr_uxtb16(raw); - - else - result = armv7_read_thumb_32_instr_uxtab16(raw); - - } - - else if (op1 == b0100 && (op2 & b1000) == b1000) - { - if (rn == b1111) - result = armv7_read_thumb_32_instr_sxtb(raw); - - else - result = armv7_read_thumb_32_instr_sxtab(raw); - - } - - else if (op1 == b0101 && (op2 & b1000) == b1000) - { - if (rn == b1111) - result = armv7_read_thumb_32_instr_uxtb(raw); - - else - result = armv7_read_thumb_32_instr_uxtab(raw); - - } - - else if ((op1 & b1000) == b1000 && (op2 & b1100) == b0000) - result = process_armv7_thumb_32_parallel_addition_and_subtraction_signed(raw); - - else if ((op1 & b1000) == b1000 && (op2 & b1100) == b0100) - result = process_armv7_thumb_32_parallel_addition_and_subtraction_unsigned(raw); - - else if ((op1 & b1100) == b1000 && (op2 & b1100) == b1000) - result = process_armv7_thumb_32_miscellaneous_operations(raw); - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.13. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_thumb_32_parallel_addition_and_subtraction_signed(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t op1; /* Champ 'op1' à retrouver */ - uint32_t op2; /* Champ 'op2' à retrouver */ - - /** - * Suit les directives de : - * § A6.3.13 Parallel addition and subtraction, signed - */ - - if ((raw & 0xff80f000) != 0xfa80f000) return NULL; - - result = NULL; - - op1 = (raw >> 20) & b111; - op2 = (raw >> 4) & b11; - - switch (op2) - { - case b00: - switch (op1) - { - case b001: - result = armv7_read_thumb_32_instr_sadd16(raw); - break; - - case b010: - result = armv7_read_thumb_32_instr_sasx(raw); - break; - - case b110: - result = armv7_read_thumb_32_instr_ssax(raw); - break; - - case b101: - result = armv7_read_thumb_32_instr_ssub16(raw); - break; - - case b000: - result = armv7_read_thumb_32_instr_sadd8(raw); - break; - - case b100: - result = armv7_read_thumb_32_instr_ssub8(raw); - break; - - } - break; - - case b01: - switch (op1) - { - case b001: - result = armv7_read_thumb_32_instr_sqadd16(raw); - break; - - case b010: - result = armv7_read_thumb_32_instr_sqasx(raw); - break; - - case b110: - result = armv7_read_thumb_32_instr_sqsax(raw); - break; - - case b101: - result = armv7_read_thumb_32_instr_sqsub16(raw); - break; - - case b000: - result = armv7_read_thumb_32_instr_sqadd8(raw); - break; - - case b100: - result = armv7_read_thumb_32_instr_sqsub8(raw); - break; - - } - break; - - case b10: - switch (op1) - { - case b001: - result = armv7_read_thumb_32_instr_shadd16(raw); - break; - - case b010: - result = armv7_read_thumb_32_instr_shasx(raw); - break; - - case b110: - result = armv7_read_thumb_32_instr_shsax(raw); - break; - - case b101: - result = armv7_read_thumb_32_instr_shsub16(raw); - break; - - case b000: - result = armv7_read_thumb_32_instr_shadd8(raw); - break; - - case b100: - result = armv7_read_thumb_32_instr_shsub8(raw); - break; - - } - break; - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.14. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_thumb_32_parallel_addition_and_subtraction_unsigned(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t op1; /* Champ 'op1' à retrouver */ - uint32_t op2; /* Champ 'op2' à retrouver */ - - /** - * Suit les directives de : - * § A6.3.14 Parallel addition and subtraction, unsigned - */ - - if ((raw & 0xff80f0c0) != 0xfa80f040) return NULL; - - result = NULL; - - op1 = (raw >> 20) & b111; - op2 = (raw >> 4) & b11; - - switch (op2) - { - case b00: - switch (op1) - { - case b001: - result = armv7_read_thumb_32_instr_uadd16(raw); - break; - - case b010: - result = armv7_read_thumb_32_instr_uasx(raw); - break; - - case b110: - result = armv7_read_thumb_32_instr_usax(raw); - break; - - case b101: - result = armv7_read_thumb_32_instr_usub16(raw); - break; - - case b000: - result = armv7_read_thumb_32_instr_uadd8(raw); - break; - - case b100: - result = armv7_read_thumb_32_instr_usub8(raw); - break; - - } - break; - - case b01: - switch (op1) - { - case b001: - result = armv7_read_thumb_32_instr_uqadd16(raw); - break; - - case b010: - result = armv7_read_thumb_32_instr_uqasx(raw); - break; - - case b110: - result = armv7_read_thumb_32_instr_uqsax(raw); - break; - - case b101: - result = armv7_read_thumb_32_instr_uqsub16(raw); - break; - - case b000: - result = armv7_read_thumb_32_instr_uqadd8(raw); - break; - - case b100: - result = armv7_read_thumb_32_instr_uqsub8(raw); - break; - - } - break; - - case b10: - switch (op1) - { - case b001: - result = armv7_read_thumb_32_instr_uhadd16(raw); - break; - - case b010: - result = armv7_read_thumb_32_instr_uhasx(raw); - break; - - case b110: - result = armv7_read_thumb_32_instr_uhsax(raw); - break; - - case b101: - result = armv7_read_thumb_32_instr_uhsub16(raw); - break; - - case b000: - result = armv7_read_thumb_32_instr_uhadd8(raw); - break; - - case b100: - result = armv7_read_thumb_32_instr_uhsub8(raw); - break; - - } - break; - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.15. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_thumb_32_miscellaneous_operations(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t op1; /* Champ 'op1' à retrouver */ - uint32_t op2; /* Champ 'op2' à retrouver */ - - /** - * Suit les directives de : - * § A6.3.15 Miscellaneous operations - */ - - if ((raw & 0xffc0f0c0) != 0xfa80f080) return NULL; - - result = NULL; - - op1 = (raw >> 20) & b11; - op2 = (raw >> 4) & b11; - - switch (op1) - { - case b00: - switch (op2) - { - case b00: - result = armv7_read_thumb_32_instr_qadd(raw); - break; - - case b01: - result = armv7_read_thumb_32_instr_qdadd(raw); - break; - - case b10: - result = armv7_read_thumb_32_instr_qsub(raw); - break; - - case b11: - result = armv7_read_thumb_32_instr_qdsub(raw); - break; - - } - break; - - case b01: - switch (op2) - { - case b00: - result = armv7_read_thumb_32_instr_rev(raw); - break; - - case b01: - result = armv7_read_thumb_32_instr_rev16(raw); - break; - - case b10: - result = armv7_read_thumb_32_instr_rbit(raw); - break; - - case b11: - result = armv7_read_thumb_32_instr_revsh(raw); - break; - - } - break; - - case b10: - if (op2 == b00) - result = armv7_read_thumb_32_instr_sel(raw); - break; - - case b11: - if (op2 == b00) - result = armv7_read_thumb_32_instr_clz(raw); - break; - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.16. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_thumb_32_multiply_multiply_accumulate_and_absolute_difference(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t op1; /* Champ 'op1' à retrouver */ - uint32_t ra; /* Champ 'ra' à retrouver */ - uint32_t op2; /* Champ 'op2' à retrouver */ - - /** - * Suit les directives de : - * § A6.3.16 Multiply, multiply accumulate, and absolute difference - */ - - if ((raw & 0xff8000c0) != 0xfb000000) return NULL; - - result = NULL; - - op1 = (raw >> 20) & b111; - ra = (raw >> 12) & b1111; - op2 = (raw >> 4) & b11; - - switch (op1) - { - case b000: - - if (op2 == b00) - { - if (ra == b1111) - result = armv7_read_thumb_32_instr_mul(raw); - - else - result = armv7_read_thumb_32_instr_mla(raw); - - } - - else if (op2 == b01) - result = armv7_read_thumb_32_instr_mls(raw); - - break; - - case b001: - - if (ra == b1111) - result = armv7_read_thumb_32_instr_smulbb_smulbt_smultb_smultt(raw); - - else - result = armv7_read_thumb_32_instr_smlabb_smlabt_smlatb_smlatt(raw); - - break; - - case b010: - if ((op2 & b10) == b00) - { - if (ra == b1111) - result = armv7_read_thumb_32_instr_smuad(raw); - - else - result = armv7_read_thumb_32_instr_smlad(raw); - - } - break; - - case b011: - if ((op2 & b10) == b00) - { - if (ra == b1111) - result = armv7_read_thumb_32_instr_smulwb_smulwt(raw); - - else - result = armv7_read_thumb_32_instr_smlawb_smlawt(raw); - - } - break; - - case b100: - if ((op2 & b10) == b00) - { - if (ra == b1111) - result = armv7_read_thumb_32_instr_smusd(raw); - - else - result = armv7_read_thumb_32_instr_smlsd(raw); - - } - break; - - case b101: - if ((op2 & b10) == b00) - { - if (ra == b1111) - result = armv7_read_thumb_32_instr_smmul(raw); - - else - result = armv7_read_thumb_32_instr_smmla(raw); - - } - break; - - case b110: - if ((op2 & b10) == b00) - result = armv7_read_thumb_32_instr_smmls(raw); - break; - - case b111: - if (op2 == b00) - { - if (ra == b1111) - result = armv7_read_thumb_32_instr_usad8(raw); - - else - result = armv7_read_thumb_32_instr_usada8(raw); - - } - break; - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.17. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_thumb_32_long_multiply_long_multiply_accumulate_and_divide(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t op1; /* Champ 'op1' à retrouver */ - uint32_t op2; /* Champ 'op2' à retrouver */ - - /** - * Suit les directives de : - * § A6.3.17 Long multiply, long multiply accumulate, and divide - */ - - if ((raw & 0xff800000) != 0xfb800000) return NULL; - - result = NULL; - - op1 = (raw >> 20) & b111; - op2 = (raw >> 4) & b1111; - - switch (op1) - { - case b000: - if (op2 == b0000) - result = armv7_read_thumb_32_instr_smull(raw); - break; - - case b001: - if (op2 == b1111) - result = armv7_read_thumb_32_instr_sdiv(raw); - break; - - case b010: - if (op2 == b0000) - result = armv7_read_thumb_32_instr_umull(raw); - break; - - case b011: - if (op2 == b1111) - result = armv7_read_thumb_32_instr_udiv(raw); - break; - - case b100: - - if (op2 == b0000) - result = armv7_read_thumb_32_instr_smlal(raw); - - else if ((op2 & b1100) == b1000) - result = armv7_read_thumb_32_instr_smlalbb_smlalbt_smlaltb_smlaltt(raw); - - else if ((op2 & b1110) == b1100) - result = armv7_read_thumb_32_instr_smlald(raw); - - break; - - case b101: - if ((op2 & b1110) == b1100) - result = armv7_read_thumb_32_instr_smlsld(raw); - break; - - case b110: - - if (op2 == b0000) - result = armv7_read_thumb_32_instr_umlal(raw); - - else if (op2 == b0110) - result = armv7_read_thumb_32_instr_umaal(raw); - - break; - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : raw = donnée brute de 32 bits à désassembler. * -* * -* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.18. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *process_armv7_thumb_32_coprocessor_advanced_simd_and_floating_point_instructions(uint32_t raw) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint32_t op1; /* Champ 'op1' à retrouver */ - uint32_t rn; /* Champ 'rn' à retrouver */ - uint32_t coproc; /* Champ 'coproc' à retrouver */ - uint32_t op; /* Champ 'op' à retrouver */ - - /** - * Suit les directives de : - * § A6.3.18 Coprocessor, Advanced SIMD, and Floating-point instructions - */ - - if ((raw & 0xec000000) != 0xec000000) return NULL; - - result = NULL; - - op1 = (raw >> 20) & 0x3f; - rn = (raw >> 16) & 0xf; - coproc = (raw >> 8) & 0xf; - op = (raw >> 4) & 0x1; - - if ((op1 & b111110) == b000000) - result = g_undef_instruction_new(IBS_UNDEFINED); - - else if ((op1 & b110000) == b110000) - result = process_armv7_simd_advanced_simd_data_processing_instructions(raw, false); - - else if ((coproc & b1110) != b1010) - { - if ((op1 & b100001) == b000000 && (op1 & b111010) != b000000) - result = armv7_read_thumb_32_instr_stc_stc2(raw); - - else if ((op1 & b100001) == b000001 && (op1 & b111010) != b000000) - { - if (rn != b1111) - result = armv7_read_thumb_32_instr_ldc_ldc2_immediate(raw); - - else/* if (rn == b1111)*/ - result = armv7_read_thumb_32_instr_ldc_ldc2_literal(raw); - - } - - else if (op1 == b000100) - result = armv7_read_thumb_32_instr_mcrr_mcrr2(raw); - - else if (op1 == b000101) - result = armv7_read_thumb_32_instr_mrrc_mrrc2(raw); - - else if ((op1 & b110000) == b100000 && op == b0) - result = armv7_read_thumb_32_instr_cdp_cdp2(raw); - - else if ((op1 & b110001) == b100000 && op == b1) - result = armv7_read_thumb_32_instr_mcr_mcr2(raw); - - else if ((op1 & b110001) == b100001 && op == b1) - result = armv7_read_thumb_32_instr_mrc_mrc2(raw); - - } - - else if ((coproc & b1110) == b1010) - { - if ((op1 & b100000) == b000000 && (op1 & b111010) != b000000) - result = process_armv7_simd_extension_register_load_store_instructions(raw, false); - - else if ((op1 & b111110) == b000100) - result = process_armv7_simd_64_bit_transfers_between_arm_core_and_extension_registers(raw, false); - - else if ((op1 & b110000) == b100000) - { - if (op == b0) - result = process_armv7_simd_floating_point_data_processing_instructions(raw, false); - - else/* if (op == b1)*/ - result = process_armv7_simd_8_16_and_32_bit_transfer_between_arm_core_and_extension_registers(raw, false); - - } - - } - - return result; - -} diff --git a/src/arch/arm/v7/thumb_32.h b/src/arch/arm/v7/thumb_32.h deleted file mode 100644 index 9d09650..0000000 --- a/src/arch/arm/v7/thumb_32.h +++ /dev/null @@ -1,37 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * thumb_32.h - prototypes pour le désassemblage des instructions ARMv7 Thumb 32 bits - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_ARM_V7_THUMB_32_H -#define _ARCH_ARM_V7_THUMB_32_H - - -#include "../../instruction.h" - - - -/* Désassemble une instruction ARMv7 liées au chapitre A6.3. */ -GArchInstruction *process_armv7_thumb_32_instruction_set_encoding(uint32_t); - - - -#endif /* _ARCH_ARM_V7_THUMB_32_H */ |